DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/22/2026 is being considered by the examiner.
Response to Amendment
An Amendment filed on 07/22/2026, responding to the Office Action mailed on 04/29/2026, has been acknowledged and entered into the record. The present Final Rejection is made with all the
suggested amendments being fully considered.
Response to Arguments
On pages 10-11 of the remarks filed on 07/22/2026, with respect to the 102 rejection of independent Claims 1 and 8, Applicant argues that in Lai, the side of the insulating protection layer 25 facing the semiconductor element 20 has a shape complementary to the side of the encapsulation layer 23 and the semiconductor element 20 facing away from the active surface of the semiconductor element 20 and is not configured with an accommodation cavity for accommodating the semiconductor element 20 but rather includes portions corresponding to the openings 230 and the slots 231 and thus, Lai fails to disclose at least "a second encapsulation layer covering the first encapsulation layer and the embedded wiring layer, wherein an accommodation cavity is formed in a region of the second encapsulation layer corresponding to the chip," as recited in claim 1. These arguments are fully considered but are not persuasive. According to Fig. 2E of Lai, the second encapsulation layer 25 is conformally formed around the chip 20 and therefore inherently defines an accommodation cavity corresponding to the outer geometry of the chip 20. Even though portions of the second encapsulation layer 25 also conform to the openings 230 and slots 231 in the first encapsulation layer 23 disposed beneath it, these contours merely reflect the underlying topography over which the second encapsulation layer 25 is molded and thus, do not alter the fundamental structure of the second encapsulation layer 25 as defining a cavity that accommodates the chip. In other words, the fact that the second encapsulation layer 25 assumes the shape of the openings 230 and slots 231 in the first encapsulation layer 23 does not preclude, and indeed is consistent with, the second encapsulation layer 25 inherently forming an accommodation cavity by virtue of being conformally formed over chip 20. Further note that this arrangement is similarly to the present disclosure, in which the second encapsulation layer 7 is also conformally deposited around the chip 1 (see Fig. 10 and paragraph 0076 in originally filed disclosure). Therefore, the rejection of Claims 1, 8 and their dependents is maintained.
On page 11 of the remarks filed on 07/22/2026, with respect to the 102 rejection of independent Claims 1 and 8, Applicant argues that Lai seeks to address the problem of low yield caused by forming openings in an encapsulation layer around a semiconductor element by laser processing avoiding the need to form the openings after the encapsulation layer has been formed and thus, Lai's disclosed solution does not involve forming an accommodation cavity in the insulating protection layer for accommodating the chip. These arguments are fully considered but are not persuasive. As mentioned earlier, the second encapsulation layer 25 is conformally formed around the chip 20 and therefore inherently defines an accommodation cavity corresponding to the outer geometry of the chip 20. Even though Lai discusses providing openings in the encapsulation layer for addressing a particular design objective and does not expressly identify providing an accommodation cavity as a solution to the problem, Lai’s disclosure does not teach away from, or otherwise preclude the second encapsulation layer 25 inherently forming the claimed accommodation cavity. Therefore, the rejection of Claims 1, 8 and their dependents is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 8, 9, 11, 12, 15 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (CN 105321894 A).
Regarding Claim 1, Lai et al. discloses a semiconductor packaging method, comprising:
providing a chip 20 (Fig. 2A: 20, page 7, lines 11-13 in English Translation of Lai et al.);
forming a first encapsulation layer 23 surrounding the chip 20 (Fig. 2D: 23, 20, page 7, lines 29-33 in English Translation of Lai et al.);
forming an embedded wiring layer 24 at least on a side 23b of the first encapsulation layer 23 (Fig. 2E: 24, 23, 23b, page 8, lines 18-20 in English Translation of Lai et al.);
forming a second encapsulation layer 25 covering the first encapsulation layer 23 and the embedded wiring layer 24, wherein an accommodation cavity is formed in a region of the second encapsulation layer 24 corresponding to the chip 20 (Fig. 2E: 25, 23, 24, 20, page 8, lines 24-27 in English Translation of Lai et al.);
Note that according to Fig. 2E, the second encapsulation layer 25 is deposited around the chip 20 and therefore the deposition would inherently form a cavity configured to accommodate the chip 20. Further note that this arrangement is similarly to the present disclosure, in which the second encapsulation layer 7 is conformally deposited around the chip 1 (see Fig. 10: 1, 7 and paragraph 0076 in originally filed disclosure).
and forming a fan-out wiring layer 260 on a surface 23a of the first encapsulation layer 23 away from the second encapsulation layer 25, wherein the fan-out wiring layer 260 is electrically connected to the embedded wiring layer 24 and a pin 200 of the chip 20 (Fig. 2G: 260, 23a, 23, 25, 24, 200, 20, page 9, lines 3-8 in English Translation of Lai et al.).
Regarding Claim 2, Lai et al. discloses the semiconductor packaging method of claim 1,
wherein forming the first encapsulation layer surrounding the chip comprises:
providing a carrier plate 21 (Fig. 2A: 21, page 7, lines 11-13 in English Translation of Lai et al.),
forming the first encapsulation layer 23 on the carrier plate 21 (Fig. 2D: 23, 21, page 8, lines 9-10 in English Translation of Lai et al.),
and attaching the chip 20 onto the first encapsulation layer 22/23 (Fig. 2B: 20, 22, Fig. 2C: 20, 23, page 7, lines 26-28, lines 29-33),
wherein the first encapsulation layer 23 surrounds the chip and a back surface 20b of the chip 20 is away from the carrier plate 21 (Fig. 2A: 21, 20b, 20, 23, page 7, lines 11-13 in English Translation of Lai et al.);
forming the embedded wiring layer 24 at least on a side 23b of the first encapsulation layer 23 comprises:
forming the embedded wiring layer 24 at least on a side 23b of the first encapsulation layer 23 away from the carrier plate 21 (Fig. 2E: 24, 23, 23b, 21, page 8, lines 18-20 in English Translation of Lai et al.);
forming the fan-out wiring layer 260 on the surface 23a of the first encapsulation layer 23 away from the second encapsulation layer 24 comprises:
removing the carrier plate 21 (Fig. 2E-2F: 21, page 8, lines 36-38 in English Translation of Lai et al.),
and forming the fan-out wiring layer 260 on the surface 23a of the first encapsulation layer 23 away from the second encapsulation layer 25 (Fig. 2F-2G: 21, 260, 23a, 23, 24, page 8, lines 36-38, page 9, lines 3-8 in English Translation of Lai et al.).
Regarding Claim 4, Lai et al. discloses the semiconductor packaging method of claim 1, wherein forming the embedded wiring layer 24 at least on a side 23b of the first encapsulation layer 23 comprises:
forming a plurality of via-holes 230 in the first encapsulation layer 23, and forming the embedded wiring layer 24 at a side 23b of the first encapsulation layer 23 and in the via-holes 230 (Fig. 2D-2E: 230, 23, 24, 23b, page 10, lines 6-12 in English Translation of Lai et al.);
or forming a recess in the first encapsulation layer, forming a plurality of via-holes in a bottom wall of the recess, and forming the embedded wiring layer in the recess and the via-holes to fill the recess and the via-holes;
or forming a recess in the first encapsulation layer, forming a plurality of via-holes in a bottom wall of the recess, forming a stepped stair structure on a sidewall of the recess, and forming the embedded wiring layer in the recess and the via-holes to cover the bottom wall of the recess and fill the via-holes.
Regarding Claim 5, Lai et al. discloses the semiconductor packaging method of claim 3,
wherein the fan-out wiring layer 260 further comprises: a third fan-out line 260-3, disposed on a surface 23a of the first encapsulation layer 23 away from the second encapsulation layer 25 and electrically connected to the embedded line 24 (see annotated Fig. 2G: 260-3, 23, 23a, 25, 24);
the semiconductor packaging method further comprises: forming a conductive column layer C1, C2, wherein the conductive column layer C1, C2 comprises a first conductive column C1 and a second conductive column C2, the first conductive column C1 is disposed on a surface of the third fan-out line 260-3 away from the second encapsulation layer 25 and electrically connected to the third fan-out line 260-3, and the second conductive column C2 is disposed on a surface of the second fan-out line 26-2 away from the second encapsulation layer 25 and electrically connected to the second fan-out line 26-2 (see annotated Fig. 2G: C1, C2, 260-3, 260-2);
and forming a dielectric layer covering the fan-out wiring layer 260 and the first encapsulation layer 23, wherein the dielectric layer surrounds the first conductive column C1 and the second conductive column C2 (see annotated Fig. 2G: dielectric layer, 260, C1, C2).
Note that a dielectric layer is inherently present between adjacent fan-out layers 260 of Fig. 2G, even if not explicitly shown or described, as such insulation is necessary for proper electrical isolation and would be recognized by a person of ordinary skill in the art.
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Annotated Fig. 2G of Lai et al. (CN 105321894 A)
Regarding Claim 6, Lai et al. discloses the semiconductor packaging method of claim 1, wherein forming the first encapsulation layer 23 surrounding the chip 20 comprises:
forming the first encapsulation layer 22/23 (Fig. 2B: 22, Fig..2C: 23;
forming a first window in the first encapsulation layer 22/23 (Fig. 2B-2B’: 22, page 7, lines 29-33);
Note that the positioning blocks 91 corresponding to the mold 9a of Fig. 2B and Fig. 2B’ will produce a window in the encapsulation layer 22/23 (see also annotated Fig. 2G).
and disposing the chip 20 in the first window (Fig. 2B’, annotated Fig. 2G).
Regarding Claim 8, Lai et al. discloses a semiconductor packaging structure, comprising:
a chip 20 (Fig. 2E: 20, page 7, lines 11-13 in English Translation of Lai et al.);
a packaging body 2, packaging the chip 20 and comprising a first encapsulation layer 23 and a second encapsulation 25 layer stacked (Fig. 2E: 20, 23, 25, Fig. 3: 2, page 7, lines 29-33, page 8, lines 24-27 in English Translation of Lai et al.);
an embedded wiring layer 24, disposed between the first encapsulation layer 23 and the second encapsulation layer 25 (Fig. 2E: 24, 23, 25, page 8, lines 18-20 in English Translation of Lai et al.);
and a fan-out wiring layer 260, disposed on a surface of the first encapsulation layer 23a away from the second encapsulation layer 25, and electrically connected to the embedded wiring layer 24 and a pin 200 of the chip 20 (Fig. 2G: 260, 23a, 23, 25, 24, 200, 20, page 9, lines 3-8 in English Translation of Lai et al.);
wherein an accommodation cavity is formed in a region of the second encapsulation layer 25 corresponding to the chip 20, and the chip 20 is disposed in the accommodation cavity (see annotated Fig. 2G: accommodation cavity, 25, 20).
Note that according to Fig. 2E, the second encapsulation layer 25 is deposited around the chip 20 and therefore the deposition would inherently form a cavity configured to accommodate the chip 20. Further note that this arrangement is similarly to the present disclosure, in which the second encapsulation layer 7 is conformally deposited around the chip 1 (see Fig. 10 and paragraph 0076 in originally filed disclosure).
Regarding Claim 9, Lai et al. discloses the semiconductor packaging structure of claim 8, wherein: a front surface 20a of the chip 20 is away from the accommodation cavity and located outside the accommodation cavity; and the embedded wiring layer 24 is disposed in a region outside the accommodation cavity (see annotated Fig. 2G: accommodation cavity, 24, 20, Fig. 2F: 20a, 24).
Regarding Claim 11, Lai et al. discloses the semiconductor packaging structure of claim 10, further comprising:
a dielectric layer, disposed at a side 23a of the first encapsulation layer 23 away from the second encapsulation layer 25, and covering the fan-out wiring layer 260 (see annotated Fig. 2G: dielectric layer, 260, 23a, 23, 25);
Note that a dielectric layer is inherently present between adjacent fan-out layers 260 of Fig. 2G, even if not explicitly shown or described, as such insulation is necessary for proper electrical isolation and would be recognized by a person of ordinary skill in the art.
and a conductive column layer C1, C2, at least partially formed in the dielectric layer, wherein the conductive column layer C1, C2 comprises a first conductive column C1 and a second conductive column C2, the first conductive column C1 is electrically connected to the embedded line 24, and the second conductive column C2 is electrically connected to the second fan-out line 260-2 (See annotated Fig. 2G: C1, C2, 260-2, 24).
Regarding Claim 12, Lai et al. discloses the semiconductor packaging structure of claim 8, wherein a plurality of via-holes 230 are provided in the first encapsulation layer 23, and the embedded wiring layer 24 fills the via-holes 230 (Fig. 2D-2E: 230, 23, 24, 23b, page 10, lines 6-12 in English Translation of Lai et al.);
or, a recess is provided in the first encapsulation layer, a plurality of via-holes are provided in a bottom wall of the recess, and the embedded wiring layer is formed in the recess and the via- holes to fill the recess and the via-holes ;
or, a recess is provided in the first encapsulation layer, a plurality of via-holes are provided in a bottom wall of the recess, and a stepped stair structure is provided in a sidewall of the recess; the embedded wiring layer is formed in the recess and the via-holes to cover the bottom wall of the recess and fill the via-holes.
Regarding Claim 15, Lai et al. discloses the semiconductor packaging structure of claim 11, wherein the fan-out wiring layer 260 further comprises a third fan-out line 260-3, which is disposed on a surface 23a of the first encapsulation layer 23 away from the second encapsulation layer 25 and electrically connected to the embedded line 24 and the first conductive column C1 (see annotated Fig. 2G: 260, 260-3, C1, 24).
Regarding Claim 16, Lai et al. discloses the semiconductor packaging structure of claim 8, wherein a first window is formed in the first encapsulation layer 23, and the chip 20 is disposed in the first window (see annotated Fig. 2G: first window, Fig. 2B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference Lai et al., but disclosed in the secondary reference(s).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (CN 105321894 A), as applied to Claim 1 above, further in view of Chew (CN 109509727 A).
Regarding Claim 3, Lai et al. discloses the semiconductor packaging method of claim 1,
wherein the pin 200 of the chip 20 comprises a first pin 200-1 and a second pin 200-2 (see annotated Fig. 2G: 20, 200-1, 200-2),
the embedded wiring layer 24 comprises an embedded line 24 (see annotated Fig. 2G: 24),
and the fan-out wiring layer 260 comprises:
a first fan-out line 260-1, electrically connected to the embedded line 24 and the first pin 200-1 of the chip 20 (see annotated Fig. 2G: 200-1, 260-1, 24);
and a second fan-out line 260-2, insulated from the first fan-out line 260-1 and electrically connected to the second pin 200-2 of the chip 20 (see annotated Fig. 2G: 200-2, 260-1, 260-2, 20).
Chew discloses a semiconductor packaging method comprising the following claim limitation not disclosed in Lai et al.
a first fan-out line 603, electrically connected to the embedded line 400 and the first pin of the chip 300 (see annotated Fig. 13: 400, 603, page 10, lines 22-32 in in English Translation of Chew)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Lai et al. with the teachings of Chew in order to have the first fan-out line, electrically connected to the embedded line and the first pin of the chip. Doing so would allow access to additional wiring layers on different layers without crossing over other metal traces in the semiconductor package.
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Annotated Fig. 2G of Chew (CN 109509727 A)
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (CN 105321894 A), as applied to Claim 1 above, further in view of Chiu et al. (US 20160079151 A1).
Regarding Claim 7, Lai et al. fails to disclose the semiconductor packaging method of claim 1, wherein forming the embedded wiring layer at least on a side of the first encapsulation layer comprises: forming a photoresist layer covering the first encapsulation layer; and patterning the photoresist layer to form a second widow in the photoresist layer, and disposing the embedded wiring layer in a region of the first encapsulation layer corresponding to the second window.
However, Chiu et al. teaches a semiconductor packaging method, wherein forming the embedded wiring layer 304 at least on a side of the first layer 302 comprises: forming a photoresist layer 303 covering the first layer 302; and patterning the photoresist layer 303 to form a second window in the photoresist layer 303, and disposing the embedded wiring layer 304 in a region of the first layer 302 corresponding to the second window (see Fig. 2A: 303, 302, Fig. 2B: 304, 302, paragraphs 20-21).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Lai et al. with the teachings of Chiu et al. in order to have the step of forming the embedded wiring layer at least on a side of the first encapsulation layer comprise: forming a photoresist layer covering the first encapsulation layer; and patterning the photoresist layer to form a second widow in the photoresist layer, and disposing the embedded wiring layer in a region of the first encapsulation layer corresponding to the second window. Doing so would allow the wiring layer to be selectively deposited within the window without the need for any additional etching steps.
Claims 10, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (CN 105321894 A), as applied to Claim 8 above, further in view of Chew (CN 109509727 A).
Regarding Claim 10, Lai et al. discloses the semiconductor packaging structure of claim 8, wherein the pin 200 of the chip 20 comprises a first pin 200-1 and a second pin 200-2, the embedded wiring layer 24 comprises an embedded line 24, and the fan-out wiring layer 260 comprises: a first fan-out line 260-1, electrically connected to the embedded line 24 and the first pin 200-1 of the chip 200; and a second fan-out line 260-2, insulated from the first fan-out line 260-1 and electrically connected to the second pin 200-2 of the chip 20 (see annotated Fig. 2G: 200-1, 200-2, 260-1, 260-2, 20, 24).
Chew discloses a semiconductor packaging structure comprising the following claim limitation not disclosed in Lai et al.
a first fan-out line 603, electrically connected to the embedded line 400 and the first pin of the chip 300 (see annotated Fig. 13: 400, 603, page 10, lines 22-32 in in English Translation of Chew)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Lai et al. with the teachings of Chew in order to have the first fan-out line, electrically connected to the embedded line and the first pin of the chip. Doing so would allow access to additional wiring layers on different layers without crossing over other metal traces in the semiconductor package.
Regarding Claim 13, Lai et al. fails to disclose the semiconductor packaging structure of claim 8, wherein a material of the first encapsulation layer comprises a photosensitive material.
However, Chew discloses a semiconductor packaging structure wherein a material of the first encapsulation layer 600 comprises a photosensitive material (Fig. 11: 600, page 10, lines 9-11 in English Translation of Chew).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Lai et al. with the teachings of Chew in order to have a material of the first encapsulation layer comprise a photosensitive material. Doing so would enable direct patterning using photolithography or laser irradiation without requiring additional etching steps, as recognized by Chew (see page 10, lines 8-14 in English Translation of Chew).
Regarding Claim 14, Lai et al. discloses the semiconductor packaging structure of claim 10, wherein the first fan-out line 260-1 and the second fan-out line 260-1 are disposed in a same layer (see annotated Fig. 2G: 260-1, 260-2).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (CN 105321894 A), as applied to Claim 8 above, further in view of Chiu et al. (US 20160079151 A1).
Regarding Claim 7, Lai et al. fails to disclose the semiconductor packaging structure of claim 8, further comprising a photoresist layer covering the first encapsulation layer, and a second window is formed in the photoresist layer by patterning the photoresist layer, and the embedded wiring layer is disposed in a region of the first encapsulation layer corresponding to the second window.
However, Chiu et al. teaches a semiconductor packaging structure, comprising a photoresist layer 303 covering the first layer 302; and a second widow is formed in the photoresist layer 303 by patterning the photoresist layer 303, and the embedded wiring layer 304 is deposed in a region of the first layer 302 corresponding to the second window (see Fig. 2A: 303, 302, Fig. 2B: 304, 302, paragraphs 20-21).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Lai et al. with the teachings of Chiu et al. in order to have a photoresist layer covering the first encapsulation layer, and a second widow is formed in the photoresist layer by patterning the photoresist layer, and the embedded wiring layer is disposed in a region of the first encapsulation layer corresponding to the second window. Doing so would allow the wiring layer to be selectively deposited within the window without the need for any additional etching steps.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (CN 105321894 A), as applied to Claim 8 above, further in view of Zhou (CN 112582283 A).
Regarding Claim 18, Lai et al. fails to discloses the semiconductor packaging structure of claim 8, further comprising a protective layer, which is provided in a front surface of the chip.
However, Zhou discloses a semiconductor packaging structure comprising a protective layer 202, which is provided in a front surface of the chip 201 (Fig. 2e: 202, 201, page 6, lines 28-29).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Lai et al. with the teachings of Zhou in order to have a protective layer, which is provided in a front surface of the chip. By doing so, the protective layer can prevent the encapsulating material from penetrating the front surface of the chip to be packaged, thus, protecting the circuit structure on the front surface of the chip, as recognized by Zhou (page 10, lines 5-9).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 08/05/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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