DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Preliminary Amendment
The Office acknowledges the applicant’s 7/11/2023 preliminary amendment to: 1. Amend the instant Specification. 2. Amend the Claims.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/11/2024 and 1/4/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: METHOD OF FABRICATING DISPLAY DEVICE USING SACRIFICIAL FILM.
Claims Status
Claims 1-18 are currently pending and being examined. Claims 1-13 have been amended, claim 12 into independent form and claim 13 into dependent form. New claims 14-18 have been added. No claims have been deleted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3, 5-11, 13 and 15-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim 3 recites the limitations "the step of etching of" in line 6. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 1, "the step of etching of" in line 6 will be interpreted to read as "the etching of".
B. Claim 5 recites the limitations "the step of forming" in line 2 and "after the step of forming" in line 4. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 1, "the step of forming" in line 2 will be interpreted to read as "a step of forming" and "after the step of forming" in line 4 will be interpreted to read as "after the forming of".
C. Claim 6 recites the limitations "the step of removing" in line 2 and "before the step of forming" in line 3. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 1, "the step of removing" in line 2 will be interpreted to read as "the removing of" and "before the step of forming" in line 3 will be interpreted to read as "before the forming of".
D. Claim 7 recites the limitation "the step of forming" in line 2 and "the step of removing" in line 4. There is insufficient antecedent basis for these limitation in the claim.
For examination purposes and consistency with claim 1, "the step of forming" in line 2 will be interpreted to read as "a step of forming" and "the step of removing" in line 4 will be interpreted to read as "the removing of".
E. Claim 8 recites the limitation "the step of forming" in line 2. There is insufficient antecedent basis for these limitation in the claim.
For examination purposes and consistency with claim 7, "the step of forming" in line 2 will be interpreted to read as "a step of forming".
F. Claim 9 recites the limitation "the step of forming" in line 2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 7, "the step of forming" in line 2 will be interpreted to read as "a step of forming".
G. Claim 10 recites the limitation "the step of forming" in line 2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 7, "the step of forming" in line 2 will be interpreted to read as "a step of forming".
H. Claim 11 recites the limitation "step of forming" in line 2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 7, "step of forming" in line 2 will be interpreted to read as "a step of forming".
I. Claim 13 recites the limitation "the step of etching" in line 3 and "the step of removing" in line 6. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 12, "the step of etching" in line 3 will be interpreted to read as "the etching of" and "the step of removing" in line 6 will be interpreted to read as "the removing of".
J. Claim 15 recites the limitations "the step of forming" in line 2 and "the step of forming" in lines 3-4. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 12, "the step of forming" in line 2 will be interpreted to read as "a step of forming" and "the step of forming" in lines 3-4 will be interpreted to read as "the forming of".
K. Claim 16 recites the limitation "the step of removing" in line 2 and "the step of forming" in lines 3-4. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 12, "the step of removing" in line 2 will be interpreted to read as "the removing of" and "the step of forming" in lines 3-4 will be interpreted to read as "the forming of".
L. Claim 17 recites the limitations "the step of forming" in line 2 and "the step of removing" in line 4. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 12, "the step of forming" in line 2 will be interpreted to read as "a step of forming" and "the step of removing" in line 4 will be interpreted to read as "the removing of".
M. Claim 18 recites the limitation "the step of forming" in line 2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 12, "the step of forming" in line 2 will be interpreted to read as "a step of forming".
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 4 is rejected under 35 U.S.C. 112(a), first paragraph, because the specification, while being enabling for oxygen free gases for etching, does not reasonably provide enablement for including H2O as an oxygen free gas for etching. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to perform oxygen free gas etching using H2O as disclosed by the invention commensurate in scope with these claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5-11; and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshitoku et al (US 2013/0084664 A1, hereafter Yoshitoku) in view of Kato et al (US 2015/0048328 A1, hereafter Kato).
Re Claim 1, Yoshitoku discloses in FIGS. 2A-2N a method of fabricating a display device (1), comprising the steps of:
forming a first pixel electrode (11a in FIG. 2A; [0041]) and a second pixel electrode (11b in FIG. 2A; [0041]);
forming a first EL film (12/12a in FIG. 2B; [0043]-[0044]) over the first pixel electrode (11a) and the second pixel electrode (11b);
forming a first sacrificial film (laminate 21/22 in FIGS. 2C-2E; [0048]-[0050]) covering the first EL film (12/12a);
etching (in FIG. 2G; [0052]-[0053]) the first sacrificial film (laminate 21/22) to form a first sacrificial layer (unlabeled patterned laminate 21/22) comprising a region overlapping (above) with the first pixel electrode (11a);
etching (in FIG. 2G; [0052]-[0053] and [0074]) the first EL film (12/12a) to form a first EL layer (12a; [0078]) comprising a region overlapping with (below) the first sacrificial layer (unlabeled patterned laminate 21/22) and to expose the second pixel electrode (11b);
forming a second EL film (12/12b in 2H; [0077]-[0078]) over the first sacrificial layer (unlabeled patterned laminate 21/22) and the second pixel electrode (11b);
forming a second sacrificial film (2nd laminate 21/22 in 2H-2I as in FIGS. 2C-2E; [0048]-[0050] and [0077]-[0078]) covering the second EL film (12/12b);
etching (in FIG. 2I as in FIGS. 2C-2G; [0048]-[0053] and [0078]) the second sacrificial film (2nd laminate 21/22) to form a second sacrificial layer (unlabeled patterned 2nd laminate 21/22) comprising a region overlapping with (above) the second pixel electrode (11b);
etching (in FIG. 2K; [0077]-[0078]) the second EL film (12/12b) to form a second EL layer (12b; [0078]) comprising a region overlapping with (below) the second sacrificial layer (unlabeled patterned 2nd laminate 21/22); and
removing (in FIG. 2L; [0079]-[0080]) the first sacrificial layer (unlabeled patterned laminate 21/22) and the second sacrificial layer (unlabeled patterned 2nd laminate 21/22).
Yoshitoku fails to disclose forming an insulating film covering a top surface and a side surface of the first sacrificial layer (unlabeled patterned laminate 21/22), a side surface of the first EL layer (12a), a top surface and a side surface of the second sacrificial layer (unlabeled patterned 2nd laminate 21/22), and a side surface of the second EL layer (12b); and
etching the insulating film to form a first insulating layer comprising a region in contact with the side surface of the first EL layer (12a) and a region in contact with the side surface of the second EL layer (12b) and to expose the first sacrificial layer (unlabeled patterned laminate 21/22) and the second sacrificial layer (unlabeled patterned 2nd laminate 21/22).
However,
Kato discloses in FIGS. 5-10 a method of fabricating a display device (1), comprising the steps of:
forming an insulating film (laminate 15 in FIG. 6A; [0115]) covering a top surface (upper horizontal plane) and a side surface (left/right vertical planes) of a first pixel electrode (left 14; [0114]) and a top surface (upper horizontal plane) and a side surface (left/right vertical planes) of a second pixel electrode (middle 14; [0114]); and
etching (in FIGS. 6B-6C; [0116]-[0117]) the insulating film (laminate 15) to form a first insulating layer (patterned laminate 15) comprising a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the first pixel electrode (left 14) and a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the second pixel electrode (middle 14), and to expose the top surface (upper horizontal plane) of the first pixel electrode (left 14) and the top surface (upper horizontal plane) of the second pixel electrode (middle 14).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yoshitoku, after FIG. 2K, and before FIG. 2L, by adding the forming of the insulating film of Kato, the insulating film covering a top surface and a side surface of the first sacrificial layer (unlabeled patterned laminate 21/22), a side surface of the first EL layer (12a), a top surface and a side surface of the second sacrificial layer (unlabeled patterned 2nd laminate 21/22), and a side surface of the second EL layer (12b); and
then adding the etching of the insulating film of Kato to form a first insulating layer comprising a region in contact with the side surface of the first EL layer (12a) and a region in contact with the side surface of the second EL layer (12b) and to expose the first sacrificial layer (unlabeled patterned laminate 21/22) and the second sacrificial layer (unlabeled patterned 2nd laminate 21/22) to prevent a short-circuiting between the first pixel electrode and second pixel electrode during device processing.
Re Claim 2, Yoshitoku discloses in FIGS. 2A-2N a method of fabricating a display device, comprising the steps of:
forming a first pixel electrode and a second pixel electrode (see claim 1);
forming a first EL film over the first pixel electrode and the second pixel electrode (see claim 1);
forming a first sacrificial film covering the first EL film (see claim 1);
etching the first sacrificial film to form a first sacrificial layer comprising a region overlapping with the first pixel electrode (see claim 1);
etching the first EL film to form a first EL layer comprising a region overlapping with the first sacrificial layer and to expose the second pixel electrode (see claim 1);
forming a second EL film over the first sacrificial layer and the second pixel electrode (see claim 1);
forming a second sacrificial film covering the second EL film (see claim 1);
etching the second sacrificial film to form a second sacrificial layer comprising a region overlapping with the second pixel electrode (see claim 1);
etching the second EL film to form a second EL layer comprising a region overlapping with the second sacrificial layer (see claim 1); and
removing the first sacrificial layer and the second sacrificial layer (see claim 1).
Yoshitoku fails to disclose forming an insulating film covering a top surface and a side surface of the first sacrificial layer, a side surface of the first EL layer, a top surface and a side surface of the second sacrificial layer, and a side surface of the second EL layer;
etching the insulating film to form a first insulating layer comprising a region in contact with the side surface of the first EL layer and a region in contact with the side surface of the second EL layer and to form a second insulating layer over the first sacrificial layer and a third insulating layer over the second sacrificial layer; and
removing the second insulating layer and the third insulating layer.
However,
Kato discloses in FIGS. 5-10 a method of fabricating a display device (1), comprising the steps of:
forming an insulating film (laminate 15 in FIG. 6A; [0115]) covering a top surface (upper horizontal plane) and a side surface (left/right vertical planes) of a first pixel electrode (left 14; [0114]) and a top surface (upper horizontal plane) and a side surface (left/right vertical planes) of a second pixel electrode (middle 14; [0114]); and
etching (in FIGS. 6B; [0116]) the insulating film (laminate 15) to form a first insulating layer (un-patterned laminate 15) comprising a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the first pixel electrode (left 14) and a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the second pixel electrode (middle 14) and to form a second insulating layer (patterned laminate 15 on left 14) over (above) the first pixel electrode (left 14) and a third insulating layer (patterned laminate 15 on middle 14) over (above) the pixel electrode (middle 14); and
removing (in FIG. 6C; [0117]) the second insulating layer (patterned laminate 15 on left 14) and the third insulating layer (patterned laminate 15 on middle 14).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yoshitoku, after FIG. 2K, and before FIG. 2L, by adding the forming of the insulating film of Kato, the insulating film covering a top surface and a side surface of the first sacrificial layer (unlabeled patterned laminate 21/22), a side surface of the first EL layer (12a), a top surface and a side surface of the second sacrificial layer (unlabeled patterned 2nd laminate 21/22), and a side surface of the second EL layer (12b); and
then adding the etching of the insulating film of Kato to form a first insulating layer (un-patterned laminate 15) comprising a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the first pixel electrode (left 14) and a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the second pixel electrode (middle 14) and to form a second insulating layer (patterned laminate 15 on left 14) over (above) the first pixel electrode (left 14) and a third insulating layer (patterned laminate 15 on middle 14) over (above) the pixel electrode (middle 14), and then removing the second insulating layer and the third insulating layer before removing the removing the first sacrificial layer and the second sacrificial layer of Yoshitoku, to prevent a short-circuiting between the first pixel electrode and second pixel electrode during device processing.
Re Claim 5, Yoshitoku discloses the method of fabricating a display device according to claim 1, further comprising a step of forming a first protective layer (patterned 23 in FIGS. 2E-2F; [0050]-[0051]) comprising a region overlapping with (above) the first pixel electrode (11a) after the forming of the first sacrificial film (laminate 21/22), wherein the first sacrificial film (laminate 21/22) is etched using the first protective layer (patterned 23) as a mask ([0074]) to form the first sacrificial layer (unlabeled patterned laminate 21/22).
Re Claim 6, Yoshitoku discloses the method of fabricating a display device according to claim 5, comprising the removing of (in FIG. 2G; [0075]) the first protective layer (patterned 23) before the forming of the second EL film (12b).
Re Claim 7, Yoshitoku discloses the method of fabricating a display device according to claim 1, further comprising a step of forming a common electrode (14 in FIG. 2N; [0084]) covering over a top surface (upper horizontal plane) of the first EL layer (12a), a top surface (upper horizontal plane) of the second EL layer (12b) after the removing of the first sacrificial layer (unlabeled patterned laminate 21/22) and the second sacrificial
layer (unlabeled patterned 2nd laminate 21/22).
Yoshitoku fails to disclose the common electrode (14) covering over a top surface a top surface and a side surface of the first insulating layer after the removing of the first sacrificial layer and the second sacrificial layer.
However, Kato would render the limitations obvious since first insulating layer (laminate 15) would be formed between the first EL layer and the second EL layer as discussed for claim 1, such that the common electrode (14) would be covering over a top surface a top surface (upper horizontal plane) and a side surface (inner side walls) of the first insulating layer (laminate 15) after the removing of the first sacrificial (unlabeled patterned laminate 21/22) and the second sacrificial layer (unlabeled patterned 2nd laminate 21/22) as part of the short-circuit protection discussed for claim 1.
Re Claim 8, Yoshitoku discloses the method of fabricating a display device according to claim 7, further comprising a step of forming a layer (13 in FIG. 2M; [0082]) covering the top surface (upper horizontal plane) of the first EL layer (12a), the top surface (upper horizontal plane) of the second EL layer (12b) before the step of forming the common electrode (14), wherein the layer (13) is a layer (electron injection layer; [0082]) containing comprises a substance (publicly-known material; [0082]) with an electron-injection property ([0082]).
Yoshitoku fails to disclose the layer (13) covering over a top surface a top surface and a side surface of the first insulating layer (unlabeled patterned laminate 21/22) and the second sacrificial layer (unlabeled patterned 2nd laminate 21/22) before the step of forming the common electrode (14).
However, Kato would render these limitations similarly to as discussed for claim 7 as part of the short-circuit protection discussed for claim 1.
Re Claim 9, Yoshitoku discloses the method of fabricating a display device according to claim 7, further comprising a step of forming a layer (13 in FIG. 2M; [0082]) covering the top surface (upper horizontal plane) of the first EL layer (12a), the top surface (upper horizontal plane) of the second EL layer (12b) before the step of forming the common electrode (14), wherein the layer (13) has a stacked-layer structure (multiple layers; [0082]) of a first layer (electron transport layer; [0082]) containing a substance (publicly-known material; [0082]) with an electron-transport property ([0082]) and a second layer (electron injection layer; [0082]) containing a substance (publicly-known material; [0082]) with an electron-injection property ([0082]) over (on) the first layer (electron transport layer).
Yoshitoku fails to disclose the layer (13) covering over a top surface a top surface and a side surface of the first insulating layer (unlabeled patterned laminate 21/22) and the second sacrificial layer (unlabeled patterned 2nd laminate 21/22) before the step of forming the common electrode (14).
However, Kato would render these limitations similarly to as discussed for claim 7 as part of the short-circuit protection discussed for claim 1.
Re claims 10-11, Yoshitoku and Kato disclose the method of fabricating a display device according to claim 7, further comprising a step of forming a layer covering the top surface of the first EL layer, the top surface of the second EL layer, and the top surface and the side surface of the first insulating layer before the step of forming the common
electrode (see claims 8-9); and further comprising a step of forming a layer covering the top surface of the first EL layer, the top surface of the second EL layer, and the top surface and the side surface of the first insulating layer before the step of forming the common electrode (see claims 8-9).
With respect to the limitations of wherein the layer is a layer containing comprises
a substance with a hole-injection property; and wherein the layer has a stacked-layer structure of a first layer containing a substance with a hole-transport property and a second layer containing a substance with a hole-injection property over the first layer, it would have been obvious to one of ordinary skill in the art that the EIL and ETL layers of Yoshitoku (see claims 8-9) would be HIL and HTL layers if the common electrode were an anode as part of the short-circuit protection discussed for claim 1.
Claim(s) 12-13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto et al (JP 2008-147072 A-translation and original provided in view of Kato et al (US 2015/0048328 A1, hereafter Kato).
Re Claim 12, Hashimoto discloses in FIGS. 1a-1g a method of fabricating a display device (1), comprising the steps of:
forming a first pixel electrode (left 2 in FIG. 1a; [0022]) and a second pixel electrode (right 2 in FIG. 1a; [0022]);
forming an EL film (6 in FIG. 1a; [0022]) over the first pixel electrode (left 2) and the second pixel electrode (right 2);
forming a sacrificial film covering the EL film (7 in FIG. 1b; [0022]);
etching (washing in FIGS. 1c-1d; [0022]) the sacrificial film (7) to form a first sacrificial layer (left 7a in FIG. 1d; [0022]) comprising a region overlapping with (above) the first pixel electrode (left 2) and to form a second sacrificial layer (right 7a in FIG. 1d; [0022]) comprising a region overlapping with (above) the second pixel electrode (right 2);
etching (in FIG. 1e; [0022]) the EL film (6) to form a first EL layer (left patterned 6) comprising a region overlapping with (below) the first sacrificial layer (left 7a) and to form a second EL layer (right patterned 6) comprising a region overlapping with (below) the second sacrificial layer (right 7a); and
removing (in FIG. 1f; [0022]) the first sacrificial layer (left 7a) and the second sacrificial layer (right 7a).
Hashimoto fails to disclose forming an insulating film covering a top surface and a side surface of the first sacrificial layer (left 7a), a side surface of the first EL layer (left patterned 6), a top surface and a side surface of the second sacrificial layer (right 7a), and a side surface of the second EL layer (right patterned 6);
etching the insulating film to form a first insulating layer comprising a region in contact with the side surface of the first EL layer (left patterned 6) and a region in contact with the side surface of the second EL layer (right patterned 6) and to expose the first sacrificial layer (left 7a) and the second sacrificial layer (right 7a); and
wherein the EL film (6) comprises a light-emitting layer emitting white light.
However,
Kato discloses in FIGS. 5-10 a method of fabricating a display device (1), comprising the steps of:
forming an insulating film (laminate 15 in FIG. 6A; [0115]) covering a top surface (upper horizontal plane) and a side surface (left/right vertical planes) of a first pixel electrode (left 14; [0114]) and a top surface (upper horizontal plane) and a side surface (left/right vertical planes) of a second pixel electrode (middle 14; [0114]); and
etching (in FIGS. 6B-6C; [0116]-[0117]) the insulating film (laminate 15) to form a first insulating layer (patterned laminate 15) comprising a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the first pixel electrode (left 14) and a region (left/right sides) in contact with (physically touching) the side surface (left/right vertical planes) of the second pixel electrode (middle 14), and to expose the top surface (upper horizontal plane) of the first pixel electrode (left 14) and the top surface (upper horizontal plane) of the second pixel electrode (middle 14); and
forming an EL film (18 in FIG. 8; [0095] and [0118]) over the first pixel electrode (left 14) and the second pixel electrode (middle 14), wherein the EL film (18) comprises a light-emitting layer (18B; [0095]) emitting white light ([0100] and [0124]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hashimoto, after FIG. 1e, and before FIG. 1f, by adding the forming of the insulating film of Kato, the insulating film covering a top surface and a side surface of the first sacrificial layer (left 7a), a side surface of the first EL layer (left patterned 6), a top surface and a side surface of the second sacrificial layer (right 7a), and a side surface of the second EL layer (right patterned 6);
then adding the etching of the insulating film of Kato to form a first insulating layer comprising a region in contact with the side surface of the first EL layer (left patterned 6) and a region in contact with the side surface of the second EL layer (right patterned 6) and to expose the first sacrificial layer (left 7a) and the second sacrificial layer (right 7a) to prevent a leakage current between the first pixel electrode and second pixel electrode during device processing; and
substituting the white light EL film of Kato for the EL film of Yoshitoku in order to reduce process steps by forming the EL film for each pixel of a desired color (white) simultaneously.
Re claim 13, Hashimoto discloses the method of fabricating a display device according to claim 12.
But, fails to disclose wherein in the etching of the insulating film, a second insulating layer is formed over the first sacrificial layer (left 7a) and a third insulating layer is formed over the second sacrificial layer (right 7a), and wherein in the removing of the first sacrificial layer (left 7a) and the second sacrificial layer (right 7a), the second insulating layer and the third insulating layer are removed.
However, Kato would render these limitations obvious by disclosing a second insulating layer (see claim 2) and a third insulating layer (see claim 2) that would be formed over the first sacrificial layer (left 7a) and the second sacrificial layer (right 7a), respectively, wherein in the removing of the first sacrificial layer (left 7a) and the second sacrificial layer (right 7a), the second insulating layer and the third insulating layer are removed as part of the leakage current protected single-color pixels discussed for claim 12.
Re claim 17, Hashimoto discloses the method of fabricating a display device according to claim 12, further comprising a step of forming a common electrode (8 in FIG. 1g; [0022]) over a top surface (upper horizontal plane) of the first EL layer (left patterned 6), a top surface (upper horizontal plane) of the second EL layer (right patterned 6) after the removing of the first sacrificial layer (left 7a) and the second sacrificial layer (right 7a).
Hashimoto fails to disclose forming the common electrode (8) over a top surface and a side surface of the first insulating layer after the removing of the first sacrificial layer and the second sacrificial layer.
However, Kato would render these limitations similarly to as discussed for claim 7 as part of the leakage current protected single-color pixels discussed for claim 12.
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshitoku and Kato as applied to claim 1 above, and further in view of Oshige (US 2013/0084666 A1, hereafter Osighe).
Re Claims 3-4, Yoshitoku discloses the method of fabricating a display device according to claim 1, wherein the first sacrificial film (unlabeled patterned laminate 21/22) comprises one or more of a metal film ([0062]), an alloy film, a metal oxide film, a semiconductor film, and an inorganic insulating film ([0062]), and wherein dry etching ([0074]) is employed in the etching of the first EL film (12/12a).
But, fails to disclose dry etching using an etching gas not containing an oxygen gas is employed in the etching of the first EL film; and wherein the etching gas not containing an oxygen gas is one or more selected from CF4, C4F8, SF6, CHF3, Cl2, H2O, BCl3, H2, and a noble gas.
However,
Oshige discloses in FIG. 1B a method of etching comprising: dry etching using an etching gas ([0042]) not containing an oxygen gas ([0042]) is employed in the etching of an first EL film (3; [0039] and [0042]); and wherein the etching gas not containing an oxygen gas is one or more selected from CF4 ([0042]), C4F8, SF6 ([0042]), CHF3, Cl2, H2O, BCl3, H2, and a noble gas.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hashimoto by using the oxygen free etching gases (CF4 or SF6) to etch the EL film to produce patterned EL layers of the desired shape ([0042]).
Claims 14-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto and Kato as applied to claim 12 above, and further in view of Yoshitoku.
Re claim 14, Hashimoto discloses the method of fabricating a display device according to claim 12.
But, fails to disclose wherein the sacrificial film comprises one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, and an inorganic insulating film.
However, Yoshitoku discloses wherein a sacrificial film (laminate 21/22) comprises one or more of a metal film ([0062]), an alloy film, a metal oxide film, a semiconductor film, and an inorganic insulating film ([0062]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hashimoto by adding the sacrificial film of Yoshitoku before the sacrificial film of Hashimoto, for blocking light which may damage EL film (Yoshitoku; [0059]).
Re claim 15, Hashimoto discloses the method of fabricating a display device according to claim 13.
But, fails to disclose the method further comprising a step of forming a first protective layer overlapping with the first pixel electrode (left 2) and a second protective layer overlapping with the second pixel electrode (right 2) after the forming of the sacrificial film, wherein the sacrificial film is etched using the first protective layer and the second protective layer as masks to form the first sacrificial layer and the second sacrificial layer.
However, Yoshitoku would render these limitations obvious by adding the sacrificial layer (see claim 14) after FIG. 1a of Hashimoto, then continuing the process at FIG. 1b using the layer (left 7a) and layer (right 7b) as a first protective layer overlapping with the first pixel electrode and a second protective layer overlapping with the second pixel electrode after the forming of the sacrificial film, wherein the sacrificial film is etched using the first protective layer and the second protective layer as masks to form the first sacrificial layer and the second sacrificial layer as part of the light blocking structure discussed for claim 14.
Re claim 16, Hashimoto and Kato and Yoshitoku disclose the method of fabricating a display device according to claim 15, further comprising the removing of the first protective layer (modified left 7a of Hashimoto) and the second protective layer (modified right 7a of Hashimoto) before the forming of the insulating film (15 of Kato) as would be part of the light blocking structures used for forming the leakage current protected single-color pixels discussed for claims 12, 14 and 15.
Re claim 18, Hashimoto discloses the method of fabricating a display device according to claim 17.
But, fails to disclose the method further comprising a step of forming a layer covering the top surface of the first EL layer, the top surface of the second EL layer, and the top surface and the side surface of the first insulating layer before the step of forming the common electrode, wherein the layer comprises at least one of a substance with an electron-injection property and a substance with a hole-injection property.
However, Yoshitoku and Kato would render these limitations obvious by disclosing forming a layer covering the top surface of the first EL layer, the top surface of the second EL layer, and the top surface and the side surface of the first insulating layer before the step of forming the common electrode, wherein the layer comprises at least one of a substance with an electron-injection property (see claim 8) as would be part of the leakage current protected single-color pixels discussed for claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408)918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC W JONES/Primary Examiner, Art Unit 2892