DETAILED ACTION
This office action is in response to amendment filed 2/27/2026.
Claims 1-13 and 15-21 are pending. Claim 14 has been canceled. Claim 21 is new. Claims 3-4, 13, and 19-20 have been withdrawn. Claims 1, 5-6, 8-10, 12, 15, and 17 have been amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 10-11, 15-18, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kelly et al. US 2016/0307870 A1 (Kelly).
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In re claim 1, Kelly discloses (e.g. FIGs. 1-2 & 5-6) a method for manufacturing a semiconductor device, comprising:
preparing a base material 115,510;
preparing a plurality of semiconductor elements 101A,101B,501A,501B each having a connection terminal 109,509;
preparing a wiring board 103,503 provided with a first wiring 106 (portion “A”, ¶ 13);
arranging the plurality of semiconductor elements 101A,101B,501A,501B on the base material 115,510;
covering the plurality of semiconductor elements 101A,101B,501A,501B on the base material 115,510 with an insulating material 107,507,115;
arranging the wiring board 103,503 on at least one of the plurality of semiconductor elements 101A,101B,501A,501B so that the first wiring is connected to at least some of the connection terminals 109,509 of the plurality of semiconductor elements 101A,101B,501A,501B covered with the insulating material 107,507,115; and
forming a second wiring 116,506,512 (of 105, ¶ 16,47,48) around (could understood to mean present “near”) the first wiring (of 103 or 503),
wherein the first wiring (of 103 or 503, high density, ¶ 13,16,47) has finer wiring than the second wiring (of 105,505,510, lower density, ¶ 26,44,52),
wherein the wiring board 103,503 comprises:
a base insulating layer (RDL portion “B”); and
the first wiring (in portion “A”) provided on the base insulating layer (portion “B”), and
wherein the base insulating layer (portion “B”) contains a resin (RDL can have polyimide or PBO, ¶ 13).
In re claim 2, Kelly discloses (e.g. FIG. 1) wherein the plurality of semiconductor elements 101A,101B are arranged on the base material 115 so that the connection terminals 109 of the plurality of semiconductor elements face a side (bottom side) opposite to the base material 115 (formed on top side of dies). Alternatively, Kelly discloses (e.g. FIG. 5) wherein the plurality of semiconductor elements 501A,501B are arranged on the base material 510 so that the connection terminals 509 of the plurality of semiconductor elements face a side (top side of 510) opposite to (bottom side of) the base material 510.
In re claim 5, Kelly discloses (e.g. FIG. 1) wherein the first wiring (of 103) includes wiring having a line width of 5 µm or less (0.5 -1 µm, ¶ 15).
In re claim 10, Kelly discloses (e.g. FIG. 1) wherein the wiring board 103 includes a wiring insulating layer (inorganic dielectric of BEOL portion “A” of 103, ¶ 13) covering the first wiring (interconnect layers of BEOL portion “A” of 103, ¶ 13) on the base insulating layer (RDL portion “B”), and
wherein an insulating material forming at least one of the base insulating layer and the wiring insulating layer has a thermal expansion coefficient of 80 ppm/°C or less (¶ 13, e.g. CTE of SiO2 is less than 80 ppm/°C).
In re claim 11, Kelly discloses (e.g. FIG. 1) wherein the base insulating layer (RLD portion “B” of 103) is thicker than the wiring insulating layer (dielectric layer of BEOL portion “A” of 103, ¶ 13).
In re claim 15, Kelly discloses (e.g. FIGs. 1 & 5) wherein the first wiring (of 103,503) is directly connected to the at least some of the connection terminals 109,509 of the plurality of semiconductor elements 101A,101B,501A,501B.
In re claim 16, Kelly discloses (e.g. FIGs.1 & 5) wherein the first wiring of the wiring board 103,503 is connected to at least two of the plurality of semiconductor elements 101A,101B,501A,501B.
In re claim 17, Kelly discloses (e.g. FIGs. 1-2) wherein the second wiring (of 105) includes a first end (top metal 116) and a second end (bottom metal 116) on a side opposite to the first end, and
wherein the second wiring is connected to the at least some of the connection terminals 109 of the plurality of semiconductor elements 101A,101B at the first end (top metal 116) and is exposed from an insulating material 118 (on bottom side of 105) covering the second wiring and connected to an external terminal 111 at the second end (bottom metal of 105 connect to external contact 111, ¶ 20).
In re claim 18, Kelly discloses (e.g. FIGs. 1-2) wherein the insulating material 108 covering the second wiring 116 does not contain a glass cloth (¶ 13-16).
In re claim 21, Kelly discloses (e.g. FIG. 2) wherein the second wiring (second wiring also including 113) is formed (FIG. 2C) after arranging the wiring board 103 on the at least one of the plurality of semiconductor elements 101A,101B (FIG. 2B).
Claims 1-2, 5-7, 9-12, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Taneda et al. US 2020/0092993 A1 (Taneda).
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In re claim 1, Taneda discloses (e.g. FIGs. 1 & 11) a method for manufacturing a semiconductor device, comprising:
preparing a base material 2 (FIG. 11);
preparing a plurality of semiconductor elements 80 each having a connection terminal 82,90;
preparing a wiring board 1 provided with a first wiring 14,16,18,20 (FIG. 1, ¶ 30);
arranging the plurality of semiconductor elements 80 on the base material 2;
covering the plurality of semiconductor elements 80 on the base material 2 with an insulating material 95;
arranging the wiring board 1 on at least one of the plurality of semiconductor elements 80 so that the first wiring 14,16,18,20 is connected to at least some of the connection terminals 82,90 of the plurality of semiconductor elements 80 covered with the insulating material 95; and
forming a second wiring 52,54,56,58,62,64,66 (FIG. 11, ¶ 106) around (understood to mean present “near”) the first wiring 14,16,18,20 (of wiring board 1),
wherein the first wiring 14,16,18,20 (of wiring board 1, higher density, ¶ 46-48,52,54) has finer wiring than the second wiring 52,54,56,58,62,64,66 (lower density, ¶ 105),
wherein the wiring board 1 comprises (FIG. 1):
a base insulating layer 12; and
the first wiring 14,16,18,20 provided on the base insulating layer 12, and
wherein the base insulating layer 12 contains a resin 121,122 (¶ 34,36,39,40).
In re claim 2, Taneda discloses (e.g. FIG. 11) wherein the plurality of semiconductor elements 80 are arranged on the base material 2 so that the connection terminals 82,90 of the plurality of semiconductor elements 80 face a side (top side of 2) opposite to (bottom side of) the base material 2.
In re claim 5, Taneda discloses (e.g. FIG. 1) wherein the first wiring 14,16,18,20 includes wiring having a line width of 5 µm or less (3 µm, ¶ 46-48,52,54).
In re claim 6, Taneda discloses (e.g. FIG. 1) wherein the base insulating layer 12 contains a glass cloth 128 (¶ 41).
In re claim 7, Taneda discloses (e.g. FIG. 1) wherein a base material 121+122 of the glass cloth 12 has a thickness of 30 µm or more and 500 µm or less (T121+T122 is approximately 45µm to 80µm, ¶ 36,40).
In re claim 9, Taneda discloses (FIG. 1) the thickness of the base insulating layer 121+122 is T121+T122 of approximately 45µm to 80µm (¶ 36,40), and surface roughness of upper surface 12a is approximately 15 nm to 40 nm and surface roughness of bottom surface 12b is approximately 180 nm to 280 nm (¶ 79). As such, the maximum thickness variation is 320nm/45µm=0.007 or approximately 0.7%, which teaches claimed thickness variation of 1% or less.
In re claim 10, Taneda discloses (e.g. FIG. 1) wherein the wiring board 1 includes a wiring insulating layer 15 covering the first wiring 14 on the base insulating layer 12 (121+122), and
wherein an insulating material forming at least one of the base insulating layer 12 (121+122) and the wiring insulating layer 15 has a thermal expansion coefficient of 80 ppm/°C or less (¶ 36,40; CTE of layer 121 is approximately 20 to 30 ppm/°C while CTE of layer 122 is approximately 16 ppm/°C or lower).
In re claim 11, Taneda discloses (e.g. FIG. 1) wherein the base insulating layer 12 (121+122) T121+T122 is approximately 45µm to 80µm, ¶ 36,40) is thicker than the wiring insulating layer 15 (approximately 5 µm to 10 µm, ¶ 50).
In re claim 12, Taneda discloses (FIG. 1) wherein a surface 12a of the base insulating layer 12 on which the first wiring 15 is formed has a surface roughness of 200 nm or less (Ra of approximately 15 nm to 40 nm, ¶ 79).
In re claim 15, Taneda discloses (e.g. FIGs. 1 & 11) wherein the first wiring 20 is directly connected to the at least some of the connection terminals 82+90 of the plurality of semiconductor elements 80.
In re claim 16, Taneda discloses (e.g. FIGs.1 & 11) wherein the first wiring 14,16,18,20 of the wiring board 1 is connected to at least two of the plurality of semiconductor elements 80.
In re claim 17, Taneda discloses (e.g. FIG. 11) wherein the second wiring 52,54,56,58,62,64,66 includes a first end (top interconnect 58) and a second end (bottom interconnect 66) on a side opposite to the first end, and
wherein the second wiring 52,54,56,58,62,64,66 is connected to the at least some of the connection terminals 82,90 of the plurality of semiconductor elements 80 at the first end (top interconnect 58) and is exposed from an insulating material 67 covering the second wiring 52,54,56,58,62,64,66 and connected to an external terminal at the second end (bottom interconnect 66 used as pad for electrical connection to board, ¶ 119).
In re claim 18, Taneda discloses (e.g. FIG. 11) wherein the insulating material 67 covering the second wiring 52,54,56,58,62,64,66 does not contain a glass cloth (solder resist 67 made of resin, ¶ 113,119).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Taneda as applied to claim 1 above.
In re claim 8, Taneda discloses (e.g. FIG. 1) wherein the base insulating layer 121+122 has a thickness T121+T122 of approximately 45µm to 80µm (¶ 36,40), which significantly overlaps the claimed range of 50 µm or more and 300 µm or less. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the base insulating layer such that it has a thickness within the claimed range. Optimizing the thickness T121+T122 would be obvious to reduce warping as recognized by Taneda (¶ 99,137). E.g. Table 1 shows T121=20 µm and T122=30 µm (i.e. a total thickness of 50 µm) for minimum warp. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Response to Arguments
Applicant's arguments filed 2/27/2026 have been fully considered but they are not persuasive.
Applicant argues Taneda fails to teach the wiring board comprises the first wiring provided on the base insulating layer, and wherein the base insulating layer contains a resin (Remark, pages 7-8).
This is not persuasive. Taneda does explicitly teach a wiring board 1 (FIG. 1) comprises:
a base insulating layer 12; and
the first wiring 14,16,18,20 provided on the base insulating layer 12, and
wherein the base insulating layer 12 contains a resin 121,122 (¶ 34,36,39,40).
Applicant’s other arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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