DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US Publication No. 2011/0165734) in view of Chew (US Publication No. 2018/0151393).
Regarding claim 1, Han discloses a semiconductor packaging method, comprising (Figure 3F):
providing a carrier (30), wherein the carrier comprises an attachment region (under A) for attaching a chip (A)
forming a bonding layer (31), wherein a material of the bonding layer (31), an orthographic projection of the bonding layer on the carrier at least covers the attachment region
attaching the chip (A) onto the bonding layer, wherein an orthographic projection (A) of the chip (A) on the carrier (30) is located in the attachment region
the chip (A) comprises a first surface (down) and a second surface (up) opposite to the first surface, the first surface faces (down) toward the bonding layer (31), and a pad (C1) is disposed on one of the first surface (down) and the second surface
forming an encapsulation layer (M), at least covering a side surface of the chip (A)
removing at least a part of the bonding layer (31), and forming a re-wiring structure (34), wherein the re-wiring structure leads out the pad (C1) (Figure 3F)
Han does not disclose the bonding layer is in a form of a film layer and uncured organic photosensitive material. However, Chew discloses a bonding layer (205) in a form of a film layer of uncured organic photosensitive material (paragraphs 135-136). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the bonding layer of Han to be formed of the material of Chew, since it can provide a seal that avoids shifting for subsequent wiring, thereby providing a reliable electrical connection (paragraphs 136-137; Figure 5A).
Regarding claim 2, Chew discloses the carrier further comprises a non-attachment region (between 201 chips) located outside the attachment region (201), the orthographic projection of the bonding layer (205) on the carrier (200) covers at least a part of the non-attachment region, the bonding layer located in the non-attachment region surrounds the chip (201), and the orthographic projection of the bonding layer (205) in the non-attachment region on the carrier adjoins the orthographic projection of the chip on the carrier (Figure 5A); the semiconductor packaging method further comprises, after attaching the chip onto the bonding layer and before forming the encapsulation layer (204): irradiating the bonding layer by light, such that a part of the bonding layer (205) with the orthographic projection on the carrier located outside the attachment region is cured (paragraph 136; Figure 5A). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 3, Chew discloses the bonding layer (205) is irradiated by light, a part of the bonding layer opposed to the chip is not cured (the portion on the back of the of the chip is removed and not cured); wherein removing at least a part of the bonding layer comprises: removing a part of the bonding layer (205) opposed to the chip (Figures 5A-5B). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 4, Chew discloses before forming the bonding layer: providing a seed layer (203) on the carrier, wherein an orthographic projection of the seed layer on the carrier covers the carrier (200); and forming a conductive column (206) on a side of the seed layer (203) away from the carrier based on the seed layer, wherein the conductive column is located outside the attachment region, and the bonding layer (205) is located on a side of the seed layer away from the carrier. As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 5, Han discloses the re-wiring structure comprises a first wiring sub-structure and a second wiring sub-structure; wherein forming the re-wiring structure comprises:
forming the first wiring sub-structure (C2) on a side of the encapsulation layer (M) away from the second surface
forming the second wiring sub-structure (34) on a side of the encapsulation layer (M) away from the first surface
wherein one of the first wiring sub-structure (C2) and the second wiring sub-structure (34) close to a front surface of the chip is electrically coupled with the pad (C1), and the first wiring sub- structure is electrically coupled with the second wiring sub-structure through the conductive column (C2) (Figure 3F)
Regarding claim 6, Chew discloses the carrier further comprises a non-attachment region (laterally away from the chip) located outside the attachment region, the orthographic projection (206) of the bonding layer on the carrier covers at least a part of the non-attachment region, the bonding layer (205) located in the non-attachment region covers a surface of the conductive column away from the seed layer, the bonding layer (205) located in the non-attachment region surrounds the chip (201), and the orthographic projection of the bonding layer in the non-attachment region on the carrier adjoins the orthographic projection of the chip on the carrier; the semiconductor packaging method further comprises, after attaching the chip onto the bonding layer and before forming the encapsulation layer (204) (Figure 5): irradiating the bonding layer by light, such that a part of the bonding layer with the orthographic projection on the carrier located outside the attachment region is cured (paragraph 135-136); removing at least a part of the bonding layer comprises, before forming the second wiring sub-structure (Figure 5F): removing the cured bonding layer on a side of the conductive column away from the seed layer (Figure 5B). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 7, Chew discloses removing at least a part of the bonding layer comprises, before forming the first wiring sub-structure: removing the carrier (200) to expose the seed layer (203) (Figure 2H); etching the seed layer (203) to expose a part of the bonding layer opposed to the chip (201); and removing the part of the bonding layer (202) opposed to the chip (201). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 8, Han discloses the first surface is provided with the pad (C1) and the chip (A) is further provided with a protective layer (31) covering the pad; the semiconductor packaging method further comprises, after removing the part of the bonding layer opposed to the chip: forming openings (connecting 34 to C1 and C2) for exposing the pad on the protective layer (Figures 3E-3F).
Regarding claim 9, Han/Chew discloses the limitations as discussed in the rejection of claim 4 above. Chew discloses the conductive column (206) comprises a first conductive portion (vertical portion connected to the chip) located on the seed layer and a second conductive portion (horizontal portion) located on a side of the first conductive portion away from the seed layer, and an edge of an orthographic projection of the second conductive portion on the carrier is located inside an edge of an orthographic projection of the first conductive portion on the carrier (Figure 2N). Han/Chew does not disclose a thickness of the conductive column is greater than 200um. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the conductive column of Chew to be greater than 200um to ensure structural integrity for external connection to the chip, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10, Han/Chew discloses the limitations as discussed in the rejection of claim 9 above. Han/Chew does not disclose a distance between the edge of the orthographic projection of the second conductive portion on the carrier and the edge of the orthographic projection of the first conductive portion on the carrier is less than or equal to 8um. However, it would have been obvious to one having ordinary skill in the art at a time before the effective filing date of the invention to have modified the first conductive portion on the carrier to be less than or equal to 8um to minimize connection distances, thereby improving speed of the device, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 11, Chew discloses a distance between the edge of the orthographic projection of the second conductive portion (2062) on the carrier and the edge of the orthographic projection of the first conductive portion (2061) on the carrier is constant (Figure 2J). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 12, Chew discloses forming the conductive column (206) located on a side of the seed layer (203) away from the carrier based on the seed layer comprises: providing a patterned insulation layer (207) on a side of the seed layer away from the carrier, wherein the patterned insulation layer is provided a hollow (Figure 2K); coupling the seed layer to a power source for electroplating to form the conductive column in a region of the seed layer exposed by the hollow; and removing the patterned insulation layer (207) (Figure 2L). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 13, Chew discloses a material of the bonding layer (205) comprises at least one of solder mask or polyimide (paragraph 135). Han/Chew is silent regarding the bonding layer has a thickness of 3um to 15um. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the bonding layer thickness to be within this range to optimize the thickness of the device against the stability of the chip from shifting, thereby providing a reliable electrical connection (paragraphs 136-137; Figure 5A), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew.
Regarding claim 14, Han discloses a semiconductor packaging structure, comprising:
a chip (A), comprising a first surface and a second surface opposite to the first surface, wherein a pad (C1) is disposed on one of the first surface and the second surface
an encapsulation layer (M), at least covering a side surface of the chip (A)
a re-wiring structure (34), electrically coupled to the pad
Han does not disclose a bonding layer, provided around the chip to securely fix the chip. However, Chew discloses a bonding layer (205) in a form of a film layer of uncured organic photosensitive material (paragraphs 135-136). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the bonding layer of Han to be formed of the material of Chew, since it can provide a seal that avoids shifting for subsequent wiring, thereby providing a reliable electrical connection (paragraphs 136-137; Figure 5A)).
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US Publication No. 2011/0165734) in view of Chew (US Publication No. 2018/0151393), and further in view of Chen et al. (US Publication No. 2011/0227220).
Han/Chew discloses the limitations as discussed in the rejection of claim 14 above. Han/Chew does not disclose the re-wiring structure comprises a first wiring sub-structure and a second wiring sub-structure, wherein the first wiring sub-structure is formed on a side of the encapsulation layer away from the second surface, and the second wiring sub-structure is formed on a side of the encapsulation layer away from the first surface, one of the first wiring sub-structure and the second wiring sub-structure close to a front surface of the chip is electrically coupled with the pad, and the first wiring sub-structure is electrically coupled with the second wiring sub-structure through a conductive column. However, Chen discloses the re-wiring structure comprises a first wiring sub-structure (130) and a second wiring sub-structure (138), wherein the first wiring sub-structure (130) is formed on a side of the encapsulation layer away from the second surface, and the second wiring sub-structure (138) is formed on a side of the encapsulation layer away from the first surface, one of the first wiring sub-structure and the second wiring sub-structure close to a front surface of the chip is electrically coupled with the pad (122), and the first wiring sub-structure is electrically coupled with the second wiring sub-structure through a conductive column (152) (Figure 1). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the re-wiring structure to connect a first and second rewiring sub-structure by a conductive column, as taught by Chen, since it can provide stacking functionality, which improves density of electronic devices (paragraph 24).
Regarding claim 16, Chen discloses a first dielectric layer (106) and a second dielectric layer (118), wherein the first dielectric layer covers the second wiring sub-structure (138), and the second dielectric layer covers the first wiring sub-structure (130) (Figure 2). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew, and further in view of Chen.
Regarding claim 17, Chen discloses wherein the second wiring sub-structure (138) comprises a second re-wiring layer (138) and a conductive protrusion (114/124/120) on a side of the second re-wiring layer away from the chip, and a surface of the conductive protrusions away from the second re-wiring layer is exposed out of the first dielectric layer (Figure 2). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew, and further in view of Chen.
Regarding claim 18, Chen discloses a protective layer (132) provided on a front surface (144) of the chip (102), wherein the protective layer covers an edge of the pad (122). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Han in view of Chew, and further in view of Chen.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hoshino et al. (US Publication No. 2011/0151625) discloses connecting orthographic projections (1) by electrodes (5) (Figure 1).
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/N.R.P/ 1/12/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897