CTNF 18/261,898 CTNF 100612 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election filed on 2/24/2026, without traverse to prosecute the claims of Invention I, claims 1-10 is acknowledged. Information Disclosure Statement The information disclosure statements (IDS) submitted on 7/18/2023 and 1/21/2025 are being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (WO 2012133760 A1, IDS) in view of Takeya (CN 110121770 A) and Liu (CN 108346588 A) . Re Claim 1 Yamauchi teaches a method of manufacturing a substrate (FIG. 10) with chips, the method comprising: preparing a stacked substrate (WT2, page 17 par 4), the stacked substrate including: a plurality of chips (CP1 and CP2, page 6 par 4); a first substrate (WT2) to which the plurality of chips are temporarily bonded; and a second substrate (WA, page 10 par 1) bonded to the first substrate (WT2) via the plurality of chips (FIG. 24); and separating the plurality of chips (CP1 and CP2) bonded to the first substrate (WT2) and the second substrate (WA), from the first substrate (WT2, FIG. 25), wherein the first substrate (WT2), from which the plurality of chips (CP1 and CP2) are separated, includes alignment marks (MW2 points in FIG. 23, page 18 par 3) that are used to ensure alignment when the first substrate and the plurality of chips (CP1 and CP2) are bonded together (FIG. 24), or that are used to measure misalignment after the first substrate and the plurality of chips are bonded together (FIG. 23-25). Yamauchi does not teach separating the plurality of chips bonded to the first substrate and the second substrate, from the first substrate in order to bond the plurality of chips to one surface of a third substrate. Takeya teaches separating the plurality of chips (120, page 6 last par) bonded to the first substrate (51, page 6) and the second substrate (53), from the first substrate (51) in order to bond the plurality of chips (120) to one surface of a third substrate (55, FIG. 1c-e). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Takeya into the structure of Yamauchi since Takeya teaches a method of bonding chips to wafers. The ordinary artisan would have been motivated to modify Takeya in combination with Yamauchi in the above manner for the motivation of bonding the chips to a third substrate to assist in the manufacturing process to build an optimal device. Yamauchi in view of Takeya does not teach the third substrate includes a device layer. Liu teaches the third substrate (300, page 17 par 4) includes a device layer (301, page 17 par 5, FIG. 3A). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Liu into the structure of Yamauchi in view of Takeya since Liu teaches a method of bonding chips to wafers. The ordinary artisan would have been motivated to modify Liu in combination with Yamauchi in view of Takeya in the above manner for the motivation of optimally packaging the wafer to reduce the cost and other benefits. Page 4 par 4 states, “Compared with the traditional SiP, wafer level system package (wafer level package(WLP) is finished on the wafer packaged integrated process, can greatly reduce the area of the package structure and reduce the manufacturing cost, optimize performance, batch manufacturing advantages, such as requirement of reduced workload and device obviously.” 07-22-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (WO 2012133760 A1, IDS) in view of Takeya (CN 110121770 A) and Liu (CN 108346588 A) as applied to claim 1 above, and further in view of Fujii et al. (US 20080099862 A1) . Re Claim 2 Yamauchi in view of Takeya and Liu teaches the method according to claim 1, but does not teach the separating of the plurality of chips from the first substrate includes: forming a plurality of modified layer portions by using a laser beam, in a dividing surface where the first substrate is going to be divided in a thickness direction; and dividing the first substrate by using the plurality of modified layer portions as starting points. Fujii teaches the separating of the plurality of chips (11 contains 1 [0037], and 1 contains a chip unit [0036]) from the first substrate (43) [0051] includes: forming a plurality of modified layer portions (where laser hits 41, amorphous silicon layer [0051]) by using a laser beam (FIG. 4D), in a dividing surface (41) [0051] where the first substrate (43) is going to be divided in a thickness direction; and dividing the first substrate (43) by using the plurality of modified layer portions (where laser contacts layer 41) as starting points (FIG. 4D and 4E). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Fujii into the structure of Yamauchi in view of Takeya and Liu since Fujii teaches a method of cutting a substrate with a laser. The ordinary artisan would have been motivated to modify Fujii in combination with Yamauchi in view of Takeya and Liu in the above manner for the motivation of using a laser to separate the chips from the first substrate. [0055] states, “Here, the laser beam is used to realize the transfer technique, but it is sufficient to separate the translucent support base from the cap layer in a separating layer as irradiated light.” 07-22-aia AIA Claim s 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (WO 2012133760 A1, IDS) in view of Takeya (CN 110121770 A) and Liu (CN 108346588 A) and Fujii et al. (US 20080099862 A1) as applied to claim s 1-2 above, and further in view of Shotokuji et al. (JP 2017041472 A, IDS) Re Claim 3 Yamauchi in view of Takeya and Liu and Fujii teaches the method according to claim 2, wherein the first substrate (Fujii, 43) includes an absorption layer (41) [0051] that is configured to absorb the laser beam between the wafer (43) and the plurality of chips (chips in 11, FIG. 4D and 4E). Yamauchi in view of Takeya and Liu and Fujii does not teach the first substrate includes a silicon wafer. Liu teaches the first substrate (100) includes a silicon wafer (page 10 par 6). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Liu into the structure of Yamauchi in view of Takeya and Liu and Fujii since Liu teaches a method of bonding chips to wafers. The ordinary artisan would have been motivated to modify Liu in combination with Yamauchi in view of Takeya and Liu and Fujii in the above manner for the motivation of using silicon for the substrate material to help optimize device performance. Page 4 par 4 states, “Compared with the traditional SiP, wafer level system package (wafer level package(WLP) is finished on the wafer packaged integrated process, can greatly reduce the area of the package structure and reduce the manufacturing cost, optimize performance, batch manufacturing advantages, such as requirement of reduced workload and device obviously.” Yamauchi in view of Takeya and Liu and Fujii does not teach the laser beam passes through the silicon wafer, and forms the modified layer portions in the absorption layer. Shotokuji teaches the laser beam (page 3 par 4 states, “…a pulse laser beam having a wavelength that is transparent to the silicon substrate is irradiated from the first substrate 3 side made of the silicon substrate …”) passes through the silicon wafer, and forms the modified layer portions in the absorption layer (5 is a resin layer and will absorb laser light, FIG. 3). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Shotokuji into the structure of Yamauchi in view of Takeya and Liu and Fujii since Shotokuji teaches a method of applying a laser to a wafer structure. The ordinary artisan would have been motivated to modify Shotokuji in combination with Yamauchi in view of Takeya and Liu and Fujii in the above manner for the motivation of optimally cutting the wafer to help the manufacturing process. Page 2 par 1 states, “By cutting the semiconductor wafer formed in this way along the planned dividing line, the region where the device is formed is divided to manufacture individual devices.” Re Claim 4 Yamauchi in view of Takeya and Liu and Fujii and Shotokuji teaches the method according to claim 3, but does not explicitly teach the alignment marks are formed between the silicon wafer and the absorption layer. Yamauchi does teach integrating the alignment marks (RS1 region between MC2 points, FIG. 10) are formed between the first wafer (WT2) and the absorption layer (RS2, page 17 par 4, resin absorbs laser light) It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yamauchi into the structure of Yamauchi in view of Takeya and Liu and Fujii and Shotokuji. The ordinary artisan would have been motivated to modify Yamauchi in combination with Yamauchi in view of Takeya and Liu and Fujii and Shotokuji in the above manner for the motivation of optimally forming alignment marks to ensure each chip is positioned accurately. Page 21 par 4 states, “The alignment of the chips CPi of one layer (i-th layer) may be performed on the temporary substrate WTi different from the substrate WA. Therefore, each chip can be positioned accurately and easily.” Re Claim 5 Yamauchi in view of Takeya and Liu and Fujii and Shotokuji teaches the method according to claim 4, but does not explicitly teach the laser beam passes through the silicon wafer and the alignment marks, and forms the modified layer portions in the absorption layer. Fujii does teach the laser beam (FIG. 4D) passes through the wafer (40) [0051] and contacts a (laser absorbing) amorphous silicon layer (41) and would therefore have a similar physical response as the enclosed invention. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Fujii into the structure of Yamauchi in view of Takeya and Liu and Fujii and Shotokuji. The ordinary artisan would have been motivated to modify Fujii in combination with Yamauchi in view of Takeya and Liu and Fujii and Shotokuji in the above manner for the motivation of using a laser to optimally removing the chips from the substrate. [0055] states, “Here, the laser beam is used to realize the transfer technique, but it is sufficient to separate the translucent support base from the cap layer in a separating layer as irradiated light.” 07-22-aia AIA Claim s 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (WO 2012133760 A1, IDS) in view of Takeya (CN 110121770 A) and Liu (CN 108346588 A) and Fujii et al. (US 20080099862 A1) as applied to claim s 1-2 above, and further in view of Yoshida (JP 2016018807 A) . Yamauchi in view of Takeya and Liu and Fujii teaches the method according to claim 2, but does not explicitly teach the alignment marks allow the laser beam to pass therethrough, Yamauchi does teach alignment marks (use WA space between MW1 regions in FIG. 23, WA is second substate) allow the laser beam to pass therethrough (FIG. 23, page 27 par 4 states, “each chip maybe separated from the temporary substrate WTi by using a laser ablation technique”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yamauchi into the structure of Yamauchi in view of Takeya and Liu and Fujii. The ordinary artisan would have been motivated to modify Yamauchi in combination with Yamauchi in view of Takeya and Liu and Fujii in the above manner for the motivation of using a laser beam to make the processing time faster by allowing the laser beam to pass through layers of the structure when trying to bond and remove chips from substrates as it is time consuming. Page 3 par 1 states, “However, when such a technique is used to join a plurality of chips on a substrate by repeating the operation of placing one chip on the substrate and performing the joining operation of the chip, there are many cases. There is a problem that it takes a long time.” Yamauchi in view of Takeya and Liu and Fujii does not teach the alignment marks absorb an infrared ray having a different wavelength from that of the laser beam. Yoshida teaches the alignment marks (9a, FIG. 1B) include a metal silicide film (page 2 par 6). When a laser beam is shined on metal silicide materials, the metal silicide will absorb infrared light of a different wavelength than the laser beam’s wavelength. There are an infinite amount of values the infrared light may be and therefore the infrared wavelength must be different than the laser beam’s wavelength. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yoshida into the structure of Yamauchi in view of Takeya and Liu and Fujii since Yoshida teaches using a metal silicide for a laser alignment mark that would absorb an infrared ray when a laser beam is shined on the metal silicide. The ordinary artisan would have been motivated to modify Yoshida in combination with Yamauchi in view of Takeya and Liu and Fujii in the above manner for the motivation of using a metal silicide material for alignment mark to absorb the laser light. Page 2 par 6 states, “compound layer is formed on the irradiated portion by irradiating a laser beam to a mark formation planned region of the metal film, and this metal silicon compound layer is used as an alignment mark.” Re Claim 7 Yamauchi in view of Takeya and Liu and Fujii and Yoshida teaches the method according to claim 6, wherein the alignment marks (Yoshida, 9a, FIG. 1B) include a metal silicide film (page 2 par 6) . 07-22-aia AIA Claim s 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (WO 2012133760 A1, IDS) in view of Takeya (CN 110121770 A) and Liu (CN 108346588 A) and Fujii et al. (US 20080099862 A1) and Yoshida (JP 2016018807 A) as applied to claim s 1-2 and 6 above, and further in view of Aoude et al. (US 20200296837 A1) . Re Claim 8 Yamauchi in view of Takeya and Liu and Fujii and Yoshida teaches the method according to claim 6, but does not teach a wavelength of the laser beam is 8,800 nm to 11,000 nm. Aoude teaches the wavelength of the laser beam is 9.8 µm [0084]. It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Aoude into the structure of Yamauchi in view of Takeya and Liu and Fujii and Yoshida since Aoude teaches a method of using a laser beam to process a semiconductor device. The ordinary artisan would have been motivated to modify Aoude in combination with Yamauchi in view of Takeya and Liu and Fujii and Yoshida in the above manner for the motivation of using a laser beam wavelength of optimal distance. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal laser beam wavelength . 07-22-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (WO 2012133760 A1, IDS) in view of Takeya (CN 110121770 A) and Liu (CN 108346588 A) and Fujii et al. (US 20080099862 A1) and Yoshida (JP 2016018807 A) as applied to claim s 1-2 and 6 above, and further in view of Takase et al. (WO 2013172110 A1) . Re Claim 9 Yamauchi in view of Takeya and Liu and Fujii and Yoshida teaches the method according to any one of claim 6, but does not teach the wavelength of the infrared ray is 1,000 nm to 2,000 nm. Takase page 9 last par states, “Specifically, the wavelength of infrared rays that can be absorbed by the above structure is, for example, in the range of 1 μm to 20 μm …” It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Takase into the structure of Yamauchi in view of Takeya and Liu and Fujii and Yoshida since Takase teaches a method of separating wafer structures with a laser. The ordinary artisan would have been motivated to modify Takase in combination with Yamauchi in view of Takeya and Liu and Fujii and Yoshida in the above manner for the motivation of using an infrared ray with a wavelength of optimal distance. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal infrared ray wavelength . 07-22-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi (WO 2012133760 A1, IDS) in view of Takeya (CN 110121770 A) and Liu (CN 108346588 A) as applied to claim 1 above, and further in view of Masuda (WO 2020080328 A1) Re Claim 10 Yamauchi in view of Takeya and Liu teaches the method according to claim 1, but does not teach comprising bonding, to the first substrate from which the plurality of chips are separated, chips that are different from the plurality of chips. Masuda teaches comprising bonding (FIG. 3c and 3d), to the first substrate (12, page 30 par 6) from which the plurality of chips are separated (62, page 30 par 7), chips that are different from the plurality of chips (substrate will be reused, FIG. 3C shows 12 bonded to chips 62, when the substrate is reused the chips 62 will be different from the previous batch of chips 62, page 30 par 3 states, “And for reuse of the carrier substrate, removal of the temporary adhesive remaining on the carrier substrate is exemplified.”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Masuda into the structure of Yamauchi in view of Takeya and Liu since Masuda teaches a method of reusing a substrate. The ordinary artisan would have been motivated to modify Masuda in combination with Yamauchi in view of Takeya and Liu in the above manner for the motivation of reusing a substrate for cost reduction during manufacturing. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENNETH MARK SIPLING/ Examiner, Art Unit 2818 /DUY T NGUYEN/ Primary Examiner, Art Unit 2818 6/11/26 Application/Control Number: 18/261,898 Page 2 Art Unit: 2818 Application/Control Number: 18/261,898 Page 3 Art Unit: 2818 Application/Control Number: 18/261,898 Page 4 Art Unit: 2818 Application/Control Number: 18/261,898 Page 5 Art Unit: 2818 Application/Control Number: 18/261,898 Page 6 Art Unit: 2818 Application/Control Number: 18/261,898 Page 7 Art Unit: 2818 Application/Control Number: 18/261,898 Page 8 Art Unit: 2818 Application/Control Number: 18/261,898 Page 9 Art Unit: 2818 Application/Control Number: 18/261,898 Page 10 Art Unit: 2818 Application/Control Number: 18/261,898 Page 11 Art Unit: 2818 Application/Control Number: 18/261,898 Page 12 Art Unit: 2818 Application/Control Number: 18/261,898 Page 13 Art Unit: 2818 Application/Control Number: 18/261,898 Page 14 Art Unit: 2818
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