Prosecution Insights
Last updated: April 19, 2026
Application No. 18/262,100

ELECTROSTATIC PROTECTION STRUCTURE AND PREPARATION METHOD THEREFOR

Non-Final OA §103
Filed
Jul 19, 2023
Examiner
GRAY, AARON J
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Csmc Technologies Fab2 Co. Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
406 granted / 497 resolved
+13.7% vs TC avg
Strong +31% interview lift
Without
With
+30.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
33 currently pending
Career history
530
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
50.1%
+10.1% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 497 resolved cases

Office Action

§103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species V in the reply filed on 02/26/2026 is acknowledged. Claims 7-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/26/2026. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. Al. (US 20200027873 A1 hereinafter Chen) and further in view of Chen et. Al. (US 20150085407 A1 hereinafter Chen407). Regarding claims 1 and 15, Chen teaches in Figs. 5-6 with associated text an electrostatic protection structure, comprising: a substrate 20, having a first conductivity type ([0044]); wherein an upper surface layer of the first deep well is provided with a first well region 22 and a second well region 26 which are isolated from each other and are floating (Fig. 5, [0044] well which acts as a base is unconnected and so is floating), both the first well region and the second well region have the second conductivity type ([0044]), an upper surface layer of the first well region is provided with a first heavily doped region 24 and a second heavily doped region 40 isolated from each other (Fig. 6, [0049]), an upper surface layer of the second well region is provided with a third heavily doped 42 region and a fourth heavily doped region 28 isolated from each other (Fig. 6, [0049]), the first heavily doped region, the second heavily doped region, the third heavily doped region and the fourth heavily doped region have the first conductivity type ([0044] and [0047]), the first heavily doped region is led out as a first electrode (first pin) and is connected to an electrostatic port, the second heavily doped region is led out as a second electrode, the third heavily doped region is led out as a third electrode and is electrically connected to the second electrode (Fig. 6, [0047]), and the fourth heavily doped region is led out as a fourth electrode (second pin). Chen does not specify a buried layer, located in the substrate and having a second conductivity type opposite to the first conductivity type; a first deep well, located on an upper surface of the buried layer and floating, and having the first conductivity type; a second deep well, located on the upper surface of the buried layer, and having the second conductivity type, a partial region of the second deep well being in contact with the substrate, the second deep well being adjacent to the first deep well and being located at a periphery of the first deep well; and a third deep well, located in the buried layer and completely in contact with the substrate, having the first conductivity type, the third deep well being adjacent to the second deep well and being located at a periphery of the second deep well; an upper surface layer of the second deep well is provided with a third well region, the third well region has the second conductivity type, and an upper surface layer of the third well region is provided with a floating fifth heavily doped region having the second conductivity type; and wherein an upper surface layer of the third deep well is provided with a fourth well region, the fourth well region has the first conductivity type, an upper surface layer of the fourth well region is provided with a sixth heavily doped region, the sixth heavily doped region has the first conductivity type, and the sixth heavily doped region is led out and is grounded together with the fourth electrode. Chen407 discloses in Fig. 2 with associated text a buried layer 204, located in a substrate 202 and having a second conductivity type (n-type) opposite to a first conductivity type (p-type Fig. 2, [0028]); a first deep well (portion of 208 surrounded by 212, 204 and 216), located on an upper surface of the buried layer and floating, and having the first conductivity type (Fig. 2, [0028]); a second deep well, located on the upper surface of the buried layer (222, 212, 226 and 216), and having the second conductivity type (Fig. 2, [0028]), a partial region of the second deep well being in contact with the substrate (Fig. 2), the second deep well being adjacent to the first deep well and being located at a periphery of the first deep well (Fig. 2, [0028]); and a third deep well 232,238 and portion of 208 outside of the second deep well), located in the buried layer and completely in contact with the substrate, having the first conductivity type (Fig. 2, [0028]), the third deep well being adjacent to the second deep well and being located at a periphery of the second deep well (Fig. 2, [0028]); an upper surface layer of the second deep well is provided with a third well region (222, 224 and 226), the third well region has the second conductivity type (Fig. 2, [0028]), and an upper surface layer of the third well region is provided with a floating fifth heavily doped region (244, 248 and 252) having the second conductivity type (Fig. 6, [0028]); and wherein an upper surface layer of the third deep well is provided with a fourth well region (232 and 238), the fourth well region has the first conductivity type, an upper surface layer of the fourth well region is provided with a sixth heavily doped region (258 and 264) (Fig. 2, [0028]) , the sixth heavily doped region has the first conductivity type, and the sixth heavily doped region is led out and is grounded together with the fourth electrode 104 (Fig. 2, [0017] and [0028]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Chen 407 surrounding the device structures of Chen because according to Chen407 the N-type sinker regions 212, 214, 216, 218, 220 partition the P-type epitaxial layer 208 into separate P-type regions 213, 215, 217 having a respective BJT element 120, 122, 126 fabricated therein. In this regard, N-type sinker regions 212, 216 define the lateral boundaries of the first protection circuitry arrangement 110 while sinker region 214 separates the base regions 213, 215 of the adjacent BJTs 120, 122, and sinker regions 218, 220 define the lateral boundaries of the second protection circuitry arrangement 110 [0033] so that such an arrangement would be useful in separating the device of Chen from any adjacent circuitry such as a device to be protected. PNG media_image1.png 352 465 media_image1.png Greyscale Regarding claims 2, Chen teaches the first conductivity type is a P-type ([0049]), and the second conductivity type is a N-type ([0049]), and wherein when the electrostatic port inputs an electrostatic voltage, the first heavily doped region, the first well region and the second heavily doped region together form a first PNP transistor; the third heavily doped region, the second well region and the fourth heavily doped region together form a second PNP transistor; and the first PNP transistor is connected to the second PNP transistor in series (Fig. 6, [0049]). Regarding claims 3, Chen teaches the electrostatic voltage is a positive voltage, the first electrode serves as an emitter of the first PNP transistor, the second electrode serves as a collector of the first PNP transistor, and the first well region serves as a base of the first PNP transistor; and the third electrode serves as an emitter of the second PNP transistor, the fourth electrode serves as a collector of the second PNP transistor, and the second well region serves as a base of the second PNP transistor ([0049]). Regarding claims 4, Chen teaches when the electrostatic voltage is a negative voltage, the first electrode serves as a collector of the first PNP transistor, the second electrode serves as an emitter of the first PNP transistor, and the first well region serves as a base of the first PNP transistor; and the third electrode is a collector of the second PNP transistor, the fourth electrode is an emitter of the second PNP transistor, and the second well region serves as a base of the second PNP transistor ([0049]). Regarding claims 5, Chen teaches there exists at least two first heavily doped regions, at least two second heavily doped regions, at least two third heavily doped regions, and at least two fourth heavily doped regions; and wherein a plurality of the first heavily doped regions are isolated from each other, a plurality of the second heavily doped regions are isolated from each other, a plurality of the third heavily doped regions are isolated from each other, and a plurality of the fourth heavily doped regions are isolated from each other (Fig. 8 2 more BJTs 48 and 50 are formed with the same structure and connections so that the first heavily doped regions, and second heavily doped regions are duplicated in different first and second wells so that here exists at least two first heavily doped regions, at least two second heavily doped regions, at least two third heavily doped regions, and at least two fourth heavily doped regions; and wherein a plurality of the first heavily doped regions are isolated from each other, a plurality of the second heavily doped regions are isolated from each other, a plurality of the third heavily doped regions are isolated from each other, and a plurality of the fourth heavily doped regions are isolated from each other the claim wouldn’t necessarily require for example that the two first heavily doped regions and the and the two second heavily doped regions are formed in the same first well. Regarding claims 6, Chen teaches the plurality of the first heavily doped regions are electrically connected to each other as the first electrode, the plurality of the second heavily doped regions are electrically connected to each other as the second electrode, the plurality of the third heavily doped regions are electrically connected to each other as the third electrode, and the plurality of the fourth heavily doped regions are electrically connected to each other as the fourth electrode (Fig. 8). Regarding claims 9, Chen teaches the upper surface layer of the first deep well is further provided with a plurality of sixth well regions (30, 53 and 55), the plurality of sixth well regions are arranged alternatively with the first well region and the second well region, and the sixth well regions have the first conductivity type (Figs. 6 and 9, [0044] and [0050]). Regarding claims 10, Chen in view of Chen407 teaches the second deep well is a circular structure and surrounds the periphery of the first deep well, and the third deep well is a circular structure and surrounds the periphery of the second deep well (Chen407 [0028]). Regarding claims 11, Chen in view of Chen407 teaches a width of a sidewall (with of sidewall contacting STIs 210) of the third well region is less than a width of a sidewall of the second deep well (Fig. 2). Regarding claims 12, Chen in view of Chen407 teaches a width of a sidewall of the fourth well region (with of sidewall contacting STIs 210) is less than a width of a sidewall of the third deep well (Fig. 2). Regarding claims 13, Chen in view of Chen407 teaches the electrostatic protection structure according to claim 1, further comprising: a first isolation structure (portion 210 of Chen407), located in the upper surface layer of the first deep well passing through an upper surface of the first deep well to a first well region; and a second isolation structure (other portion of 210 of Chen407), located in the upper surface layer of the first deep well, and passing through the upper surface of the first deep well to the second well region (Fig. 2). Chen407 teaches does not specify the first isolation structure, wherein the first isolation structure is arranged alternatively with the first heavily doped region and the second heavily doped region; and wherein the second isolation structure is arranged alternatively with the third heavily doped region and the fourth heavily doped region however Chen407 teaches the first isolation structure is arranged alternatively with any heavily doped region at the surface (Fig. 2) so that by arranging them alternatively with the heavily doped regions of Chen the first isolation structure would be arranged alternatively with the first heavily doped region and the second heavily doped region; and the second isolation structure, would be arranged alternatively with the third heavily doped region and the fourth heavily doped region. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Chen 407 surrounding the device structures of Chen because according to Chen407 such structures laterally isolate subsequently formed neighboring contact regions [0034] so that such an arrangement would be useful in separating the highly doped regions of Chen. Regarding claims 14, Chen in view of Chen407 teaches third isolation structures (portion of 208 between 232 and 222), located in upper surface layers of the second deep well and the third deep well, and located between the fifth heavily doped region and the sixth heavily doped region; fourth isolation structures (210 of Chen407 between 256 and 244), located in the upper surface layer of the fourth well region, and located between the first heavily doped region and the fifth heavily doped region and between the fourth heavily doped region and the fifth heavily doped region (Fig. 2, [0028]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AARON J GRAY/Examiner, Art Unit 2897
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Prosecution Timeline

Jul 19, 2023
Application Filed
Mar 18, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+30.9%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 497 resolved cases by this examiner. Grant probability derived from career allow rate.

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