Prosecution Insights
Last updated: May 29, 2026
Application No. 18/263,435

PLATING METHOD AND PLATING APPARATUS

Non-Final OA §103
Filed
Jul 28, 2023
Priority
Feb 03, 2021 — JP 2021-015670 +1 more
Examiner
MARUF, SHEIKH
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
473 granted / 545 resolved
+18.8% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
26 currently pending
Career history
580
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
89.7%
+49.7% vs TC avg
§102
6.1%
-33.9% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 545 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election without traverse of Group -I in the reply filed on 02/04/2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over SHOZO et al. (FP: JP2010185113A, attached in IDS), herein after SHOZO, in view of known arts like OOMI HIROSHI (FP: JP2001102448A, attached in IDS), herein after OOMI. Regarding claim 1, SHOZO teaches a plating method, in paragraphs [0005]-[0008],[0022], [0024], [0027], [0037], [0040]-[0045], [0051], [0053], comprising: preparing a substrate having a seed layer of cobalt or a cobalt alloy formed in a recess (forming an electroless copper plating layer uniform to the depth even for a via of a high aspect ratio, which comprises: depositing a displacement plateable metal film such as Co through CVD. The present invention is characterized by immersing the substrate in which the hole is formed in the electroless copper plating solution described … and forming an embedded wiring made of an electroless copper plating layer in the hole.); performing a displacement plating processing on the substrate to replace a surface layer of the seed layer with copper by using a first plating liquid containing a copper ion (then executing an electroless copper plating process on the metal film); performing, after the performing of the displacement plating processing, a reduction plating processing on the recess of the substrate by using a second plating liquid containing the copper ion and a reducing agent (burying Cu in the via through electroplating with the electroless copper plating layer formed through the electroless copper plating process as a seed layer. also describes a feature in which a reducing agent can be used for a component of an electroless copper plating liquid and a condition such as a temperature for electroless copper plating can be selected as appropriate in accordance with physical properties, etc., of an object to be plated.). SHOZO does not explicitly teach executing burying of Cu in the via through electroless plating. However, executing burying of Cu in the via through electroless plating is a well-known feature as described in OOMI (Paragraph [0009]-[0012]), A step of removing, a step of embedding a Cu plating layer in the connection hole by forming a Cu plating layer on the Cu seed layer by an electroless plating method using a copper plating solution, and the embedded Cu plating layer And a step of forming an upper layer wiring thereon). Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use SHOZO’s plating method with i teaching from OOMI so that the time required for the CMP process can be shortened, and thus the wiring formation time can be shortened. Regarding claim 2, SHOZO does not explicitly teach the plating method of Claim 1, wherein the performing of the reduction plating processing is performed by using the second plating liquid which is produced by mixing the first plating liquid containing the reducing agent in a proportion smaller than a preset value and a third plating liquid containing the reducing agent in a proportion larger than that of the first plating liquid. However, a reducing agent can be used for a component of an electroless copper plating liquid and a condition such as a temperature for electroless copper plating can be selected as appropriate in accordance with physical properties, etc., of an object to be plated as known to people skilled in the art and also taught in SHOZO Paragraph [0023]-[0035]. The ratio and the adjustment of a reducing agent and the rotation number of a substrate are merely features selected as appropriate in accordance with physical properties, etc., of an object to be plated such that device can be formed with proper thickness and size. Regarding claim 3, SHOZO teaches the plating method of Claim 1, wherein the first plating liquid contains no reducing agent. According to the electroless copper plating method of the present invention, by using an electroless copper plating solution containing chlorine ions, the formation speed of the electroless copper plating layer can be increased regardless of the inner diameter of the holes formed in the substrate. Chlorine ion is not an reducing agent (Paragraphs [0023]-[0035]). Regarding claim 4, SHOZO teaches the plating method of Claim 1, wherein the performing of the reduction plating processing is performed on the substrate wet with the first plating liquid. That is, the electroless copper plating solution generally contains a soluble copper salt as a copper ion source, a copper ion complexing (chelating) agent, and a reducing agent, and further contains necessary additives, and has a pH value. Is an aqueous solution adjusted to about 12-13. As a copper salt which is a copper ion source, any copper salt may be used as long as it can generate copper ions when dissolved in water. For example, copper sulfate, copper nitrate, copper chloride, copper bromide, copper oxide, copper hydroxide, Examples include copper pyrophosphate. Any complexing agent for copper ions may be used as long as it can form a complex with copper ions. Examples thereof include oxycarboxylic acids such as lactic acid, malic acid, tartaric acid, citric acid, and gluconic acid, or salts thereof, nitrilotriacetic acid. , Ethylenediaminetetraacetic acid (EDTA), hydroxyethylethylenediaminetriacetic acid, diethylenetriaminepentaacetic acid, triethylenetetraminehexaacetic acid, 1,3-propanediaminetetraacetic acid, hydroxyethyliminodiacetic acid, dihydroxyethylglycine, glycol etherdiaminetetraacetic acid, asparagine Examples thereof include aminocarboxylic acids such as acid diacetic acid, methylglycine diacetic acid, glutamic acid diacetic acid, and ethylenediamine disuccinic acid, or salts thereof, triethanolamine, and glycerin Paragraph [0023]-[0035]). Regarding claim 5, SHOZO teaches the plating method of Claim 1, wherein the seed layer is formed by a CVD method (Paragraph [0005]. However, since the electrical resistivity of tungsten is as high as about 20 μΩcm, and a high temperature process of about 400 ° C. is required when filling tungsten by CVD). Regarding claim 6, SHOZO teaches the plating method of Claim 1, wherein the seed layer has a thickness equal to or larger than 1 nm (According to the present invention, even a hole having a small diameter and a high aspect ratio can form a uniform copper plating layer all the way to the back. For example, the diameter is 1 to 10 μm and the aspect ratio is 5 to 10 A hole is preferable, and in particular, a hole having a diameter of 2 to 6 μm and an aspect ratio of 10 to 30 is more preferable.). According to Paragraph [0019] of OOMI, Hence it is possible to adjust hole size as known to people skilled in the art in order for the method to prepare a device meeting functionality. In addition, according to the method for forming a buried wiring of the present invention, since a uniform electroless copper plating layer is formed to the depth of the hole regardless of the size of the inner diameter of the hole, it is possible to form a highly reliable buried wiring inside the hole. Regarding claim 7, SHOZO teaches the plating method of Claim 1, wherein the second plating liquid has a temperature higher than that of the first plating liquid. A reducing agent can be used for a component of an electroless copper plating liquid and a condition such as a temperature for electroless copper plating can be selected as appropriate in accordance with physical properties, etc., of an object to be plated as known to people skilled in the art. The ratio and the adjustment of a reducing agent and the rotation number of a substrate are merely features selected as appropriate in accordance with physical properties, etc., of an object to be plated (Paragraph [0023]-[0035]. A person skilled in the art would be provided only by the conditions set forth in claims would be able to achieve in order meet device need. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHEIKH MARUF/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jul 28, 2023
Application Filed
Apr 22, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+10.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 545 resolved cases by this examiner. Grant probability derived from career allowance rate.

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