DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Claim Objections 3
IV. Claim Rejections - 35 USC § 112 4
A. Claims 1-3, 6, 8-11, 13, 15-18, 22-26, 29, and 31-37 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 4
1. Claims 1 and 24 4
2. Claim 25 5
B. Claims 6 and 29 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 6
V. Claim Rejections - 35 USC § 103 6
A. Claims 1-3, 6, 8-11, 13, 18, 22-4, 26, 29, and 31-37 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2019/143664 (“Hersam”) in view of Ting Lei, et al., entitled “Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes” in Nature Communications (2019)10:2161 (“Lei”). 7
VI. Allowable Subject Matter 17
VII. Response to Arguments 18
Conclusion 21
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 06/02/2026 has been entered.
III. Claim Objections
Claims 3, 17, and 26 objected to because of the following informalities:
Bearing in mind the amendment to claims 1 and 24, limiting “the semiconducting material” to “consist[ing] essentially of ultrahigh purity semiconducting single-walled carbon nanotubes (SWCNTs) having a semiconducting purity of at least 99.9%”, replace claims 3 and 26 with the following version for clarity, particularly with regard to antecedent basis:
3. (Original) The OCGT of claim 1, wherein the semiconducting material is
26. (Original) The method of claim 24, wherein the semiconducting material is
Replace claim 17 with the following version, for clarity:
17. (Currently amended) A common-source amplifier comprising the OCGT of claim 1, wherein the OCGT is used in the common-source amplifier to attain -1 and a length-scaled signal gain of about 230 μm-1.
Appropriate correction is required.
IV. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claims 1-3, 6, 8-11, 13, 15-18, 22-26, 29, and 31-37 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
1. Claims 1 and 24
Each of independent claims 1 and 24 was amended to include the limitation, “each of the first and second dielectric layers an ultrathin high-k dielectric layer having a thickness of less than 20 nm”. There is not support for the claimed range of “less than 20 nm”. Throughout the Instant Application, the sole thickness is 12 nm. There are no other examples of thicknesses or any range provided. Moreover, there is no analysis provided in the Instant Application that a thicknesses in a range of 13 nm to 20 nm would provide the claimed properties of “unipolar p-type transport with an Ion/Ioff ratio of greater than 104, an output current of about 10 μA∙μm-1, and a leakage current of about 10 pA∙μm-1 in the channel length of less than about 300 nm”.
The invention is, for purposes of the “written description” inquiry, whatever is now claimed. Vas-Cath, Inc. v. Mahurkar, 935 F.2d 1555, 1563-64 (Fed. Cir. 1991). One shows “possession” by descriptive means such as words, structures, figures, diagrams, and formulas that fully set forth the claimed invention. Lockwood v. American Airlines, Inc., 107 F.3d 1565, 1572 (Fed. Cir. 1997). It is not sufficient for purposes of the written description requirement that the disclosure, when combined with the knowledge in the art, would lead one to speculate as to modifications that the inventor might have envisioned, but failed to disclose. Id.
Claims 2, 3, 6, 8-11, 13, 15-18, 22, 23, 25, 26, 29, and 31-37 are rejected for including the same indefinite feature by depending from either claim 1 or claim 24, either directly or indirectly.
2. Claim 25
Claim 25 reads,
25. (Original) The method of claim 24, wherein said forming the thin film is performed by chemical vapor deposition (CVD), mechanical exfoliation, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
There is not support in the Instant Application to show that the Instant Inventors were in possession of forming the claimed “thin film formed of a semiconductor material” that “consists essentially of ultrahigh purity semiconducting single-walled carbon nanotubes (SWCNTs) having a semiconducting purity of at least 99.9%” is made by any of the processes recited in claim 25. Instead, there is only support in the Instant Application for forming said SWCNTs by solution processing. Consequently, claim 25 introduced new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
B. Claims 6 and 29 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 29 read,
6. (Currently Amended) The OCGT of claim 1, wherein the thin film comprises an SWCNT random network with a linear density of about 40 CNTs∙μm-1.
29. (Currently Amended) The method of claim 24, wherein the thin film comprises an SWCNT random network with a linear density of about 40 CNTs∙μm-1.
The limitation “an SWCNT random network” has unclear antecedent basis because claims 1 and 24, were amended to include the limitation, “the semiconducting material consists essentially of ultrahigh purity semiconducting single-walled carbon nanotubes (SWCNTs) having a semiconducting purity of at least 99.9%”.
Applicant may overcome the rejection by using, e.g., the following language, “wherein the thin film comprises the SWCNTs in a configuration of a random network …”
V. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3, 6, 8-11, 13, 18, 22-4, 26, 29, and 31-37 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2019/143664 (“Hersam”) in view of Ting Lei, et al., entitled “Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes” in Nature Communications (2019)10:2161 (“Lei”).
Claim 1 reads,
1. (Currently amended) An ohmic-contact-gated transistor (OCGT), comprising:
[1] a bottom gate electrode formed on a substrate;
[2] a first dielectric layer formed on the bottom gate electrode;
[3] a thin film formed of a semiconducting material on the first dielectric layer;
[4] a bottom contact formed on and in ohmic contact with a part of the thin film;
[5] a second dielectric layer conformally grown on the bottom contact to result in a self-aligned dielectric extension from the bottom contact on the thin film; and
[6] a top contact formed on the second dielectric layer on the top of the bottom contact and fully overlapping with the dielectric extension to define a device channel having a channel length in the thin film under the dielectric extension between the bottom contact and the top contact,
[7] wherein the semiconducting material consists essentially of ultrahigh purity semiconducting single-walled carbon nanotubes (SWCNTs) having a semiconducting purity of at least 99.9%, and each of the first and second dielectric layers is an ultrathin high-k dielectric layer having a thickness of less than 20 nm, k being a dielectric constant,
[8] whereby the OCGT provides unipolar p-type transport with an Ion/Ioff ratio of greater than 104, an output current of about 10 μA∙μm-1, and a leakage current of about 10 μA∙μm-1 in the channel,
[9] wherein the channel has the channel length of less than about 300 nm.
With regard to claim 1, Hersam discloses, generally in Figs. 1A-1B,
1. (Currently amended) An ohmic-contact-gated transistor (OCGT), comprising:
[1] a bottom gate electrode 110 formed on a substrate [“SASC MoS2 FETs were fabricated on local gates (Au) 110 on undoped Si wafers with about 300 nm thick thermal oxide 120” (p. 27, line 25); also p. 22, lines 16 and 19-21];
[2] a first dielectric layer 130 formed on the bottom gate electrode 110 [“The gate dielectric 130 and the dielectric extension 170 are both about 30 nm thick ALD-grown Al2O3.” (p. 27, lines 27-28)];
[3] a thin film 140 formed of a semiconducting material [e.g. MoS2] on the first dielectric layer 130 [p. 22, lines 5-16];
[4] a bottom contact 150 formed on a part of the thin film 140 [Fig. 1B; 150 is Au; p. 23, lines 14-20];
[5] a second dielectric layer 170 conformally grown on the bottom contact 150 to result in a self-aligned dielectric extension 170 from the bottom contact on the thin film 140 [“The gate dielectric 130 and the dielectric extension 170 are both about 30 nm thick ALD-grown Al2O3.” (p. 27, lines 27-28)]; and
[6] a top contact 180 formed on the second dielectric layer 170[,] on the top of the bottom contact 150[,] and fully overlapping with the dielectric extension 170 to define a device channel in the thin film 140 under the dielectric extension 170 between the bottom contact 150 and the top contact 180 [as shown in Figs. 1A and 1B; p. 23, lines 14-20; paragraph bridging pp. 27-28)],
[7] wherein the semiconducting material consists essentially of …[ MoS2]…, and each of the first and second dielectric layers is an ultrathin high-k dielectric layer having a thickness of …[30 nm] …, k being a dielectric constant [“The gate dielectric 130 and the dielectric extension 170 are both about 30 nm thick ALD-grown Al2O3.” (p. 27, lines 27-28)
[8] … [not taught] …
[9] wherein the channel has the channel length of less than about 300 nm [Abstract].
With regard to features [7] and [8] of claim 1 and claims 3 and 6,
[7] wherein the semiconducting material consists essentially of ultrahigh purity semiconducting single-walled carbon nanotubes (SWCNTs) having a semiconducting purity of at least 99.9%, and each of the first and second dielectric layers is an ultrathin high-k dielectric layer having a thickness of less than 20 nm, k being a dielectric constant,
[8] whereby the OCGT provides unipolar p-type transport with an Ion/Ioff ratio of greater than 104, an output current of about 10 μA∙μm-1, and a leakage current of about 10 pA∙μm-1 in the channel,
3. (Original) The OCGT of claim 1, wherein the semiconducting material comprises a solution-processed semiconducting material.
6. (Original) The OCGT of claim 4, wherein the thin film comprises an SWCNT random network with a linear density of about 40 CNTs∙μm-1.
Hersam does not limit the semiconductor material of the self-aligned short-channel transistor (SASC) that includes only the first semiconductor layer, such as the transistor shown on the left in Fig. 1A of Hersam. In this regard, Hersam states,
In one embodiment, the first semiconductor layer formed of an atomically thin material comprising MoS2, MoSe2, WS2, WSe2, InSe, GaTe, black phosphorus (BP), or related two-dimensional materials.
(Hersam: p. 4, lines 15-17; emphasis added)
Hersam further teaches that SWCNTs can be used as the second semiconductor material in van der Waals heterojunctions (vdWHs) shown on the right in Fig. 1, as well as in Figs. 3A, 4B, and 13A. See Hersam at p. 5, lines 4-7; p. 7, lines 4-8; p. 23, lines 9-13; p. 25, lines 15-19; p. 48, claim 15; p. 51, claim 33.
Hersam does not, however, show in the embodiment shown in Fig. 1B that the semiconductor layer 140 is the SWCNTs as limited in feature [7] of claim 1 and claims 3 and 6.
Lei, like Hersam, teaches a thin-film transistor (TFT) including vapor deposited metal electrodes and ALD deposited Al2O3 dielectric layers. (Lei: abstract; p. 4, Fig. 1a; pp. 3-5, section entitled “Device fabrication and stability consideration”; p. 9, section entitled, “Fabrication of flexible CNT circuits on polyimide substrates”)
Lei further teaches forming the semiconductor layer of the TFT using solution-processed SWCNTs of “ultrahigh purity (99.997%) and resulting in a line density of about “35-40 CNTs/μm” (Lei: abstract: pp. 2-5; p. 4, Fig. 1a; pp. 3-5, section entitled “Device fabrication and stability consideration”; p. 9, section entitled, “Fabrication of flexible CNT circuits on polyimide substrates”). Therefore, Lei teaches each of the limitations recited in claims 3-6 and 26-29, above.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the solution-processed, ultra-high purity SWCNTs having a line density of 35-40 CNTs/μm deposited as in Lei to form the first semiconductor layer 140 shown in Fig. 1B of Hersam, because (1) Hersam does not limit the semiconductor material used to make the SASC transistor, such as the transistor shown in Fig. 1B, (2) Hersam suggests using SWCNTs as a semiconductor material in related vdWH devices, and (3) Lei teaches the ultra-high purity, solution-processed SWCNTs can be used as the active semiconductor layer in a TFT. As such, the use of SWCNTs would be the substitution of one known semiconductor channel material for another known semiconductor channel material with the expected result of functioning as the channel of a TFT.
The properties recited in feature [8] of claim 1, amount to a statement of intended use of the claimed transistor that fail to require a structural feature and consequently fail to have patentable weight. “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). (See MPEP 2114(II).)
Aside from the claimed thickness for the first and second dielectric layers of “less than 20 nm”—which is not supported in the Instant Application as explained in the rejection under 35 USC 112(a) (supra)—because the transistor of Hersam/Lei, includes all of the claimed structural features recited in claim 1, for which there is support in the Instant Application, it is held, absent evidence to the contrary that said transistor of Hersam/Lei is capable of resulting in the claimed properties when used, which is all that is required. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
Finally with regard to claim 3, although Lei teaches the claimed solution processing of the SWCNTs that results in a purity of 99.997%, “solution processing” is a process limitation that fails to have patentable weight for failing to explicitly or implicitly require a structure. Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that Applicant has the burden of proof in such cases, as the above case law make clear.
This is all of the limitations of claims 1, 3, and 6.
With regard to claims 2, 8-11 and 13, Hersam further discloses,
2. (Original) The OCGT of claim 1, wherein the substrate comprises an undoped Si wafer [“SASC MoS2 FETs were fabricated on local gates (Au) 110 on undoped Si wafers with about 300 nm thick thermal oxide 120” (p. 27, line 25); also p. 22, lines 16 and 19-21].
8. (Original) The OCGT of claim 1, wherein the bottom gate electrode 110, the bottom contact 150 and the top contact 180 are formed of the same conductive material [e.g. Au, as shown in Fig. 1B] or different conductive materials [p. 22, lines 17-21; p. 23, lines 14-20].
9. (Previously presented) The OCGT of claim 8, wherein each of the bottom gate electrode 110, the bottom contact 150 and the top contact 180 is formed of palladium (Pd), gold (Au), aluminum (Al),titanium (Ti), nickel (Ni), chromium (Cr), transparent indium tin oxides, or a combination thereof [p. 22, lines 17-21; p. 23, lines 14-20].
10. (Original) The OCGT of claim 1, wherein the first dielectric layer 130 and the second dielectric layer 170 comprise a same dielectric material [e.g. Al2O3, as shown in Fig. 1B] or different dielectric materials [Fig. 1B; p. 22, lines 16-17; p. 22, line 30 to p. 23, line 4; p. 27, lines 27-28].
11. (Previously presented) The OCGT of claim 10, wherein each of the first dielectric layer and the second dielectric layer is formed of HfO2, Al2O3, ZrO2, ZnO, SiO2, or dielectrics including alumina, hafnia, or zirconia [Fig. 1B; p. 22, lines 16-17; p. 22, line 30 to p. 23, line 4; p. 27, lines 27-28].
13. (Previously presented) The OCGT of claim 1, wherein an overlap region of the dielectric extension 170 with the top contact 180
[1] determines the channel length [as shown in Figs. 1A-1B; “the dielectric extension defining a channel length of a channel in the first semiconductor layer” (abstract)] and
[2] creates a secondary gate that is shorted to the top contact 180 [as shown in Fig. 1B; i.e. the portion of 180 overlapping the dielectric extension 170 is the claimed “secondary gate” and the portion of 180 contacting the semiconductor layer 140 is the “top contact”; therefore, they are electrically shorted].
Claim 18 reads,
18. (Previously presented) The OCGT of claim 1, wherein the OCGT has a width-normalized output conductance of about 60 nS∙μm-1 while maintaining width-normalized output current levels of about 30 μA∙μm-1.
Claim18 merely recites statements of intended use of the OCGT of claim 1 and/or characteristics demonstrated upon use of the OCGT of claim 1, which fail to have patentable weight for failing to require any structure other than that required in claim 1. In this regard, it has been held that “apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) (See MPEP 2114(II).)
Because the OCGT disclosed in Hersam includes all of the structural limitations recited in claim 1, it is held, absent evidence to the contrary, that the OCGT disclosed in Hersam is capable of being used as recited in claim 18 and will inherently demonstrate the same characteristic upon used as recited in claim 18. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V) and MPEP 2114(I).)
With regard to claim 22 and 23, Hersam further discloses,
22. (Previously presented) A circuit, comprising at least one ohmic-contact-gated transistor (OCGT) according to claim 1 [“the invention relates to a circuitry having one or more SASC electronic devices according to the above disclosure.” (p. 5, lines 18-19); p. 48, claim 21].
23. (Previously presented) A device, comprising at least one ohmic-contact-gated transistor (OCGT) according to claim 1 [at least pp. 46-48 claims 1-20].
With regard to claims 24, 26, and 29, Hersam modified according to Lei, as explained above, teaches,
24. (Currently amended) A method for fabricating an ohmic-contact-gated transistor (OCGT), comprising:
[1] forming a bottom gate electrode 110 on a substrate [“SASC MoS2 FETs were fabricated on local gates (Au) 110 on undoped Si wafers with about 300 nm thick thermal oxide 120” (p. 27, line 25); also p. 22, lines 16 and 19-21];
[2] forming a first dielectric layer 130 on the bottom gate electrode 110 [“The gate dielectric 130 and the dielectric extension 170 are both about 30 nm thick ALD-grown Al2O3.” (p. 27, lines 27-28)];
[3] forming a thin film 140 of a semiconducting material on the first dielectric layer 130 [p. 22, lines 5-16];
[4] forming a bottom contact 150 on and in ohmic contact with a part of the thin film 140 [Fig. 1B; 150 is Au; p. 23, lines 14-20];
[5] conformally growing a second dielectric layer 170 on the bottom contact 150 to result in a self-aligned dielectric extension 170 from the bottom contact 150 on the thin film 140 [“The gate dielectric 130 and the dielectric extension 170 are both about 30 nm thick ALD-grown Al2O3.” (p. 27, lines 27-28)]; and
[6] forming a top contact 180 on the second dielectric layer 170[,] on the top of the bottom contact 150[,] and fully overlapping with the dielectric extension 170 to define a device channel having a channel length in the thin film 140 under the dielectric extension 170 between the bottom contact 150 and the top contact 180 [as shown in Figs. 1A and 1B; p. 23, lines 14-20; paragraph bridging pp. 27-28)],
[7] wherein the semiconducting material consists essentially of ultrahigh purity semiconducting single-walled carbon nanotubes (SWCNTs) having a semiconducting purity of at least 99.9%, and each of the first and second dielectric layers is an ultrathin high-k dielectric layer having a thickness of less than 20 nm, k being a dielectric constant [as taught by Lei, as explained under claim 1 (supra)],
[8] whereby the OCGT provides unipolar p-type transport with an Ion/Ioff ratio of greater than 104, an output current of about 10 μA∙μm-1, and a leakage current of about 10 μA∙μm-1 in the channel [as taught by Lei, as explained under claim 1 (supra)],
[9] wherein the channel has the channel length of less than about 300 nm [Hersam: abstract].
26. (Original) The method of claim 24, wherein the semiconducting material comprises a solution-processed semiconducting material [as taught by Lei, as explained under claim 1 (supra)].
29. (Original) The method of claim 27, wherein the thin film comprises an SWCNT random network with a linear density of about 40 CNTs∙μm-1 [as taught by Lei, as explained under claim 1 (supra)].
With regard to claim 31, Hersam further discloses,
31. (Previously presented) The method of claim 24, wherein said forming the first dielectric layer 130 is grown via atomic layer deposition (ALD) of a dielectric oxide.
Hersam blanket deposits the gate dielectric layer 130, i.e. the claimed “first dielectric layer” over the entire substrate using ALD. As sated above, “The gate dielectric 130 and the dielectric extension 170 are both about 30 nm thick ALD-grown Al2O3.” (p. 27, lines 27-28)
With regard to claim 32, Hersam discloses,
32. (Previously presented) The method of claim 24, wherein said growing the second dielectric layer 170 is performed with an undercut profile of negative photoresist combined with conformal atomic layer deposition (ALD) of a dielectric oxide [e.g. Al2O3] resulting in the self-aligned dielectric extension.
Hersam discloses that the directional evaporation is used to deposit the bottom contact 150 through the opening in the photoresist and then the second dielectric 170 is deposited using ALD with the undercut being forming by the bilayer resist in Fig. 1. However, a single layer, negative resist may also be used (infra). In this regard, Hersam states,
In certain embodiments, the underlying building block of the self-aligned method is a dielectric extension protruding from metal electrodes, which is formed by exploiting resist undercuts that are ubiquitous in lithographic processes. Both electron-beam lithography and photolithography resist undercuts have been optimized to obtain dielectric extensions in the range of about 100 nm to about 800 nm, as shown in FIGS. 5A-5C and 6. For example, as shown in FIG. 1A, a bilayer of two poly( methyl methacrylate) electron-beam lithography resists, in which the lower molecular weight resist (resist 1, higher sensitivity to electron dose) is under the higher molecular weight resist (resist 2, lower sensitivity), results in an undercut down to about 135 nm. The metal electrodes (metal 1) are obtained by directional evaporation (i.e., edges defined by resist 2), and the dielectric extension is obtained by conformal growth of a dielectric (i.e., edges defined by resist 1) by atomic layer deposition (ALD), followed by liftoff processes.
(p. 27, lines 10-23; emphasis added)
The gate dielectric 130 and the dielectric extension 170 are both about 30 nm thick ALD-grown Al2O3.
(p. 27, lines 27-28; emphasis added)
With regard to the resist undercut shown in Figs. 5A-5C, Hersam states,
FIGS. 5A-5C show atomic force microscopy analysis of the dielectric extension according to embodiments of the invention. Specifically, FIG. 5A shows a schematic process-flow for dielectric extension formation using single resist photolithography, where the natural undercut in the photoresist is used in conjunction with isotropic metal evaporation and conformal ALD growth to realize the dielectric extension. …
(p. 12, lines 2-6; emphasis added)
Large-area SASC MoS2 transistors were fabricated using a photolithography-based process exploiting the inherent undercut in single-layer photoresists on a continuous CVD MoS2 film, as shown in FIGS. 5A-5C and 20A-20C. (1) The MoS2 film was patterned into rectangles using a Microposit S 1813 (Shipley Company) positive resist and reactive ion etching using Ar (power = 50 W, pressure = 100 mTorr, and flow rate = 50 seem, time = 20 sec). (2) The negative photoresist NR9-1000 PY (Futurrex, Inc.) is spin-coated from about 3000 to about 6000 rpm for about 40 sec and pre-baked at about l50°C. (3) A SUSS MABA6 Mask Aligner with wavelength of about 365 nm and intensity of about 9 mW/cm is used to expose the desired areas of the resist for about 20-40 sec, followed by post-bake at about l00°C. (4) The substrate is then developed in RD6 (Futurrex, Inc.) for about 12-18 sec. (5) The (about 4 nm Ti)/( about 30 nm Au)/( about 4 nm Al) metal contacts are thermally evaporated. (6) ALD of 30 nm thick Al2O3 is carried out at about l00°C with about 30 sec intervals between pulses. (7) Finally, the top electrode is fabricated using a normal photolithography process with negative resist.
(paragraph bridging pp. 34-35; emphasis added)
With regard to claim 33, Hersam further discloses,
33. (Previously presented) The method of claim 24, wherein the top contact electrode 180 is patterned using photolithography and directional metal evaporation such that it fully overlaps the dielectric extension from the bottom contact [i.e. the dielectric extension 170].
See quoted paragraphs under claim 32, above, particularly, “The metal electrodes (metal 1) are obtained by directional evaporation (i.e., edges defined by resist 2) …” and “(7) Finally, the top electrode [e.g. 180] is fabricated using a normal photolithography process with negative resist.”
To the extent that it is unclear if photolithography and directional evaporation are used to form the top contact electrode 180 in the embodiment shown in Fig. 1B, then it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use photolithography and directional evaporation because Hersam uses these to form a top contact of the transistors, such as shown in Fig. 1B.
With regard to claims 34 and 35, Hersam further discloses,
34. (Original) The method of claim 24, wherein the bottom gate electrode, the bottom contact 150 and the top contact 180 are formed of the same conductive material or different conductive materials.
35. (Previously presented) The method of claim 34, wherein each of the bottom gate electrode, the bottom contact and the top contact is formed of palladium (Pd), gold (Au), aluminum (Al), titanium (Ti), nickel (Ni), chromium (Cr), or transparent indium tin oxide.
Fig. 1B shows gold for each of the bottom 150 and top 180 contacts. In addition, a laminate of Ti/Au/Al may be used for a bottom contact and Ti/Au for the top contact (p. 34, lines 24-28).
With regard to claims 36 and 37, Hersam further discloses,
36. (Original) The method of claim 24, wherein the first dielectric layer 130 and the second dielectric layer 170 comprise a same dielectric material or different dielectric materials.
37. (Previously presented) The method of claim 36, wherein each of the first dielectric layer 130 and the second dielectric layer 170 is formed of HfO2, Al2O3, ZrO2, ZnO, SiO2, or dielectrics including alumina, hafnia, or zirconia.
Fig. 1B, shows Al2O3 for each of the first 130 and second 170 dielectrics.
VI. Allowable Subject Matter
Claim 12 is allowed.
The following is a statement of reasons for the indication of allowable subject matter, as repeated from the Final Rejection mailed 03/02/2026: Dependent claim 12 has been rewritten in independent form including all of the features of independent claim 1, from which claim 12 previously indirectly depended. Dependent claim 12 had been previously indicated to include allowable subject matter (Non-Final Rejection mailed 10/17/2025 at p. 25).
By depending from claim 12, claim 20 may be allowable if, and only if, the rejection of claim 20 under 35 USC 112(a) can be overcome.
VII. Response to Arguments
Applicant’s arguments filed 06/02/2026 have been fully considered but they are not persuasive.
Applicant’s amendments to claims 1 and 24 overcomes the rejection under 35 USC 112(a) for lack of written description but added new matter, thereby necessitating a new rejection under 35 USC 112(a) for lack of written description.
Applicant’s amendments to claims 1 and 24 overcomes the rejection under 35 USC 102, however, the amendments do not overcome the rejection under 35 USC 103 for the reasons explained in the rejection, above.
Applicant argues that the Instant Invention “solves a specific problem not addressed by either reference [i.e. Hersam and Lei] (Remarks: paragraph bridging pp. 10-11). Examiner respectfully submits that it is well settled that the problem addressed does not negate that the combination of Hersam and Lei discloses all of the claimed structural features, and therefore renders the claims obvious—bearing in mind the rejection under 35 USC 112(a).
Applicant argues that “Hersam and Lei are directed to different problems and different technical solutions”.
In response to applicant’s arguments that Hersam and Lei are directed to different problems with different technical solutions, and that there is no teaching, suggestion, or motivation to combine the references (Remarks: p. 11), the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). As explained in the rejection, Hersam does not limit the 2-D semiconductor material used to make the OCGT, and Lei is cited for teaching another known 2-D semiconductor material known for making the semiconductor channel of a transistor. To repeat, Hersam does not limit the semiconductor material of the self-aligned short-channel transistor (SASC) that includes only the first semiconductor layer, such as the transistor shown on the left in Fig. 1A. In this regard, Hersam states,
In one embodiment, the first semiconductor layer formed of an atomically thin material comprising MoS2, MoSe2, WS2, WSe2, InSe, GaTe, black phosphorus (BP), or related two-dimensional materials.
(Hersam: p. 4, lines 15-17; emphasis added)
Hersam further teaches that SWCNTs can be used as the second semiconductor material in van der Waals heterojunctions (vdWHs) shown on the right in Fig. 1, as well as in Figs. 3A, 4B, and 13A. See Hersam at p. 5, lines 4-7; p. 7, lines 4-8; p. 23, lines 9-13; p. 25, lines 15-19; p. 48, claim 15; p. 51, claim 33.
Hersam does not, however, show in the embodiment shown in Fig. 1B that the semiconductor layer 140 is solution-processed SWCNTs.
Lei, like Hersam, teaches a thin-film transistor (TFT) including vapor deposited metal electrodes and ALD deposited Al2O3 dielectric layers. (Lei: abstract; p. 4, Fig. 1a; pp. 3-5, section entitled “Device fabrication and stability consideration”; p. 9, section entitled, “Fabrication of flexible CNT circuits on polyimide substrates”)
Lei further teaches forming the semiconductor layer of the TFT using solution-processed SWCNTs of “ultrahigh purity (99.997%) and resulting in a line density of about “35-40 CNTs/μm” (Lei: abstract: pp. 2-5; p. 4, Fig. 1a; pp. 3-5, section entitled “Device fabrication and stability consideration”; p. 9, section entitled, “Fabrication of flexible CNT circuits on polyimide substrates”). Therefore, Lei teaches each of the limitations recited in claims 3-6 and 26-29, above.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the solution-processed, ultra-high purity SWCNTs having a line density of 35-40 CNTs/μm deposited as in Lei to form the first semiconductor layer 140 shown in Fig. 1B of Hersam, because (1) Hersam does not limit the semiconductor material used to make the SASC transistor, such as the transistor shown in Fig. 1B, (2) Hersam suggests using SWCNTs as a semiconductor material in related vdWH devices, and (3) Lei teaches the ultra-high purity, solution-processed SWCNTs can be used as the active semiconductor layer in a TFT. As such, the use of SWCNTs would be the substitution of one known semiconductor channel material for another known semiconductor channel material with the expected result of functioning as the channel of a TFT.
Based on the foregoing, Applicant’s argument that Hersam and Lei are directed to solving different problems is not found persuasive.
Applicant further argues unexpected synergistic results (Remarks: p. 12). However, bearing in mind the rejection under 35 USC 112(a), there is no evidence of unexpected results for the currently claimed device, i.e. no evidence that the claimed properties of the OCGT having first and second dielectric layers with a thickness of “less than 20 nm”, specifically from 13 nm to 20 nm will even have the claimed properties since there is only evidence for a thickness of 12 nm.
Applicant further argues that “Examiner’s inherency argument is legally flawed” because
[1] The Examiner has provided no evidence, nor is there any teaching in the references, that the combination of Hersam and Lei would necessarily produce the claimed electrical performance. [2] Hersam's device with a 30 nm dielectric and MoS2 channel demonstrably does not. Lei's device in a conventional TFT structure demonstrably does not. One skill in the art would not have a reasonable expectation of achieving the claimed synergistic analog performance by simply substituting materials. Therefore, the inherency argument fails.
(Remarks: p. 12)
With regard to argument [1], first, as Applicant is well aware, there is no requirement for Examiner to provide evidence for the properties of a transistor since the USPTO does not have the fabs or labs or time to carry out such experimentations. Second, the OCGT of Hersam/Lei has all of the claimed structural features of claims 1 and 24, thereby providing evidence that said OCGT would have the same claimed properties when used. Therefore, the burden of proof was properly shifted to Applicant to prove that the prior art OCGT of Hersam/Lei does have the claimed properties when used. Third, Applicant failed to meet its burden of proof.
Based on all of the foregoing, Applicant’s arguments are not found persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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