Prosecution Insights
Last updated: April 19, 2026
Application No. 18/271,914

Display Device, Manufacturing Method Of Display Device, And Electronic Device

Non-Final OA §102§103§112
Filed
Jul 12, 2023
Examiner
LEE, ALVIN LYNGHI
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co. Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
98%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
55 granted / 63 resolved
+19.3% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
48 currently pending
Career history
111
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
26.1%
-13.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 63 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Group I in the reply filed on November 17, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 17, 2025. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation of “transmit light of the same color” in lines 8-9 can be read in two different ways. The first would mean to transmit light entering the layer, that is the light from the EL layer. An analogy would be to view this is as a stained-glass window. The stained-glass window (coloring layer) transmits the sunlight (light of a same color) through the stained-glass window. [0088] of the instant application discloses the EL layers can emit the same color. This corresponds to the limitation in lines 6-7 with the EL layers emitting the same color. Thus, the coloring layers would transmit the light entering; the light being the same color. The limitation can also be read to mean transmit light exiting the layer, that is light after the conversion process. Using the stained-glass window analogy again, this would mean the stained-glass window itself transmits the light after the color has been changed; like two adjacent green panes (coloring layer) transmits green (light of the same color). [0091] of the instant application discloses an arrangement of pixels such that in one direction pixels emit one color but in a different direction the pixels emit red, green, and blue. This would mean the pixels emit the same color, which is the case considering the pixel arrangement disclosed in [0091] of the instant application. For purposes of Examination, Examiner will read the limitation to mean the coloring layers transmit light of the same color entering the layer. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 7-8, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et. al. (KR 20200082491 A), hereinafter Park. Regarding claim 1, Park teaches display device (Fig 1 display device 100, [0023] of translation) comprising a first light-emitting element (Fig 7 first sub-pixel P1, [0037] of translation); a second light-emitting element (Fig 7 second sub-pixel P2, [0037] of translation); and a gap (Fig 7 trench T, [0040] of translation), wherein the first light-emitting element (Fig 7 first sub-pixel P1, [0037] of translation) comprises a first lower electrode (Fig 7 electrode 121, [0049] of translation), a first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation) over the first lower electrode (Fig 7 electrode 121, [0049] of translation), and an upper electrode (Fig 7 second electrode 140, [0076] of translation) over the first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation), wherein the second light-emitting element (Fig 7 second sub-pixel P2, [0037] of translation) comprises a second lower electrode (Fig 7 electrode 122, [0049] of translation), a second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation) over the second lower electrode (Fig 7 electrode 122, [0049] of translation), and the upper electrode (Fig 7 second electrode 140, [0076] of translation) over the second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation), wherein the first light-emitting element (Fig 7 first sub-pixel P1, [0037] of translation) is adjacent to (Fig 7) the second light-emitting element (Fig 7 second sub-pixel P2, [0037] of translation), and wherein the gap (Fig 7 trench T, [0040] of translation) is provided between (Fig 7) the first lower electrode (Fig 7 electrode 121, [0049] of translation) and first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation) and the second lower electrode (Fig 7 electrode 122, [0049] of translation) and second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation). Regarding claim 2, Park teaches the upper electrode (Fig 7 second electrode 140, [0076] of translation) comprises a region overlapping (Fig 7 shows a portion of electrode 140 within dashed box A) with the gap (Fig 7 trench T, [0040] of translation). Regarding claim 3, Park teaches a first protective layer (Fig 7 bank 125, [0093] of translation) is provided between (Fig 7) the gap (Fig 7 trench T, [0040] of translation) and the upper electrode (Fig 7 second electrode 140, [0076] of translation). Regarding claim 4, Park teaches a second protective layer (Fig 7 sealing film 150, [0093] of translation) is provided over (Fig 7) the upper electrode (Fig 7 second electrode 140, [0076] of translation). Regarding claim 5, Park teaches a first coloring layer (Fig 7 color filter CF1, [0089] of translation) is provided over the second protective layer (Fig 7 sealing film 150, [0093]) to comprise a region overlapping with the first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation), wherein a second coloring layer (Fig 7 color filter CF2, [0089] of translation) is provided over the second protective layer (Fig 7 sealing film 150, [0093]) to comprise a region overlapping with the second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation), wherein the first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation) and the second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation) are configured to emit light of the same color (light-emitting layer may be formed to emit white light; thus can be formed as a common layer on all sub-pixels, [0061] of translation), and wherein the first coloring layer (Fig 7 color filter CF1, [0089] of translation) and the second coloring layer (Fig 7 color filter CF2, [0089] of translation) are configured to transmit light of the same color (the color filter transmits (puts out) the respective color, [0089] of translation; Examiner notes that since the structure is similar to that of the claims, the function would be the same MPEP 2112.01(I)). Regarding claim 7, Park teaches the first light-emitting element (Fig 7 first sub-pixel P1, [0037] of translation) and the second light-emitting element (Fig 7 second sub-pixel P2, [0037] of translation) are provided over an insulating layer (Fig 7 insulating layer 115, [0040] of translation), wherein a top surface of the insulating layer (Fig 7 insulating layer 115, [0040] of translation) comprises a region (Fig 7 Bottom of trench T) in contact with a bottom surface of the gap (Fig 7 trench T, [0040] of translation), and wherein a thickness (See annotated figure) of the insulating layer (Fig 7 insulating layer 115, [0040] of translation) in the region where the top surface of the insulating layer (Fig 7 insulating layer 115, [0040] of translation) is in contact with the bottom surface of the gap (Fig 7 trench T, [0040] of translation) is smaller than a thickness (See annotated figure) of the insulating layer (Fig 7 insulating layer 115, [0040] of translation) in a region overlapping with the first lower electrode (Fig 7 electrode 121, [0049] of translation) and a thickness (See annotated figure) of the insulating layer (Fig 7 insulating layer 115, [0040] of translation) in a region overlapping with the second lower electrode (Fig 7 electrode 122, [0049] of translation). PNG media_image1.png 818 848 media_image1.png Greyscale Regarding claim 8, Park teaches a region (width of trench T, [0127] of translation) where a distance between a side surface of the first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation) and a side surface of the second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation) is shorter than or equal to 1 µm (0.2 µm or more, [0127] of translation). Regarding claim 14, Park teaches an electronic device (Fig 11b storage case 10, [0161] of translation) comprising the display device claim 1 (Fig 1 display device 100, [0023] of translation corresponds to Fig 11 display device 11 and 12, [0161] of translation), and a lens (Fig 11 eyepiece lens 20, [0161] of translation). Claim 6 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et. al. (KR 20200082491 A), hereinafter Park, with supporting evidence from (KLA; citing Malitson, 1965, “Refractive Index of SiO2, Fused Silica, Silica, Silicon Dioxide, Thermal Oxide, ThermalOxide”, https://www.kla.com/products/instruments/refractive-index-database/SiO2/Fused-Silica-Silica-Silicon-Dioxide-Thermal-Oxide-ThermalOxide). Park teaches a third protective layer (Fig 7 insulating layer 127, [0040] of translation) is provided to comprise a region in contact (Fig 7 portion of insulating layer 127 in trench; Applicant has not specified type of contact thus Examiner interprets this limitation to mean in electrical contact) with a side surface (Fig 7 side surface of electrode 121 is facing insulating layer 127) of the first lower electrode (Fig 7 electrode 121, [0049] of translation), a side surface (Fig 7 light-emitting layer 130 for P1 is facing insulating layer 127) of the first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation), and a side surface (Fig 7 trench is facing insulating layer 127) of the gap (Fig 7 trench T, [0040] of translation), and wherein the third protective layer (Fig 7 insulating layer 127, [0040] of translation) comprises a region with a refractive index (insulating layer 127 has refractive index of 1.7 or lower, [0117] of translation) higher than a refractive index (bank 125 is made of silicon oxide, [0134] of translation; from KLA the refractive index of silicon oxide is 1.4 to 1.55) of the gap (Fig 7 trench T with bank 125; Examiner notes that the gap of the instant application contains a material (gas, [0110] of instant application); accordingly the trench of Park contains material from bank 125). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park et. al. (KR 20200082491 A), hereinafter Park. Park fails to teach a region where a distance between the side surface of the first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation) and the side surface of the second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation) is shorter than or equal to 100 nm. However, Park teaches a second stack 133 is formed on a charge generation layer 132; and that during the formation a portion of the second stack 133 is formed on a charge generation layer 132 forms inside the trench ([0104] of translation). Park also teaches the width of the trench is such that the second stacks of two sub-pixels do not touch ([0104] of translation). Further, Park teaches the desire for high resolution displays in the art ([0005] of translation). The width of the distance between second stacks is therefore a result-effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width of the distance between second stacks as Park has identified the width as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a distance between the side surface of the first EL layer (Fig 7 light-emitting layer 130 for P1, [0054] of translation) and the side surface of the second EL layer (Fig 7 light-emitting layer 130 for P2, [0054] of translation) is shorter than or equal to 100 nm, in order to achieve the desired balance between the resolution of the display and the distance between the second stack, as taught by Park. MPEP 2144.05. Furthermore, the applicant has not presented persuasive evidence that the claimed distance is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed distance). Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Park et. al. (KR 20200082491 A), hereinafter Park, in view of Nakata et. al. (US 20150034926 A1), hereinafter Nakata. Regarding claim 10, Park fails to teach the gap comprises any one or more selected from nitrogen, oxygen, carbon dioxide, and a Group 18 element. However, Park teaches a protective layer (Fig 7 bank 125, [0093] of translation) formed in the gap; the protective layer being made of silicon oxide ([0134] of translation). Nakata teaches a physical deposition method for forming a protection layer, made of oxide silicon ([0080]), using sputtering with gas molecules ([0082]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate the teachings of Nakata by forming a protective layer using sputtering with gas molecules. This would allow for depositing a film with lower energy requirements ([0082]). In modifying Park to use the teachings of Nakata, the protective layer formed in the gap would comprise any one or more selected from nitrogen, oxygen (from the protective film), carbon dioxide, and a Group 18 element (from the sputtering process). Regarding claim 11, Park as modified in claim 10 teaches the Group 18 element (Nakata: from the sputtering process, [0082]) comprises one or more selected from helium, neon, argon (Nakata: argon, [0082]), xenon, and krypton. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et. al. (KR 20200082491 A), hereinafter Park, in view of Yamazaki et. al. (WO 2018087625 A1 using US 20200057330 A1 for ease of reference), hereinafter Yamazaki. Regarding claim 12, Park teaches a first transistor (Fig 7 transistor TFT for P1, [0050]); and a second transistor (Fig 7 transistor TFT for P2, [0050]), wherein one of a source and a drain (the first electrode is connected to a source or drain terminal of the driving transistor, [0050] of translation) of the first transistor (Fig 7 transistor TFT for P1, [0050]) is electrically connected to the first lower electrode (Fig 7 electrode 121, [0049] of translation), wherein one of a source and a drain (the first electrode is connected to a source or drain terminal of the driving transistor, [0050] of translation) of the second transistor (Fig 7 transistor TFT for P2, [0050]) is electrically connected to the second lower electrode (Fig 7 transistor TFT for P2, [0050]). Park fails to teach the first transistor and the second transistor each comprise silicon in a channel formation region. However, Yamazaki teaches the semiconductor layer of transistors can be made of silicon ([0379]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate the teachings of Yamazaki by having the semiconductor layer of the transistor be made of silicon. This would increase carrier mobility in the channel ([0379]). In modifying Park with the teachings of Yamazaki, the first transistor (Park: Fig 7 transistor TFT for P1, [0050]) and the second transistor (Park: Fig 7 transistor TFT for P2, [0050]) each comprise silicon in a channel formation region (silicon semiconductor layer which contains the channel formation region, [0379]). Regarding claim 13, Park teaches a first transistor (Fig 7 transistor TFT for P1, [0050]); and a second transistor (Fig 7 transistor TFT for P2, [0050]), wherein one of a source and a drain (the first electrode is connected to a source or drain terminal of the driving transistor, [0050] of translation) of the first transistor (Fig 7 transistor TFT for P1, [0050]) is electrically connected to the first lower electrode (Fig 7 electrode 121, [0049] of translation), wherein one of a source and a drain (the first electrode is connected to a source or drain terminal of the driving transistor, [0050] of translation) of the second transistor (Fig 7 transistor TFT for P2, [0050]) is electrically connected to the second lower electrode (Fig 7 electrode 122, [0049] of translation), and wherein the first transistor (Fig 7 transistor TFT for P1, [0050]) and the second transistor (Fig 7 transistor TFT for P2, [0050]) each comprise a metal oxide in a channel formation region. Park fails to teach the first transistor and the second transistor each comprise a metal oxide in a channel formation region. However, Yamazaki teaches the semiconductor layer of transistors can be made of a metal oxide ([0343]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Park to incorporate the teachings of Yamazaki by having the semiconductor layer of the transistor be made of a metal oxide. This would improve charge storage time due to the low off-state current of metal oxide semiconductors ([0343]). In modifying Park with the teachings of Yamazaki, the first transistor (Park: Fig 7 transistor TFT for P1, [0050]) and the second transistor (Park: Fig 7 transistor TFT for P2, [0050]) each comprise a metal oxide in a channel formation region (metal oxide semiconductor layer which contains the channel formation region, [0379]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hamashita (US 20240032392 A1) teaches a protective layer that forms a cavity portion between sub-pixels. The cavity portion is used to reflect light due to differences in refractive index. Lim et. al. (US 20200185650 A1) teaches a trench between sub-pixels. The trench is not filled with a material. However, the contents of the trench are not disclosed. Lim et. al. (US 20200006694 A1) teaches insulation layers formed on the side of bottom electrodes to reduce current concentration. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALVIN L LEE/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jul 12, 2023
Application Filed
Jan 23, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
98%
With Interview (+10.7%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 63 resolved cases by this examiner. Grant probability derived from career allow rate.

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