DETAILED ACTION
This Office Action is in response to Application filed July 17, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants' election with traverse of Group II, claims 24 and 25, in the reply filed on February 5, 2026 is acknowledged. The traversal is on the grounds that “It is respectfully submitted that the subject matter of all claims is sufficiently related that a thorough search for the subject matter of any one Group of claims would encompass a search for the subject matter of the remaining claims”, and that “Thus, it is respectfully submitted that the search and examination of the entire application could be made without serious burden.” This is not found persuasive because (a) current application is a 371 application, and a search and examination burden is not a standard of a restriction requirement of a 371 application, and (b) in addition, even if arguendo current application is a US application, a search and examination burden is not a standard of a restriction requirement between two distinct inventions, while the search and examination burden may be a standard of a species restriction. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Ostermaier et al. (US 2017/0186600) in view of Saito et al. (US 7,935,983) in view of in view of Arena et al. (US 2008/0303118)
Regarding claim 24, Ostermaier et al. disclose a method for manufacturing a nitride semiconductor substrate (Fig. 10) ([0092]), the method comprising steps of: placing a member (151 in second/middle figure) ([0091]) so as to cover a single crystal silicon layer ((top portion of) 111) ([0072]) inward from an edge thereof, because (a) Applicants do not specifically claim how the (ring-shaped) member is placed, not to mention what it is made of, and (b) therefore, the deposition process of the layer 151 in the edge regions 114 can be referred to be a step of placing a (ring-shaped) member; and growing a plurality of Group III nitride layers (116) ([0092]).
Ostermaier et al. differ from the claimed invention by not comprising steps of preparing at least a supporting substrate and a single crystal silicon substrate for laminating; bonding the supporting substrate and the single crystal silicon substrate for laminating via a silicon oxide layer; thinning the single crystal silicon substrate for laminating to be processed into a single crystal silicon layer; and growing an AIN film on the single crystal silicon layer; and growing a GaN film or an AlGaN film, or both thereof on the AIN film, and by not showing that the member is a ring-shaped member.
Ostermaier et al. further disclose in paragraph [0033] that “The substrate 21 is typically substantially circular” describing Fig. 1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the member 151 shown in Fig. 10 of Ostermaier et al. can be a ring-shaped member, because (a) the substrate or single crystal silicon layer 111 shown in Fig. 10 of Ostermaier et al. can be substantially circular as is the case with the substrate 21 shown in Fig. 1 of Ostermaier et al. since circular semiconductor substrates have been one of the most commonly employed and most available substrates as a wafer manufacturing process commonly involves rotating an ingot to obtain a semiconductor crystal boule, which is then sliced into semiconductor substrates, and (b) in this case, when the substrate or single crystal silicon layer 111 shown in Fig. 10 of Ostermaier et al. is substantially circular, the member 151 would be a ring-shaped member.
Further regarding claim 24, Ostermaier et al. differ from the claimed invention by not comprising steps of preparing at least a supporting substrate and a single crystal silicon substrate for laminating; bonding the supporting substrate and the single crystal silicon substrate for laminating via a silicon oxide layer; thinning the single crystal silicon substrate for laminating to be processed into a single crystal silicon layer; and growing an AIN film on the single crystal silicon layer; and growing a GaN film or an AlGaN film, or both thereof on the AIN film.
Saito et al. disclose a method for manufacturing a nitride semiconductor substrate (composite structure of 2-5 in Fig. 1), comprising growing an AlN film (3) (col. 3, line 21) on a (single crystal) silicon layer (23) (col. 3, line 12); and growing a GaN film (4) (col. 3, line 24) or an AlGaN film (5) (col. 3, line 25), or both thereof on the AIN film, where the single crystal silicon layer 23 is a part of a silicon-on-insulator substrate (2) (col. 3, lines 9-10).
Since both Ostermaier et al. and Saito et al. teach a method for manufacturing a nitride semiconductor substrate, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Ostermaier et al. can comprise method steps disclosed by Saito et al. including using a silicon-on-insulator substrate, and growing an AlN film and GaN/AlGaN film as disclosed by Saito et al., because (a) Saito et al. state that “it is possible to alleviate electric field concentration on the edge of the gate electrode 8, and to improve the breakdown voltage of the nitride semiconductor device 1” on lines 60-63 of column 3, (b) therefore, a method employing a silicon-on-insulator substrate would allow one of ordinary skill in the art to form a field effect transistor having a higher breakdown voltage, and thus the higher-breakdown-voltage field effect transistor that can be employed as a component of a power semiconductor device, and (c) an AlN film has been commonly employed as a buffer layer for forming GaN-based semiconductor devices, a GaN film has been employed as a channel layer or a light emitting layer of GaN-based semiconductor devices, and an AlGaN film has been commonly employed as a barrier layer or an electron supply layer of GaN-based semiconductor devices.
Still further regarding claim 24, Ostermaier et al. in view of Saito et al. differ from the claimed invention by not comprising the steps of preparing at least a supporting substrate and a single crystal silicon substrate for laminating; bonding the supporting substrate and the single crystal silicon substrate for laminating via a silicon oxide layer; thinning the single crystal silicon substrate for laminating to be processed into a single crystal silicon layer.
Arena et al. disclose a method for manufacturing a nitride semiconductor structure (Fig. 2D) ([0072]) using a silicon-on-insulator substrate (Fig. 2C), comprising preparing at least a supporting substrate (10) ([0018] and [0049]) and a single crystal silicon substrate (11) ([0019] and [0049]) for laminating; bonding the supporting substrate and the single crystal silicon substrate for laminating via a silicon oxide layer (12a, 12b or composite layer of 12a and 12b) ([0050]), because (a) Applicants do not specifically claim what “a silicon oxide layer” refers to, and where the silicon oxide layer was located before the claimed bonding step, and (b) Applicants do not specifically claim that “a silicon oxide layer” is the only material layer that is disposed between the supporting substrate and the single crystal silicon substrate since the preposition “via” does not necessarily preclude another material layer or other material layers for the claimed bonding step; thinning the single crystal silicon substrate for laminating to be processed into a single crystal silicon layer (S6 in Fig. 2C) ([0060]).
Since both Ostermaier et al. and Arena et al. teach a method for manufacturing a nitride semiconductor structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the silicon-on-insulator substrate disclosed by Ostermaier et al. in view of Saito et al. can be manufactured in a manner disclosed by Arena et al., because the method disclosed by Arena et al. allows one of ordinary skill in the art to employ various materials for the silicon-on-insulator substrate, which can reduce the manufacturing cost, as well as allowing one of ordinary skill in the art to obtain a substrate with a high quality such as a lower surface roughness, a higher crystallinity, and a lower defect density.
Regarding claim 25, Ostermaier et al. in view of Saito et al. and further in view of Arena et al. differ from the claimed invention by not showing that the supporting substrate is a supporting substrate composed of polycrystalline silicon or single crystal silicon.
Arena et al. further disclose that the supporting substrate (10) is a supporting substrate composited of, for example, polycrystalline silicon carbide ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the supporting substrate can be composed of polycrystalline silicon, because (a) a polycrystalline silicon and a polycrystalline silicon carbide have been commonly and interchangeably employed as substrate materials due to their similar characteristics, (b) employing a polycrystalline silicon rather than a polycrystalline silicon carbide would lower the manufacturing cost, and (c) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Brawley et al. (US 2018/0294158)
Akiyama et al. (US 11,800,805)
Dutta et al. (US 2020/0135766)
Lee et al. (US 11,362,109)
Lin (US 11,152,364)
Kume et al. (US 9,196,731)
Comeau et al. (US 9,356,045)
Aujol et al. (US 8,557,042)
Kittler et al. (US 2012/0270378)
Briere (US 8,866,190)
Ishida et al. (US 2011/0095335)
Joblot et al. (US 7,785,991)
Blakely et al. (US 5,910,339)
Huang et al. (US 10,629,545)
Sizov et al. (US 12,331,426)
Cheng et al. (US 2017/0104012)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 March 6, 2026