DETAILED ACTION
This Office Action is in response to Amendment filed June 25, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Ostermaier et al. (US 2017/0186600) in view of Saito et al. (US 7,935,983) and further in view of Arena et al. (US 2008/0303118)
Ostermaier et al. disclose a method for manufacturing a nitride semiconductor substrate (Fig. 10) ([0092]), the method comprising steps of: placing a member (151 in second/middle figure) ([0091]) so as to cover a region of a single crystal silicon layer ((top portion of) 111) ([0072]) inward from an edge thereof, because (a) Applicants do not specifically claim how the (ring-shaped) member is placed, not to mention what it is made of, and (b) therefore, the deposition process of the layer 151 in the edge regions 114 can be referred to be a step of placing a (ring-shaped) member; and growing a plurality of Group III nitride layers (116) ([0092]).
Ostermaier et al. differ from the claimed invention by not comprising steps of preparing at least a composite substrate in which a plurality of layers are bonded and a single crystal silicon substrate; bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer; thinning the single crystal silicon substrate to be processed into a single crystal silicon layer; growing an AIN film on the single crystal silicon layer; and growing a GaN film or an AlGaN film, or both thereof on the AIN film, and by not showing that the member is a ring-shaped member and covers a region of 0.3 mm or longer and shorter than 3 mm from the single crystal silicon layer inward from an edge thereof.
Ostermaier et al. further disclose in paragraph [0033] that “The substrate 21 is typically substantially circular” describing Fig. 1, and in paragraph [0034] that “The edge region 30 and the peripheral region 26 of the upper surface 22 of the wafer 21 has a width d which may lie in the range of 1 mm to 1 cm.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the member 151 shown in Fig. 10 of Ostermaier et al. can be a ring-shaped member that covers a region of 0.3 mm or longer and shorter than 3 mm from the single crystal silicon layer inward from an edge thereof, because (a) the substrate or single crystal silicon layer 111 shown in Fig. 10 of Ostermaier et al. can be substantially circular as is the case with the substrate 21 shown in Fig. 1 of Ostermaier et al. since circular semiconductor substrates have been one of the most commonly employed and most available substrates as a wafer manufacturing process commonly involves rotating an ingot to obtain a semiconductor crystal boule, which is then sliced into semiconductor substrates, (b) in this case, when the substrate or single crystal silicon layer 111 shown in Fig. 10 of Ostermaier et al. is substantially circular, the member 151 would be a ring-shaped member, (c) the size or width of the region covered by the ring-shaped member should be controlled and optimized depending on (i) the lateral sizes of the composite substrate and the nitride semiconductor substrate, and (ii) the lateral size of the semiconductor device formed on the single crystal silicon layer, (d) the size or width of the region covered by the ring-shaped member disclosed by Ostermaier et al., i.e. 1 mm to 1 cm, overlaps with the claimed range of 0.3 mm to 3 mm, and (e) the claim is prima facie obvious without showing that the claimed range of the size of the region achieves unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Further regarding claim 24, Ostermaier et al. differ from the claimed invention by not comprising steps of preparing at least a composite substrate in which a plurality of layers is bonded and a single crystal silicon substrate; bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer; thinning the single crystal silicon substrate to be processed into a single crystal silicon layer; growing an AIN film on the single crystal silicon layer; and growing a GaN film or an AlGaN film, or both thereof on the AIN film.
Saito et al. disclose a method for manufacturing a nitride semiconductor substrate (composite structure of 2-5 in Fig. 1), comprising growing an AlN film (3) (col. 3, line 21) on a (single crystal) silicon layer (23) (col. 3, line 12); and growing a GaN film (4) (col. 3, line 24) or an AlGaN film (5) (col. 3, line 25), or both thereof on the AIN film, where the single crystal silicon layer 23 is a part of a silicon-on-insulator substrate (2) (col. 3, lines 9-10).
Since both Ostermaier et al. and Saito et al. teach a method for manufacturing a nitride semiconductor substrate, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Ostermaier et al. can comprise method steps disclosed by Saito et al. including using a silicon-on-insulator substrate, and growing an AlN film and GaN/AlGaN film as disclosed by Saito et al., because (a) Saito et al. state that “it is possible to alleviate electric field concentration on the edge of the gate electrode 8, and to improve the breakdown voltage of the nitride semiconductor device 1” on lines 60-63 of column 3, (b) therefore, a method employing a silicon-on-insulator substrate would allow one of ordinary skill in the art to form a field effect transistor having a higher breakdown voltage, and thus the higher-breakdown-voltage field effect transistor that can be employed as a component of a power semiconductor device, and (c) an AlN film has been commonly employed as a buffer layer for forming GaN-based semiconductor devices, a GaN film has been employed as a channel layer or a light emitting layer of GaN-based semiconductor devices, and an AlGaN film has been commonly employed as a barrier layer or an electron supply layer of GaN-based semiconductor devices.
Still further regarding claim 24, Ostermaier et al. in view of Saito et al. differ from the claimed invention by not comprising the steps of preparing at least a composite substrate in which a plurality of layers is bonded and a single crystal silicon substrate; bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer; thinning the single crystal silicon substrate for laminating to be processed into a single crystal silicon layer.
Arena et al. disclose a method for manufacturing a nitride semiconductor structure (Fig. 2D) ([0072]) using a silicon-on-insulator substrate (Fig. 2C), comprising preparing at least a composite substrate (10 in Fig. 2A) ([0018] and [0049]), because (a) Areana et al. disclose that “The support substrate may in particular be a material chosen from at least one of the following materials: polycrystalline AlN, single-crystal or polycrystalline GaN, single-crystal or polycrystalline SiC, sapphire, a ceramic, such as an aluminum oxide or alumina, or else a metal alloy such as an Mo, Cr and Ni alloy of the Hastelloy type, … (emphasis added)” in paragraph [0018], and (b) therefore, Arena et al. disclose a composite substrate where more than one of the materials of polycrystalline AlN, single-crystal GaN, polycrystalline GaN, single-crystal SiC, polycrystalline SiC, sapphire, a ceramic such as an aluminum oxide or alumina, and a metal alloy such as an Mo, Cr and Ni alloy of the Hastelloy type are bonded since Applicants do not specifically claim how the plurality of layers are bonded to each other in claim 24, and a single crystal silicon substrate (11) ([0019] and [0049]); bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer (12a, 12b or composite layer of 12a and 12b) ([0050]), because (a) Applicants do not specifically claim what “a silicon oxide layer” refers to, and where the silicon oxide layer was located before the claimed bonding step, and (b) Applicants do not specifically claim that “a silicon oxide layer” is the only material layer that is disposed between the supporting substrate and the single crystal silicon substrate since the preposition “via” does not necessarily preclude another material layer or other material layers for the claimed bonding step; thinning the single crystal silicon substrate to be processed into a single crystal silicon layer (S6 in Fig. 2C) ([0060]).
Since both Ostermaier et al. and Arena et al. teach a method for manufacturing a nitride semiconductor structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the silicon-on-insulator substrate disclosed by Ostermaier et al. in view of Saito et al. can be manufactured in a manner disclosed by Arena et al., because the method disclosed by Arena et al. allows one of ordinary skill in the art to employ various materials for the silicon-on-insulator substrate, which can reduce the manufacturing cost as well as allowing one of ordinary skill in the art to obtain a substrate with a high quality such as a lower surface roughness, a higher crystallinity, and a lower defect density.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Ostermaier et al. (US 2017/0186600) in view of Saito et al. (US 7,935,983) and further in view of Arena et al. (US 2008/0303118) as applied to claim 24, and still further in view of Odnoblyudov et al. (US 2019/0198311) The teachings of Ostermaier et al. in view of Saito et al. and further in view of Arena et al. are discussed above.
Ostermaier et al. in view of Saito et al. and further in view of Arena et al. differ from the claimed invention by not showing that the composite substrate in which the plurality of the layers are bonded is a composite substrate comprising: a polycrystalline ceramic core; a first adhesive layer bonded to the polycrystalline ceramic core; a conductive layer bonded to the first adhesive layer as necessary; a second adhesive layer bonded to the conductive layer; and a barrier layer bonded to the second adhesive layer.
Odnoblyudov et al. disclose a method for manufacturing a nitride semiconductor substrate (Fig. 1) ([0021]), the method comprising the step of preparing a composite substrate (bottom portion of engineered substrate 100 disposed below silicon oxide bonding layer 120) ([0036]) in which a plurality of layers (110-118) are bonded, wherein the composite substrate in which the plurality of the layers are bonded is a composite substrate having: a polycrystalline ceramic core (110) ([0021]); a first adhesive layer (112) ([0022]) bonded to the polycrystalline ceramic core; a conductive layer (114) ([0024]) bonded to the first adhesive layer as necessary; a second adhesive layer (116) ([0027]) bonded to the conductive layer; and a barrier layer (118) ([0028]) bonded to the second adhesive layer.
Since both Ostermaier et al./Arena et al. and Odnoblyudov et al. teach a method for manufacturing a nitride semiconductor substrate, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the composite substrate disclosed by Ostermaier et al. in view of Saito et al. and further in view of Arena et al. can have the claimed configuration as disclosed by Odnoblyudov et al., because (a) (at least some of) the materials constituting the composite substrate disclosed by Odnoblyudov et al. are disclosed in paragraph [0018] of Arena et al. as discussed above with regard to claim 24, (b) the composite substrate disclosed by Odnoblyudov et al. incorporated into the composite substrate disclosed by Ostermaier et al./Arena et al. would allow one of ordinary skill in the art to control and optimize the difference between the coefficient of thermal expansion of the composite substrate and the coefficient of thermal expansion of the semiconductor layers formed on the composite substrate ([0004] of Odnoblyudov et al.), which would allow one of ordinary skill in the art to improve quality of the semiconductor layers since one of ordinary skill in the art would be able to better control the epitaxial growth process and the subsequent cooling process.
Response to Arguments
Applicants’ arguments with respect to claim 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The Examiner would like to point out two things: (a) Ostermaier et al. already disclosed the claimed size of the covered edge recited in the amended claim 24 as discussed above under 35 USC 103 rejection. (b) Applicants’ arguments in the REMARKS filed June 25, 2026 are not persuasive, because (i) it appears that Applicants argue as if the claimed size is an only critical parameter in itself in view of Fig. 4 of current application, (ii) however, Applicants did not originally disclose the newly claimed size of the covered edge is a critical parameter in the original disclosure, (iii) also, the nitride semiconductor substrate formed by the claimed method can be cut into multiple substrates, and therefore, even if arguendo there is an unexpected result from selecting the size of the covered edge in the claimed range, the benefit would disappear once the claimed nitride semiconductor substrate is cut into multiple substrates, and one of ordinary skill in the art uses only substrates close to the center of the original nitride semiconductor substrate. (c) Also, effects shown in Fig. 4 of current application and the claimed range of the size of the covered edge would also strongly depend on other parameters such as (i) a surface orientation of the single crystal silicon layer, (ii) a surface roughness of the single crystal silicon layer, (iii) a defect density and a type of defects in the single crystal silicon layer, (iv) whether a native oxide remains on the single crystal silicon layer, (v) whether a thermal treatment is performed or other processes such as a plasma treatment are performed before the AlN film is formed, (vi) epitaxial conditions of the AlN film, the GaN and AlGaN film, which would determine the quality of the AlN, GaN and AlGaN film more determinatively than the claimed size of the covered edge, (vii) a material composition of the ring-shaped member, which will also determine creation of defects near the ring-shaped member, etc. (d) Therefore, Applicants cannot persuasively allege that the newly claimed size of the covered edge is the only critical parameter when all the other parameters and conditions that are more critical to the quality of the AlN, GaN and AlGaN film are not claimed in the amended claim 24.
Conclusion
Applicants' amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 July 24, 2026
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