DETAILED ACTION
This Office Action is in response to Application filed July 17, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants' election with traverse of Group II, claims 24 and 25, in the reply filed on March 3, 2026 is acknowledged. The traversal is on the grounds that “The Office Action relies on Dagher to allegedly show a posteriori lack of unity of invention”, that “However, Applicant respectfully submits that the Office Action has not demonstrated that Dagher discloses each and every limitation, in combination, of the nitride semiconductor substrate”, that “Accordingly, a posteriori lack of unity of invention has not been established”, that “Therefore, Applicant respectfully submits that lack of unity of invention has not been established, and thus a restriction requirement based on a lack of unity of invention is entirely improper.” This is not found persuasive, because Fig. 2(c) of Dagher et al. discloses the claimed invention recited in claim 10 as stated in the Restriction Requirement mailed January 14, 2026 as follows: Dagher et al. disclose a nitride semiconductor substrate (Fig. 2(c)), comprising a Ga-containing nitride semiconductor thin film (coalesced GaN film in Fig. 2(c)) formed on a substrate (substrate including Si, SiO2 and Si, which constitutes SOI, i.e. silicon on insulator, nano-pillars mentioned in the Title) for film-forming in which a single crystal silicon layer (silicon layer of SOI nano-pillars) is formed on a composite substrate (composite substrate of Si and SiO2 in Fig. 2) in which a plurality of layers (Si and SiO2) is bonded, wherein the nitride semiconductor substrate has a region where the Ga-containing nitride semiconductor thin film (coalesced GaN in Fig. 2(c)) is not formed inward from an edge of the single crystal silicon layer being a growth surface of the nitride semiconductor thin film, because (a) the uppermost inverse trapezoidal shape in Fig. 2(c) corresponds to a region where the nitride semiconductor thin film formed of GaN is not formed, (b) Applicants do not specifically claim the lateral and vertical sizes, and the shape of the nitride semiconductor thin film, (c) the coalesced GaN shown in Fig. 2(c) of Dagher et al. is not formed inward from an edge of the single crystal silicon layer in the center region since (i) Merriam-Webster dictionary defines the adjective “inward” as “situated on the inside : inner”, and thus the coalesced GaN shown in Fig. 2(c) is not formed entirely inward or is not formed on some inward portions from an edge of the single crystal silicon layer just like Applicants’ original disclosure, (c) Applicants do not specifically claim where the nitride semiconductor substrate and the Ga-containing nitride semiconductor thin film are employed, and (d) additionally, as discussed below in the prior art rejection, Ostermaier et al. in view of Saito et al. and further in view of Arena et al. disclose all the limitations of the independent claim 24. The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim 24 is objected to because of the following informalities: on line 3, “a plurality of layers is” should be replaced with “a plurality of layers are” to be grammatically correct. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 25, it is not clear what the limitation “bonded to an entirety of” recited on lines 4-7 suggests, because (a) for example, the first adhesive layer 2 cannot be bonded to an entirety of the polycrystalline ceramic core 1 in Fig. 3 of current application since, while arguendo the first adhesive layer 2 may be bonded to an entire outermost surface of the polycrystalline ceramic core 1, the first adhesive layer cannot be bonded to an entirety of the polycrystalline ceramic core since “an entirety of the polycrystalline ceramic core” also includes an inner portion of the polycrystalline ceramic core such as a center portion of the polycrystalline ceramic core, and (b) likewise, one of the claimed other component layers cannot be bonded to “an entirety of” another of the claimed other component layers.
(2) Also regarding claim 25, even if arguendo Applicants had meant to claim that the first adhesive layer is bonded to an entire outermost surface of the polycrystalline ceramic core, etc., it is not clear how the first adhesive layer can be bonded to the entire outermost surface of the polycrystalline ceramic core, etc., because (a) for the claimed bonding processes, each of the inner elements should be held or supported by something or some mechanism, (b) in other words, during the bonding processes, (i) the polycrystalline ceramic core, (ii) the composite structure of the polycrystalline ceramic core and the first adhesive layer, (iii) the composite structure of the polycrystalline ceramic core, the first adhesive layer and the conductive layer, and (iv) the composite structure of the polycrystalline ceramic core, the first adhesive layer, the conductive layer and the second adhesive layer cannot float freely to expose entire outermost surfaces for the claimed bonding processes, (c) when (i) the polycrystalline ceramic core, (ii) the composite structure of the polycrystalline ceramic core and the first adhesive layer, (iii) the composite structure of the polycrystalline ceramic core, the first adhesive layer and the conductive layer, and (iv) the composite structure of the polycrystalline ceramic core, the first adhesive layer, the conductive layer and the second adhesive layer are held or supported by something or some mechanism, the areas of (i) the polycrystalline ceramic core, (ii) the composite structure of the polycrystalline ceramic core and the first adhesive layer, (iii) the composite structure of the polycrystalline ceramic core, the first adhesive layer and the conductive layer, and (iv) the composite structure of the polycrystalline ceramic core, the first adhesive layer, the conductive layer and the second adhesive layer held by something or some mechanism would not be bonded to the subsequently bonded layer or element, and (d) therefore, it is not clear whether the phrase “an entirety of” recited on lines 4-7 really implies “an entirety of”, or the phrase “an entirety of” actually implies a portion of.
(3) Further regarding claim 25, even if arguendo Applicants had meant to claim that the first adhesive layer is bonded to an entire outermost surface of the polycrystalline ceramic core, etc., it is not clear how the first adhesive layer can be bonded to the entire outermost surface of the polycrystalline ceramic core, etc., because (a) it is not clear how one can define the bonding to the entire outermost surface of an underlying structure since (i) the atoms constituting the subsequently bonded layer or element would have different sizes than the atoms constituting the underlying, intermediate structures, and (ii) the crystallinity and bonding mechanism of the subsequently bonded layer or element would be different than the crystallinity and bonding mechanism of the underlying, intermediate structures, (b) for example, unless the first adhesive layer has a crystalline structure and a crystal size exactly identical to the polycrystalline ceramic core, some portions of the outermost surface of the polycrystalline ceramic core would not be atomically bonded to the atoms constituting the first adhesive layer, (c) likewise, unless the claimed component layers have exactly identical structures including defects to the underlying, intermediate structures, the claimed component layers cannot be bonded to an entire outermost surface of the underlying, intermediate structures, and (d) therefore, the limitations recited on lines 4-7 appear to be noncompliant with the Enablement requirement.
(4) Still further regarding claim 25, it is not clear what the phrase “as necessary” recited on line 5 suggests, because (a) it is not clear how “a conductive layer” recited on line 4 is deemed necessary, and who determines whether “a conductive layer” is necessary, and (b) it is not clear a conductive layer that is bonded to the underlying first adhesive layer would meet the claim limitation when an actual function of “a conductive layer” was not considered during the manufacturing process, and thus it was not determined whether or not the conductive layer is necessary.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Ostermaier et al. (US 2017/0186600) in view of Saito et al. (US 7,935,983) and further in view of Arena et al. (US 2008/0303118)
Ostermaier et al. disclose a method for manufacturing a nitride semiconductor substrate (Fig. 10) ([0092]), the method comprising steps of: placing a member (151 in second/middle figure) ([0091]) so as to cover a single crystal silicon layer ((top portion of) 111) ([0072]) inward from an edge thereof, because (a) Applicants do not specifically claim how the (ring-shaped) member is placed, not to mention what it is made of, and (b) therefore, the deposition process of the layer 151 in the edge regions 114 can be referred to be a step of placing a (ring-shaped) member; and growing a plurality of Group III nitride layers (116) ([0092]).
Ostermaier et al. differ from the claimed invention by not comprising steps of preparing at least a composite substrate in which a plurality of layers is bonded and a single crystal silicon substrate; bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer; thinning the single crystal silicon substrate to be processed into a single crystal silicon layer; growing an AIN film on the single crystal silicon layer; and growing a GaN film or an AlGaN film, or both thereof on the AIN film, and by not showing that the member is a ring-shaped member.
Ostermaier et al. further disclose in paragraph [0033] that “The substrate 21 is typically substantially circular” describing Fig. 1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the member 151 shown in Fig. 10 of Ostermaier et al. can be a ring-shaped member, because (a) the substrate or single crystal silicon layer 111 shown in Fig. 10 of Ostermaier et al. can be substantially circular as is the case with the substrate 21 shown in Fig. 1 of Ostermaier et al. since circular semiconductor substrates have been one of the most commonly employed and most available substrates as a wafer manufacturing process commonly involves rotating an ingot to obtain a semiconductor crystal boule, which is then sliced into semiconductor substrates, and (b) in this case, when the substrate or single crystal silicon layer 111 shown in Fig. 10 of Ostermaier et al. is substantially circular, the member 151 would be a ring-shaped member.
Further regarding claim 24, Ostermaier et al. differ from the claimed invention by not comprising steps of preparing at least a composite substrate in which a plurality of layers is bonded and a single crystal silicon substrate; bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer; thinning the single crystal silicon substrate to be processed into a single crystal silicon layer; growing an AIN film on the single crystal silicon layer; and growing a GaN film or an AlGaN film, or both thereof on the AIN film.
Saito et al. disclose a method for manufacturing a nitride semiconductor substrate (composite structure of 2-5 in Fig. 1), comprising growing an AlN film (3) (col. 3, line 21) on a (single crystal) silicon layer (23) (col. 3, line 12); and growing a GaN film (4) (col. 3, line 24) or an AlGaN film (5) (col. 3, line 25), or both thereof on the AIN film, where the single crystal silicon layer 23 is a part of a silicon-on-insulator substrate (2) (col. 3, lines 9-10).
Since both Ostermaier et al. and Saito et al. teach a method for manufacturing a nitride semiconductor substrate, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Ostermaier et al. can comprise method steps disclosed by Saito et al. including using a silicon-on-insulator substrate, and growing an AlN film and GaN/AlGaN film as disclosed by Saito et al., because (a) Saito et al. state that “it is possible to alleviate electric field concentration on the edge of the gate electrode 8, and to improve the breakdown voltage of the nitride semiconductor device 1” on lines 60-63 of column 3, (b) therefore, a method employing a silicon-on-insulator substrate would allow one of ordinary skill in the art to form a field effect transistor having a higher breakdown voltage, and thus the higher-breakdown-voltage field effect transistor that can be employed as a component of a power semiconductor device, and (c) an AlN film has been commonly employed as a buffer layer for forming GaN-based semiconductor devices, a GaN film has been employed as a channel layer or a light emitting layer of GaN-based semiconductor devices, and an AlGaN film has been commonly employed as a barrier layer or an electron supply layer of GaN-based semiconductor devices.
Still further regarding claim 24, Ostermaier et al. in view of Saito et al. differ from the claimed invention by not comprising the steps of preparing at least a composite substrate in which a plurality of layers is bonded and a single crystal silicon substrate; bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer; thinning the single crystal silicon substrate for laminating to be processed into a single crystal silicon layer.
Arena et al. disclose a method for manufacturing a nitride semiconductor structure (Fig. 2D) ([0072]) using a silicon-on-insulator substrate (Fig. 2C), comprising preparing at least a composite substrate (10 in Fig. 2A) ([0018] and [0049]), because (a) Areana et al. disclose that “The support substrate may in particular be a material chosen from at least one of the following materials: polycrystalline AlN, single-crystal or polycrystalline GaN, single-crystal or polycrystalline SiC, sapphire, a ceramic, such as an aluminum oxide or alumina, or else a metal alloy such as an Mo, Cr and Ni alloy of the Hastelloy type, … (emphasis added)” in paragraph [0018], and (b) therefore, Arena et al. disclose a composite substrate where more than one of the materials of polycrystalline AlN, single-crystal GaN, polycrystalline GaN, single-crystal SiC, polycrystalline SiC, sapphire, a ceramic such as an aluminum oxide or alumina, and a metal alloy such as an Mo, Cr and Ni alloy of the Hastelloy type are bonded since Applicants do not specifically claim how the plurality of layers are bonded to each other in claim 24, and a single crystal silicon substrate (11) ([0019] and [0049]); bonding the composite substrate and the single crystal silicon substrate via a silicon oxide layer (12a, 12b or composite layer of 12a and 12b) ([0050]), because (a) Applicants do not specifically claim what “a silicon oxide layer” refers to, and where the silicon oxide layer was located before the claimed bonding step, and (b) Applicants do not specifically claim that “a silicon oxide layer” is the only material layer that is disposed between the supporting substrate and the single crystal silicon substrate since the preposition “via” does not necessarily preclude another material layer or other material layers for the claimed bonding step; thinning the single crystal silicon substrate to be processed into a single crystal silicon layer (S6 in Fig. 2C) ([0060]).
Since both Ostermaier et al. and Arena et al. teach a method for manufacturing a nitride semiconductor structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the silicon-on-insulator substrate disclosed by Ostermaier et al. in view of Saito et al. can be manufactured in a manner disclosed by Arena et al., because the method disclosed by Arena et al. allows one of ordinary skill in the art to employ various materials for the silicon-on-insulator substrate, which can reduce the manufacturing cost as well as allowing one of ordinary skill in the art to obtain a substrate with a high quality such as a lower surface roughness, a higher crystallinity, and a lower defect density.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Ostermaier et al. (US 2017/0186600) in view of Saito et al. (US 7,935,983) and further in view of Arena et al. (US 2008/0303118) as applied to claim 24, and still further in view of Odnoblyudov et al. (US 2019/0198311) The teachings of Ostermaier et al. in view of Saito et al. and further in view of Arena et al. are discussed above.
Ostermaier et al. in view of Saito et al. and further in view of Arena et al. differ from the claimed invention by not showing that the composite substrate in which the plurality of the layers are bonded is a composite substrate having: a polycrystalline ceramic core; a first adhesive layer bonded to an entirety of the polycrystalline ceramic core; a conductive layer bonded to an entirety of the first adhesive layer as necessary; a second adhesive layer bonded to an entirety of the conductive layer or to the entirety of the first adhesive layer; and a barrier layer bonded to an entirety of the second adhesive layer.
Odnoblyudov et al. disclose a method for manufacturing a nitride semiconductor substrate (Fig. 1) ([0021]), the method comprising the step of preparing a composite substrate (bottom portion of engineered substrate 100 disposed below silicon oxide bonding layer 120) ([0036]) in which a plurality of layers (110-118) are bonded, wherein the composite substrate in which the plurality of the layers are bonded is a composite substrate having: a polycrystalline ceramic core (110) ([0021]); a first adhesive layer (112) ([0022]) bonded to an entirety of the polycrystalline ceramic core, which is indefinite as discussed above under 35 USC 112(b) rejections; a conductive layer (114) ([0024]) bonded to an entirety of the first adhesive layer as necessary, which is also indefinite as discussed above under 35 USC 112(b) rejections; a second adhesive layer (116) ([0027]) bonded to an entirety of the conductive layer or to the entirety of the first adhesive layer, which is also indefinite as discussed above under 35 USC 112(b) rejections; and a barrier layer (118) ([0028]) bonded to an entirety of the second adhesive layer, which is also indefinite as discussed above under 35 USC 112(b) rejections.
Since both Ostermaier et al./Arena et al. and Odnoblyudov et al. teach a method for manufacturing a nitride semiconductor substrate, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the composite substrate disclosed by Ostermaier et al. in view of Saito et al. and further in view of Arena et al. can have the claimed configuration as disclosed by Odnoblyudov et al., because (a) (at least some of) the materials constituting the composite substrate disclosed by Odnoblyudov et al. are disclosed in paragraph [0018] of Arena et al. as discussed above with regard to claim 24, (b) the composite substrate disclosed by Odnoblyudov et al. incorporated into the composite substrate disclosed by Ostermaier et al./Arena et al. would allow one of ordinary skill in the art to control and optimize the difference between the coefficient of thermal expansion of the composite substrate and the coefficient of thermal expansion of the semiconductor layers formed on the composite substrate ([0004] of Odnoblyudov et al.), which would allow one of ordinary skill in the art to improve quality of the semiconductor layers since one of ordinary skill in the art would be able to better control the epitaxial growth process and the subsequent cooling process.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Arena et al. (US 8,692,260)
Ostermaier et al. (US 10,199,216)
Gardner et al. (US 2019/0067081)
Sato (US 2012/0034768)
Yoshiharu et al. (US 4,925,809)
Yamamoto (US 9,355,852)
Faure et al. (US 8,093,138)
Boussagol et al. (US 7,615,468)
Letertre et al. (US 6,794,276)
Lochtefeld et al. (US 10,347,794)
Odnoblyudov et al. (US 10,655,243)
Odnoblyudov et al. (US 10,297,445)
Odnoblyudov et al. (US 10,833,186)
Odnoblyudov et al. (US 10,734,303)
Ghyselen et al. (US 8,173,512)
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 March 26, 2026
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