DETAILED ACTION
Claims 1-4 are pending in the Instant Application.
Claims 1-4 are rejected (Non-Final Rejection).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The Instant Application, filed 07/17/2023, is a National Stage entry of PCT/EP2022/050607, International Filing Date 01/13/2022, which claims foreign priority to 21152987.0, filed 01/22/2021 in the European Patent Office. Thus, the earliest effective filing date is 1/22/2021.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 7/17/2023 and 11/12/2025 were considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Hӧfig et al. (“Hofig”), European Patent Application No. EP-3579074-A1, published 11 December 2019.
As per claim 1, Hofig discloses a computer-implemented method for resolving closed loops in automatic fault tree analysis of a multi-component system ([0012] wherein the method is recited), the method comprising:
a. modeling the multi-component system using a fault tree, the fault tree comprising elements associated with components of the multi-component system and interconnections between the elements associated with functional dependencies between the components ([0012] wherein the claim language, most importantly the modeling using the fault tree comprising components and their dependencies is described);
b. back-tracing failure propagation paths rom an output element of the fault tree via the interconnections towards one or more input elements of the fault tree ([0012] wherein the back-tracing is described);
c. checking, for all failure propagation paths, if the respective failure propagation path contains a closed loop by identifying a downstream element of the respective failure propagation path having a dependency of an output value on an output value of an upstream element-of the failure propagation path ([0012] wherein the checking if the failure propagation path contains a closed loop is described);
d. setting the input value corresponding to a loop interconnection of each downstream element to Boolean TRUE ([0012] wherein the limitations for setting the input value to TRUE is recited);
e. identifying any Boolean AND-gate having, independently of the specific values of the input elements, no Boolean TRUE as output value ([0012] wherein any Boolean AND-gate having no Boolean TRUE value as output is identified as they are replaced in the prior art);
cutting off any Boolean TRUE input to any identified Boolean AND-gate between the respective downstream element and the respective upstream element ([0012] wherein the Boolean TRUE input are cut off to any of the identified Boolean AND-gates); and
f. setting the input value of each respective downstream element corresponding to the loop interconnection to Boolean FALSE ([0012] wherein the input value is set to Boolean FALSE as described).
As per claim 2, Hofig discloses the method according to claim 1, wherein the fault tree is expressed within Boolean algebra by iteratively expanding the fault tree into Boolean expressions at the elements ([0018] wherein the fault tree is expressed with Boolean expressions and are iteratively expanding).
As per claim 3, Hofig discloses the method according to claim 1, wherein the closed loop of the fault tree is associated with a closed-loop control circuitry of the multi-component system ([0019] wherein closed-loop control circuity) .
As per claim 4, Hofig discloses a device comprising a processor configured to perform the method according to claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KANNAN SHANMUGASUNDARAM whose telephone number is (571)270-7763. The examiner can normally be reached M-F 9:00 AM -6:00 PM.
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/KANNAN SHANMUGASUNDARAM/Primary Examiner, Art Unit 2168
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