DETAILED ACTION
Claims 1-4 are pending in the Instant Application.
Claims 1-4 are rejected (Final Rejection).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Hӧfig et al. (“Hofig”), European Patent Application No. EP-3579074-A1, published 11 December 2019.
As per claim 1, Hofig discloses a computer-implemented method for resolving closed loops in automatic fault tree analysis of a multi-component system ([0012] wherein the method is recited), the method comprising:
a. modeling the multi-component system using a fault tree, the fault tree comprising elements associated with components of the multi-component system and interconnections between the elements associated with functional dependencies between the components ([0012] wherein the claim language, most importantly the modeling using the fault tree comprising components and their dependencies is described);
b. back-tracing failure propagation paths rom an output element of the fault tree via the interconnections towards one or more input elements of the fault tree ([0012] wherein the back-tracing is described);
c. checking, for all failure propagation paths, if the respective failure propagation path contains a closed loop by identifying a downstream element of the respective failure propagation path having a dependency of an output value on an output value of an upstream element-of the failure propagation path ([0012] wherein the checking if the failure propagation path contains a closed loop is described);
d. setting the input value corresponding to a loop interconnection of each downstream element to Boolean TRUE ([0012] wherein the limitations for setting the input value to TRUE is recited);
e. identifying any Boolean AND-gate having, independently of the specific values of the input elements, no Boolean TRUE as output value ([0012] wherein any Boolean AND-gate having no Boolean TRUE value as output is identified as they are replaced in the prior art);
cutting off any Boolean TRUE input to any identified Boolean AND-gate between the respective downstream element and the respective upstream element ([0012] wherein the Boolean TRUE input are cut off to any of the identified Boolean AND-gates); and
f. setting the input value of each respective downstream element corresponding to the loop interconnection to Boolean FALSE ([0012] wherein the input value is set to Boolean FALSE as described).
As per claim 2, Hofig discloses the method according to claim 1, wherein the fault tree is expressed within Boolean algebra by iteratively expanding the fault tree into Boolean expressions at the elements ([0018] wherein the fault tree is expressed with Boolean expressions and are iteratively expanding).
As per claim 3, Hofig discloses the method according to claim 1, wherein the closed loop of the fault tree is associated with a closed-loop control circuitry of the multi-component system ([0019] wherein closed-loop control circuity) .
As per claim 4, Hofig discloses a device comprising a processor configured to perform the method according to claim 1.
Response to Arguments
Applicant's arguments filed 26 May 2026 have been fully considered but they are not persuasive.
Applicant states in REMARKS, page 4, that “Hofig does not teach "identifying any Boolean AND-gate having, independently of the specific values of the input elements, no Boolean TRUE as output value," as recited in element (e) of claim 1.” Examiner asserts that the equivalent actions are performed by the prior art, but described in different terms. In [0012] of Hofig discloses “identifying any Boolean AND-gate having, independently of the specific values of the input elements, no Boolean TRUE as output value,” by determining “any Boolean AND-gate remaining.”
To begin analysis, the Instant Application further recites “cutting off any Boolean TRUE input to any identified Boolean AND-gate between the respective downstream element and the respective upstream element.” The Hofig reference also teaches “cutting off any Boolean TRUE input to any Boolean AND-gate… between the respective downstream element and the respective upstream element;” however, instead of performing this on the identified Boolean AND-gate,” Hofig performs this on the remainder of Boolean AND-gates. The determination of the “remainder” in Hofig is the ”identifying of a “Boolean AND-gate having, independently of the specific values of the input elements, no Boolean TRUE as output value," since earlier in Hofig, any Boolean AND-gate having… Boolean TRUE as output value were replaced with a Boolean OR-gate between the respective downstream element and the respective upstream element. Thus, all that is left, the “remainder” have no Boolean true as an output value. So, by identifying the “remainder,” Hofig identifies any Boolean AND-gate with no Boolean TRUE as output.
Applicant goes on to state in REMARKS, page 4, that “Hofig does not teach "cutting off any Boolean TRUE input to any identified Boolean AND-gate between the respective downstream element and the respective upstream element," as recited in claim 1.” However, Examiner has shown that Hofig “identifies” the Boolean AND-gate by determining the remainder. Since the remainder is the same set as the identified, and Hofig discloses “cutting off any Boolean TRUE input to any remaining/identified Boolean AND-gate and the remainder is also identified, the Hofig properly discloses the claim language above.
Applicant argues in REMARKS, page 5, that “Hofig requires a replacement step that is entirely absent from the claims.” A prior art reference can teach more than the limitations in a claim and still disclose the invention. In this case Hofig actually provides a manner by which the claim could “[[identify]] any Boolean AND-gate having, independently of the specific values of the input elements, no Boolean TRUE as output value.” Applicant would have to affirmatively exclude the “replacement step” for this argument to be pursuasive.
Applicant argues on page 5 that the Instant Application and Hofig resolve loops through “fundamentally different algorithms.” Applicant is encouraged to include such differences in the claim language. The Hofig references discloses each element of the claimed invention as currently provided since determining the remainder of Boolean AND-gates would identify the AND-gates with no Boolean TRUE as output. Applicant is encouraged to either elaborate on the differences of the prior art and include those limitations in the claim to further prosecution. All other REMARKS, rely on the arguments above and the same rationale and reasoning applies. If questions remain, please contact the Examiner for an interview.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KANNAN SHANMUGASUNDARAM whose telephone number is (571)270-7763. The examiner can normally be reached M-F 9:00 AM -6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles Rones can be reached at (571) 272-4085. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KANNAN SHANMUGASUNDARAM/Primary Examiner, Art Unit 2168
Prosecution Insights