DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/30/2026 was filed after the mailing date of the Non-Final Rejection on 10/10/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 6-9, filed 01/30/2026, with respect to the drawings have been fully considered and are persuasive. The objection of the drawings has been withdrawn.
Applicant’s arguments, see pages 6-9, filed 01/30/2026, with respect to the rejection(s) of claims 1-20 under 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kobayashi et al. (US 20170092177 A1) in view of Kurokawa (US 20190067360 A1) and (Yamazaki et al. (US 20080042180 A1).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 20170092177 A1) in view of Kurokawa (US 20190067360 A1) and (Yamazaki et al. (US 20080042180 A1).
Regarding claim 1, Kobayashi discloses a semiconductor device comprising:
a first layer (184); ([0071], Fig. 2)
a second layer (165) over the first layer (184); ([0075], Fig. 3) and
a third layer (163) over the second layer (165), ([0075], Fig. 3)
wherein the first layer (184) comprises a storage unit (133) including memory cells (inside 133). ([0064], [0070], Fig. 1)
Kobayashi does not disclose:
wherein the second layer comprises a circuit including a first transistor, wherein the third layer comprises pixel circuits each including a second transistor, wherein the third layer comprises light-emitting elements, wherein one of the pixel circuits is electrically connected to one of the light-emitting elements, wherein the circuit is configured to control an operation of the pixel circuits, and wherein the one of the pixel circuits is configured to control emission luminance of the one of the light-emitting elements.
However, Kurokawa discloses:
wherein second layer (1400) comprises a circuit (31 or 32) including a first transistor (per [0191]), (Fig. 11b)
wherein the third layer (1100+1200) comprises pixel circuits (41 and 42) each including a second transistor (per [0101]), (Fig. 11A)
wherein the third layer (1100+1200) comprises light-emitting elements (60), (Fig. 11A)
wherein one of the pixel circuits (41) is electrically connected to one of the light-emitting elements (60), ([0198], Fig. 11A)
wherein the circuit (31 or 32) is configured to control an operation of the pixel circuits (Fig. 11A) and
wherein the one of the pixel circuits (41 and 42) is configured to control emission luminance of the one of the light-emitting elements (60). ([0123], Fig. 11A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi and Kurokawa to arrive at the claimed invention in order to “provide a semiconductor device with an image processing function” (Kurokawa, [0017])
Kobayashi in view of Kurokawa do not disclose:
wherein the first layer and the second layer are bonded to each other.
However, Yamazaki discloses:
wherein the first layer (301a) and the second layer (302a) are bonded to each other (by 306). ([0114], Fig. 3B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa and Yamazaki for wherein the first layer and the second layer are bonded to each other “so that it adheres” (Yamazaki, [0099])
Regarding claim 2, Kurokawa discloses the semiconductor device according to claim 1,
wherein the first transistor (31 or 32) is a Si transistor (per [0194]), and
wherein the second transistor (41 or 42) is a Si transistor (per 0196]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa and Yamazaki for similar reasons mentioned above.
Regarding claim 3, Yamazaki discloses the semiconductor device according to claim 2,
a region wherein the first layer (301a) and the second layer (302a) include regions that are connected to each other by Cu-Cu bonding (in layer 306). ([0114], Fig. 3B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa and Yamazaki for similar reasons mentioned above.
Regarding claim 4, Kurokawa discloses the semiconductor device according to claim 1,
wherein the first transistor (31 or 32) is a Si transistor (per [0194]), and
wherein the second transistor (41) is an OS transistor (per [0156, [0196]]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa and Yamazaki for similar reasons mentioned above.
Regarding claim 5, Kobayashi discloses the semiconductor device according to claim 1,
wherein the circuit comprises at least one of a CPU, a GPU, a super-resolution circuit, a sensor circuit, a communication circuit, and an input/output circuit. ([0063])
Regarding claim 6, Kobayashi discloses the semiconductor device according to claim 1,
wherein each of the light-emitting elements (DE2) is an organic EL element (per [0095]). (Fig. 5A)
Regarding claim 7, Kurokawa discloses the semiconductor device according to claim 6,
wherein each of the light-emitting elements (60) comprises a tandem structure (see Fig. 11A).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa and Yamazaki for similar reasons mentioned above.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 20170092177 A1) in view of Kurokawa (US 20190067360 A1) and (Yamazaki et al. (US 20080042180 A1) as applied to claim 1 above, and further in view of Ikeda et al. (US 20230022181 A1).
Regarding claim 8, Kobayashi in view of Kurokawa and Yamazaki disclose the semiconductor device according to claim 1. Kobayashi in view of Kurokawa and Yamazaki do not disclose
wherein in a region including pixel circuits and the light- emitting elements, a diagonal size of the region is greater than or equal to 0.5 inches and less than or equal to 2.0 inches.
However, Ikeda discloses:
wherein in a region (30) including pixel circuits (34) and the light- emitting elements (572), a diagonal size of the region (30) is greater than or equal to 0.5 inches and less than or equal to 2.0 inches. ([0166], [0528], Table 2, page 39)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa, Yamazaki and Ikeda to have a region including pixel circuits and the light- emitting elements, a diagonal size of the region is greater than or equal to 0.5 inches and less than or equal to 2.0 inches so that “a high-performance display device provided with driver circuits can be obtained” (Ikeda, [0004])
Claim 16-20 are rejected under 35 U.S.C. 103 as being unpatentable Kobayashi et al. (US 20170092177 A1) in view of Kurokawa (US 20190067360 A1) and (Yamazaki et al. (US 20080042180 A1).
Regarding claim 16, Kobayashi discloses a semiconductor device comprising:
a first layer (184); ([0071], Fig. 2)
a second layer (165) over the first layer (184); ([0075], Fig. 3) and
a third layer (163) over the second layer (165), ([0075], Fig. 3)
wherein the first layer (184) comprises a storage unit (133) including memory cells (inside 133). ([0064], [0070], Fig. 1)
Kobayashi does not disclose:
wherein the second layer comprises a circuit,
wherein the third layer comprises a display portion including pixels,
wherein the circuit comprises a storage unit driver circuit and a display portion driver circuit, and
wherein each of the pixels comprises a pixel circuit and a light-emitting element over the pixel circuit.
However, Kurokawa discloses:
wherein second layer (1400) comprises a circuit (31 or 32) (Fig. 11b)
wherein the third layer (1100+1200) comprises a display portion including pixels, ([0020], [0462], Fig. 3B and 43A)
wherein the circuit (31/32) comprises a storage unit driver circuit (31) and a display portion driver circuit (32), ([0192], Fig. 11A) and
wherein each of the pixels (per [0020]) comprises a pixel circuit (41) and a light-emitting element (60) over the pixel circuit (41). (Fig. 11A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi and Kurokawa to arrive at the claimed invention in order to “provide a semiconductor device with an image processing function” (Kurokawa, [0017])
Kobayashi in view of Kurokawa do not disclose:
wherein the first layer and the second layer are bonded to each other.
However, Yamazaki discloses:
wherein the first layer (301a) and the second layer (302a) are bonded to each other (by 306). ([0114], Fig. 3B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa and Yamazaki for wherein the first layer and the second layer are bonded to each other “so that it adheres” (Yamazaki, [0099])
Regarding claim 17, Kurokawa discloses the semiconductor device according to claim 16,
wherein the circuit (31) comprises a second transistor (31), (Fig. 10)
wherein the pixel circuit (41) comprises a third transistor (41), and
and a composition of a second semiconductor layer (35) included in the second transistor (31) are different from a composition of a third semiconductor layer included in the third transistor (41). ([0194] - [0196]), Fig. 10)
Kurokawa does not disclose:
wherein each of the memory cells comprises a first transistor,
however, Yamazaki discloses:
wherein each of the memory cells comprises a first transistor, (Fig. 3B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kurokawa and Yamazaki for each of the memory cells comprises a first transistor in order to have “a circuit to operate a memory element” (Yamazaki, [0074]) so as to “a semiconductor device including a memory circuit which is non-volatile, easily manufactured, and can be additionally written” (Yamazaki, [0004])
Regarding claim 18, Yamazaki discloses the semiconductor device according to claim 16,
wherein the storage unit (16) comprises a DRAM (per [0068]). (Fig. 1B and 3B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kobayashi, Kurokawa, and Yamazaki for the storage unit comprises a DRAM a conventional choice in the art so as to have “a semiconductor device having higher function and added value” (Yamazaki, [0003])
Regarding claim 19, Kobayashi discloses the semiconductor device according to claim 16,
wherein each of the light-emitting elements (DE2) is an organic EL element (per [0095]). (Fig. 5A)
Regarding claim 20, Kobayashi discloses the semiconductor device according to claim 19,
wherein each of the light-emitting elements (DE2) comprises a tandem structure (per [0095]).
Allowable Subject Matter
Claim 9-15 are allowed.
The following is an examiner’s statement of reasons for allowance: The allowable subject matter for The allowable subject matter for claim 9 is “wherein the memory chips are arranged along at least part of an outer periphery of the display portion”.
The closest prior art appears to be Kobayashi et al. (US 20170092177 A1) in view of Yamazaki et al. (US 20080042180 A1) and Kurokawa (US 20190067360 A1) and which teaches an analogous device including:
Regarding 9, Kobayashi discloses a semiconductor device comprising:
a first layer (184); ([0071], Fig. 2)
a second layer (160) over the first layer (184); ([0075], Fig. 3) and
a sealing substrate (162) over the second layer (160), ([0075], Fig. 3)
wherein the first layer (184) comprises a circuit ([0071]), (Fig. 2)
wherein the second layer (160) comprises a display portion (160) including pixels (110), ([0074], Fig. 2-4B)
wherein the display portion (160) and the storage unit (133) are covered with the sealing substrate (162). (Fig. 2)
Yamazaki discloses:
wherein the first layer (401a) and the second layer (401b) are bonded to each other (by 306). ([0114], Fig. 5A)
wherein the second layer (402a) comprises a storage unit including memory chips (454). (Fig. 4B)
Kurokawa discloses:
wherein each of the pixels (60) comprises a pixel circuit (41) and a light-emitting element (61) over the pixel circuit (41), (Fig. 11A)
Claims 10-15 are allowable for being dependent on allowable independent claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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