DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on September 01, 2026. Claims 1, 7, 10 and 15 have been amended. No new claims have been added. No claims have been canceled. Claims 5, 9 and 14 have been withdrawn. Currently, claims 1-4, 6-8, 10-13 and 15 are pending.
Applicant’s amendment to claims 1, 7, 10 and 15 successfully overcomes the 112(b) rejection of claims 1, 7, 10 and 15 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 10 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-8, 10-13 and 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claims 1 and 10, the claim recites a first step of depositing a first protective dielectric film and a second step of anisotropically etching the first protective dielectric film, followed by a third step of “repeating the first step and second step a plurality of time” to form a stacked film including the first protective dielectric film and a second protective dielectric film having a composition different from that of the first protective dielectric film.
It is unclear whether “repeating the first step and the second step” requires repeated deposition and etching of the first protective dielectric film or instead requires depositing and anisotropically etching successive protective dielectric films of different compositions, including the recited second protective dielectric film. The claim does not clearly recite the deposition and anisotropic etching of the second protective dielectric film. Accordingly, the scope of the claimed third step is unclear.
The claims further recite, “wherein the second protective film is formed over the first protective film to fill a plurality of gaps present at the second semiconductor layers of the stacked film caused by the etching of the stacked film;” where “second protective film” and “first protective film” are indefinite and lack antecedent basis.
Claims 2-4 and 6-8 depend upon claim 1 and do not rectify the problem therefore they are also rejected.
Claims 11-13 and 15 depend upon claim 10 and do not rectify the problem therefore they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US 10,103,238 B1) in view of Song et al. (US 2023/0261079 A1; hereafter Song) and Ando et al. (US 2019/0157414 A1; hereafter Ando).
Regarding claim 1, Zang teaches a method for manufacturing a semiconductor device (see e.g., Figures 1, 11-16) that includes a stacked channel in which thin or sheet-shaped channels are stacked in a direction perpendicular to a substrate in a gate formation region (see e.g., nanosheet channel layers 10 are stacked in a direction perpendicular to the substrate 14 in a sacrificial gate structure 20 region, Column 3, Lines 5-20, Figure 11), and in which a gate and a semiconductor substrate are isolated from each other by an insulating film (see e.g., conformal dielectric layer 58 fills up the cavity 38 to define a dielectric isolation region between the substrate 14 and the sacrificial gate structure 20, Figure 16),
the semiconductor device having a structure in which a stacked film is provided in which a plurality of first semiconductor layers and a plurality of second semiconductor layers are alternately stacked on the semiconductor substrate (see e.g., semiconductor layers 11 and 13 are formed in an alternating sequence on a substrate 14. The semiconductor layers 11 are composed of silicon and the semiconductor layers 13 are composed of silicon germanium, Column 2, Lines 25-35, Figure 1), the gate and a gate sidewall spacer film are further formed on the stacked film (see e.g., sacrificial gate structures 20 are formed on the top surface of the semiconductor layers 11, 13 in the layer stack. Each sacrificial gate structure 20 is covered by a dielectric cap 22 that is located on its top surface, and dielectric spacers 24 that are located adjacent to its vertical sidewalls, Colum 2, Lines 60-65, Figure 1), a part of the stacked film is removed by etching along the gate sidewall spacer film, and a part or all of a lowermost first semiconductor layer or a part or all of a lowermost second semiconductor layer formed on the lowermost first semiconductor layer are left without being etched (see e.g., the semiconductor layer 19 may have the same composition as of semiconductor layers 13 and maybe thicker than the individual semiconductor layers 13. Trenches 28 are formed that extend through the semiconductor layers 11 and 13 to form nanosheet channel layers 10 and sacrificial layers 12. The trenches 28 are not extended through the semiconductor layer 19, instead the trenches 28 are terminated at the top surface of the semiconductor layer 19, Column 7, Lines 4-11, Figure 11),
the method comprising:
a first step of depositing a first protective dielectric film on a sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers that are formed by the etching (see e.g., a conformal dielectric layer 31 is formed on the sidewalls of the nanosheet channel layers 10 and the etched sacrificial layers 12, Column 7, Lines 25-30, Figure 12);
a second step of subjecting the protective dielectric film to anisotropic etching in a vertical direction (see e.g., the conformal dielectric layer 31 is subjected to one or more etching processes, such as reactive ion etching (RIE) in a vertical direction, Column 7, Lines 30-36, Figures 12 and 13);
a fourth step of removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by etching (see e.g., the sacrificial layer 18 is removed by etching to form cavities 38, Column 7, Lines 51-60, Figure 15).
Zang does not explicitly teach
“a first step of depositing a first protective dielectric film …on a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer;
.. subjecting the first protective dielectric film to anisotropic etching in a vertical direction to expose the surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer”.
In a similar field of endeavor Song teaches
a first step of depositing a first protective dielectric film …on a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer;
.. subjecting the first protective dielectric film to anisotropic etching in a vertical direction to expose the surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer (see e.g., after the formation of the first source/drain holes, a sidewall of the preliminary channel structure and a top surface of the first semiconductor pattern SP1 are exposed. A protection layer is conformally deposited on the entire surface of the substrate 100 and anisotropically etched to form protective spacers SSP on the sidewalls of the first source/drain holes. As a result of the anisotropic etching, the first semiconductor pattern SP1 is exposed between the protective spacers, Paras [0044], [0093], Figures 10B, 11B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Song’s teachings of a first step of depositing a first protective dielectric film …on a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer; .. subjecting the first protective dielectric film to anisotropic etching in a vertical direction to expose the surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer in the method of Zang in order to protect the sidewalls of the stacked channel structure during subsequent selective removal of the lower semiconductor material while leaving the lower semiconductor surface exposed for such removal.
Zang does not explicitly teach
“a third step of repeating the first step and the second step a plurality of times and forming, on the sidewall, a stacked film of protective dielectric films including the first protective dielectric film and a second protective dielectric film having a composition that is different from a composition of the first protective dielectric film, wherein the second protective film is formed over the first protective dielectric film to fill a plurality of gaps present at the second semiconductor layers of the stacked film caused by the etching of the stacked film;”
In a similar field of endeavor Ando teaches
a third step of repeating the first step and the second step a plurality of times and forming, on the sidewall, a stacked film of protective dielectric films including the first protective dielectric film and a second protective dielectric film having a composition that is different from a composition of the first protective dielectric film, wherein the second protective film is formed over the first protective dielectric film to fill a plurality of gaps present at the second semiconductor layers of the stacked film caused by the etching of the stacked film (see e.g., a stack of alternating sacrificial semiconductor layers 104 and channel semiconductor layers 106. The sacrificial semiconductor layers 104 are laterally recessed to form recessed sacrificial layers 302.
A first inner spacer 402 is conformally deposited within the recesses formed by the recessed sacrificial layers 302. The first inner spacer layer 402 may comprise silicon nitride. The first inner spacer layer 402 is anisotropically etched from exposed surfaces while retaining the dielectric material within the sidewall recesses. The first inner spacer layer is formed to a thickness that intentionally leaves residual gaps 404 within the recesses.
The dielectric deposition and anisotropic etching process is repeated. A second inner spacer layer 502 is conformally deposited into the residual gaps 404 left by first inner spacer layer 402 to fill the remaining portions of the recesses. Second inner spacer layer 502 comprises silicon dioxide and therefore has a composition different from the silicon nitride first inner spacer layer 402. The second inner spacer layer 502 is anisotropically etched from exposed surfaces, Paras [0033] – [0036], Figures 3-5);
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Ando’s teachings of a third step of repeating the first step and the second step a plurality of times and forming, on the sidewall, a stacked film of protective dielectric films including the first protective dielectric film and a second protective dielectric film having a composition that is different from a composition of the first protective dielectric film, wherein the second protective film is formed over the first protective dielectric film to fill a plurality of gaps present at the second semiconductor layers of the stacked film caused by the etching of the stacked film in the method of Zang to predictably provide more complete filling of the recessed spacer regions while retaining dielectric material on the semiconductor stack sidewalls and removing unwanted dielectric material from exposed horizontal surfaces.
Regarding claim 3, Zang, as modified by Song and Ando, teaches the limitations of claim 1 as mentioned above. Zang further teaches
the first semiconductor layers are silicon germanium (see e.g., semiconductor layers 13 are composed of silicon germanium, Column 2, Lines 25-32, Figure 1), and the second semiconductor layers are silicon (see e.g., semiconductor layers 11 are composed of silicon, Column 2, Lines 25-32, Figure 1).
Zhao does not explicitly teach
“wherein the semiconductor substrate is silicon,”
In a similar field of endeavor Song teaches
wherein the semiconductor substrate is silicon (see e.g., the substrate maybe a silicon substrate, Para [0030], Figure 10B),
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Song’s teachings of wherein the semiconductor substrate is silicon in the method of Zang as it is a commonly used substrate in semiconductor manufacturing.
Regarding claim 10, Zang teaches a plasma processing method for performing plasma processing on a structure (see e.g., Figures 1, 11-16) in which a stacked film is provided in which a plurality of first semiconductor layers and a plurality of second semiconductor layers are alternately stacked on a semiconductor substrate (see e.g., nanosheet channel layers 10 are stacked in a direction perpendicular to the substrate 14 in a sacrificial gate structure 20 region, Column 3, Lines 5-20, Figure 11), a gate and a gate sidewall spacer film are further formed on the stacked film (see e.g., sacrificial gate structures 20 are formed on the top surface of the semiconductor layers 11, 13 in the layer stack. Each sacrificial gate structure 20 is covered by a dielectric cap 22 that is located on its top surface, and dielectric spacers 24 that are located adjacent to its vertical sidewalls, Colum 2, Lines 60-65, Figure 1), a part of the stacked film is removed by etching along the gate sidewall spacer film, and a part or all of a lowermost first semiconductor layer or a part or all of a lowermost second semiconductor layer formed on the lowermost first semiconductor layer are left without being etched (see e.g., the semiconductor layer 19 may have the same composition as of semiconductor layers 13 and maybe thicker than the individual semiconductor layers 13. Trenches 28 are formed that extend through the semiconductor layers 11 and 13 to form nanosheet channel layers 10 and sacrificial layers 12. The trenches 28 are not extended through the semiconductor layer 19, instead the trenches 28 are terminated at the top surface of the semiconductor layer 19, Column 7, Lines 4-11, Figure 11),
the plasma processing method comprising continuously performing:
a first step of depositing a first protective dielectric film on a sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers that are formed by the etching (see e.g., a conformal dielectric layer 31 is formed on a sidewall of the nanosheet channel layers 10 and the sacrificial layers 12, Column 7, Lines 25-30, Figure 12);
a second step of subjecting anisotropic etching to the first protective dielectric film in a vertical direction (see e.g., the conformal dielectric layer 31 is subjected to one or more etching processes, such as reactive ion etching (RIE) in a vertical direction, Column 7, Lines 30-36, Figures 12 and 13);
a fourth step of removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by etching (see e.g., the sacrificial layer 18 is removed by etching, Column 7, Lines 51-60, Figure 15).
Zang does not explicitly teach
“a third step of repeating the first step and the second step a plurality of times and forming, on the sidewall, a stacked film of protective dielectric films including the first protective dielectric film and a second protective dielectric film having a composition that is different from a composition of the first protective dielectric film, wherein the second protective film is formed over the first protective dielectric film to fill a plurality of gaps present at the second semiconductor layers of the stacked film caused by the etching of the stacked film;”
In a similar field of endeavor Ando teaches
a third step of repeating the first step and the second step a plurality of times and forming, on the sidewall, a stacked film of protective dielectric films including the first protective dielectric film and a second protective dielectric film having a composition that is different from a composition of the first protective dielectric film, wherein the second protective film is formed over the first protective dielectric film to fill a plurality of gaps present at the second semiconductor layers of the stacked film caused by the etching of the stacked film (see e.g., a stack of alternating sacrificial semiconductor layers 104 and channel semiconductor layers 106. The sacrificial semiconductor layers 104 are laterally recessed to form recessed sacrificial layers 302.
A first inner spacer 402 is conformally deposited within the recesses formed by the recessed sacrificial layers 302. The first inner spacer layer 402 may comprise silicon nitride. The first inner spacer layer 402 is anisotropically etched from exposed surfaces while retaining the dielectric material within the sidewall recesses. The first inner spacer layer is formed to a thickness that intentionally leaves residual gaps 404 within the recesses.
The dielectric deposition and anisotropic etching process is repeated. A second inner spacer layer 502 is conformally deposited into the residual gaps 404 left by first inner spacer layer 402 to fill the remaining portions of the recesses. Second inner spacer layer 502 comprises silicon dioxide and therefore has a composition different from the silicon nitride first inner spacer layer 402. The second inner spacer layer 502 is anisotropically etched from exposed surfaces, Paras [0033] – [0036], Figures 3-5);
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Ando’s teachings of a third step of repeating the first step and the second step a plurality of times and forming, on the sidewall, a stacked film of protective dielectric films including the first protective dielectric film and a second protective dielectric film having a composition that is different from a composition of the first protective dielectric film, wherein the second protective film is formed over the first protective dielectric film to fill a plurality of gaps present at the second semiconductor layers of the stacked film caused by the etching of the stacked film in the method of Zang to predictably provide more complete filling of the recessed spacer regions while retaining dielectric material on the semiconductor stack sidewalls and removing unwanted dielectric material from exposed horizontal surfaces.
Zang does not explicitly teach
“a first step of depositing a first protective dielectric film … on a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer;
.. subjecting anisotropic etching to the first protective dielectric film in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer
..removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by isotropic etching”
In a similar field of endeavor Song teaches
a first step of depositing a first protective dielectric film … on a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer;
.. subjecting anisotropic etching to the first protective dielectric film in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer (see e.g., after the formation of the first source/drain holes, a sidewall of the preliminary channel structure and a top surface of the first semiconductor pattern SP1 are exposed. A protection layer is conformally deposited on the entire surface of the substrate 100 and anisotropically etched to form protective spacers SSP on the sidewalls of the first source/drain holes. As a result of the anisotropic etching, the first semiconductor pattern SP1 is exposed between the protective spacers, Paras [0044], [0093], Figures 10B, 11B)
…removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by isotropic etching (see e.g., isotropic etching process may be performed to remove the first semiconductor pattern SP1, Para [0094], Figure 10B, 11B)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Song’s teachings of a first step of depositing a first protective dielectric film … on a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer; .. subjecting anisotropic etching to the first protective dielectric film in a vertical direction to expose a surface of the lowermost first semiconductor layer or the lowermost second semiconductor layer …removing the lowermost first semiconductor layer or the lowermost first semiconductor layer and the lowermost second semiconductor layer by isotropic etching in the method of Zang protect the sidewalls of the stacked channel structure during subsequent selective removal of the lower semiconductor material while leaving the lower semiconductor surface exposed for such removal.
Regarding claim 15, Zang, as modified by Song and Ando, teaches the limitations of claim 1 as mentioned above. Zang further teaches
wherein in the first step and the third step, the protective dielectric film is deposited by an ALD method (see e.g., conformal dielectric film 31 deposited by ALD, Column 3, Lines 53-60, Figure 12).
Claims 2, 6-8 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US 10, 103,238 B1) in view of Song et al. (US 2023/0261079 A1; hereafter Song) and Ando et al. (US 2019/0157414 A1; hereafter Ando) and further in view of Zhou et al. (US 2019/0157095 A1; hereafter Zhou).
Regarding claim 2, Zang, as modified by Song and Ando, teaches the limitations of claim 1 as mentioned above. Zang does not explicitly teach
“wherein the first step to the fourth step are performed continuously in the same plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integrating atomic layer deposition (ALD) and etching operations within a single plasma processing chamber using in-situ ALD. Such integration eliminates the need for separate ALD and additional cleaning tools, reduces substrate transfers and cleaning time, avoids vacuum breaks between processing steps and thereby reduces processing time and manufacturing cost.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 6, Zang, as modified by Song and Ando, teaches the limitations of claim 1 as mentioned above. Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, the first step to the fourth step, and a step of removing the stacked film of the protective dielectric films by isotropic etching are performed continuously in the same plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integrating atomic layer deposition (ALD) and etching operations within a single plasma processing chamber using in-situ ALD. Such integration eliminates the need for separate ALD and additional cleaning tools, reduces substrate transfers and cleaning time, avoids vacuum breaks between processing steps and thereby reduces processing time and manufacturing cost.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 7, Zang, as modified by Song and Ando, teaches the limitations of claim 1 as mentioned above. Zang further teaches
in a subsequent step the insulating film for isolating the gate and the semiconductor substrate is deposited and subjected to vertical etching (see e.g., a conformal dielectric layer 58 deposited and isotopically etched to form dielectric spacers 60 that fill the cavities 29. The conformal dielectric layer 58 also fills the cavities 38 to define the dielectric isolation region 36, Column 7, Lines 6166, Column 8, Lines 1-5, Figure 16).
Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, and the first step to the fourth step are performed continuously in the same plasma processing apparatus”,
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integrating atomic layer deposition (ALD) and etching operations within a single plasma processing chamber using in-situ ALD. Such integration eliminates the need for separate ALD and additional cleaning tools, reduces substrate transfers and cleaning time, avoids vacuum breaks between processing steps and thereby reduces processing time and manufacturing cost.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 8, Zang, as modified by Song and Ando, teaches the limitations of claim 1 as mentioned above. Zang does not explicitly teach
“wherein after removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, sidewalls of the first semiconductor layers other than the lowermost layer are subjected to isotropic etching, and thereafter, the first step to the fourth step and a step of removing the stacked film of the protective dielectric films by isotropic etching are performed continuously in the same plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integrating atomic layer deposition (ALD) and etching operations within a single plasma processing chamber using in-situ ALD. Such integration eliminates the need for separate ALD and additional cleaning tools, reduces substrate transfers and cleaning time, avoids vacuum breaks between processing steps and thereby reduces processing time and manufacturing cost.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 11, Zang, as modified by Song and Ando, teaches the limitations of claim 10 as mentioned above. Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by the vertical etching, the first step to the fourth step, and a step of removing the stacked film of the protective dielectric films by the isotropic etching are performed continuously in one plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integrating atomic layer deposition (ALD) and etching operations within a single plasma processing chamber using in-situ ALD. Such integration eliminates the need for separate ALD and additional cleaning tools, reduces substrate transfers and cleaning time, avoids vacuum breaks between processing steps and thereby reduces processing time and manufacturing cost.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 12, Zang, as modified by Song and Ando, teaches the limitations of claim 10 as mentioned above. Zang does not explicitly teach
“wherein vertical etching of the gate sidewall spacer film in order to form the gate sidewall spacer film, a step of removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by vertical etching, and the first step to the fourth step are performed continuously in one plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integrating atomic layer deposition (ALD) and etching operations within a single plasma processing chamber using in-situ ALD. Such integration eliminates the need for separate ALD and additional cleaning tools, reduces substrate transfers and cleaning time, avoids vacuum breaks between processing steps and thereby reduces processing time and manufacturing cost.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Regarding claim 13, Zang, as modified by Song and Ando, teaches the limitations of claim 10 as mentioned above. Zang further teaches
wherein after removing a part of the stacked film including the first semiconductor layers and the second semiconductor layers by the vertical etching, sidewalls of the first semiconductor layers other than the lowermost first semiconductor layer are subjected to isotropic etching (see e.g., after forming the nanosheet channel layers 10 and the sacrificial layers 12, the sacrificial layers 12 are partially laterally recessed with an isotropic etching process, Column 3, Lines 26-35, Figure 3)
Zang does not explicitly teach
“thereafter, the first step to the fourth step and a step of removing the stacked film of the protective dielectric film by the isotropic etching are performed continuously in one plasma processing apparatus”.
Zang is silent as to the processing steps are either performed in the same or different chambers thereby not precluding that all the processing steps maybe performed in the same plasma processing chamber.
In a similar field of endeavor Zhou teaches integrating atomic layer deposition (ALD) and etching operations within a single plasma processing chamber using in-situ ALD. Such integration eliminates the need for separate ALD and additional cleaning tools, reduces substrate transfers and cleaning time, avoids vacuum breaks between processing steps and thereby reduces processing time and manufacturing cost.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement processing steps continuously in the same plasma apparatus since use of separate chambers for deposition and etching increases processing time, processing steps, and costs, thus adversely affecting throughput. Moreover, the use of separate chambers requires transferring substrates from one chamber to another, which entails vacuum breaks and increases the likelihood of unwanted materials or particles coming into contact with the substrates. This may cause loss of material functionality and/or integrity on the substrate.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US 10,103,238 B1) in view of Song et al. (US 2023/0261079 A1; hereafter Song) and Ando et al. (US 2019/0157414 A1; hereafter Ando) and further in view of Chen et al. (US 2022/0029023 A; hereafter Chen).
Regarding claim 4, Zang, as modified by Song and Ando, teaches the limitations of claim 1 as mentioned above. Zang further teaches
wherein among the stacked film of the protective dielectric films, a film that is in contact with the sidewall of the stacked film including the first semiconductor layers and the second semiconductor layers is formed of a film containing a silicon element and a nitrogen element (see e.g., The conformal dielectric layer 31 may be composed of a dielectric material, such as silicon nitride (Si.sub.3N.sub.4), Column 3, Lines 50-60, Figure 12),
Zang does not explicitly teach
“a film that is located on an upper layer side of the stacked film of the protective dielectric films is formed of a film containing an aluminum element and an oxygen element”.
In a similar field of endeavor Chen teaches a multilayer inner spacer including a first inner spacer layer 224-1 and a second inner spacer layer 224-2 (see e.g., Paras [0027], [0028], Figure 4). Chen teaches that the first and second inner spacer layers may have different compositions selected from, among other materials, silicon nitride, aluminum oxynitride, aluminum oxide, silicon oxycarbonitride, silicon carbonitride, zirconium aluminum oxide and other dielectric materials. Chen further teaches that the different compositions permit the second inner spacer layer to be selectively etched relative to the first inner spacer layer.
Accordingly, it would have been obvious to one skilled in art to form the first inner spacer layer of silicon nitride and the second inner spacer layer of aluminum oxide to provide compositionally different spacer layers having different etch rates and thereby permit selective etching of one spacer layer relative to the other.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to implement Chen’s teachings of a film that is located on an upper layer side of the stacked film of the protective dielectric films is formed of a film containing an aluminum element and an oxygen element in the method of Zang to provide different etch rates between spacer layers and thereby allow one spacer layer to be selectively etched relative to the other during fabrication.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
