DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7 -12 of argument, filed 02/10/2026, with respect to claims 1-5 and 7 have been fully considered and are not persuasive. The previous rejection of claims 1- 5 and 7 has been upheld. No new claims have been added.
The Examiner acknowledges the corrected Replacement Drawing Sheets which address Fig. 9, 10 and 11. The previous drawing objection is withdrawn.
Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Reference Ito, Shingo (US 20190090359)Fig. 2B, is relied upon to show the obvious method of completely removing the photoresist for a particular layer.
The 35 USC § 103 rejection is upheld. The Examiner respectfully disagrees with the argument on page 9 -10, that Chunyang et al. (CN 111799245), herein referred to as Chunyang, does not teach the amended limitations of independent claim 1 and claim 7 “ removing the outwardly exposed metal layer other than the target position, wherein, except the target position, the surface of the wafer is not covered with the metal layer or the photoresist”. As is clearly shown in Fig. 5 of Chunyang, the metal layer (5) has been formed after patterning with a photoresist. Any subsequent “retaining of the photoresist” is for the forming of a different layer not on layer (5). As disclosed in Chunyang [0058], “The first seed layer 5 can be formed by the following process: forming a first seed layer 5 that completely covers the surface of the wafer 1 by sputtering or electrodeposition, and removing the first seed layer 5 outside the marking area and all redistribution areas by etching.” Thus, Chunyang teaches the complete removal of the photoresist from the seed layer itself.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 1 and 3 - 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li Chunyang et al. (CN 111799245), herein referred to as Chunyang in view of Ito, Shingo (US 20190090359) herein referred to as Ito. (Chunyang Figs. 5 and 12) (Ito Fig. 2B)
As to claim(s) 1, Chunyang teaches a method for preparing a dielectric layer on a surface of a wafer, comprising:
providing a wafer (Fig. 12, [0039] wafer (1)), wherein the wafer is provided with a substrate (Fig. 1, [0039] chip (2)),
a bonding pad (Fig. 1, [0039] pad (3)) formed on the substrate and a passivation layer ([0010] “…a position of the first passivation layer corresponding to the bonding pad;”), and
the bonding pad is exposed outwardly from a passivation layer (Figs. 3 - 8. 12, [0040] (4)) opening in the passivation layer ([0010]”… forming a bonding pad opening at a position of the first passivation layer (4) corresponding to the bonding pad…”);
covering an upper surface of the wafer ([0039] wafer (1)) with a metal layer (Fig. 12, [0010] “forming a first seed layer (5) in the marking region”) having a thickness of not less than 0.3 µm ([0057] range of 0.2 - 1 µm), wherein
the metal layer (1st seed layer 5 is directly attached to the surface of the substrate [0057] “ The material of the first seed layer can be a single metal or a metal alloy, and the thickness of the first seed layer 5 can be 0.2- 1μm.”) is a UBM layer shaped on the upper surface of the wafer ([0039] wafer (1)).
covering an upper surface of the metal layer with a photoresist ([0076] “Photoresist is coated on the side surface of the wafer 1 where the second seed layer 9 is formed”) to form a photoresist layer;
removing the photoresist layer other than a target position, such that the remaining photoresist layer forms a photoresist block above the target position ([0087] “The photoresist is exposed and developed to remove the photoresist on the surface of the first seed layer 5.”), and
the metal layer (1st seed layer (5) is the metal layer) other than the target position
(layer 6 is the target position) is exposed outwardly;
removing the photoresist block after the outwardly exposed metal layer other than the target position is removed, so as to enable the metal layer at the target position to form a metal block which is used as an alignment mark on the upper surface of the wafer and is only arranged on the passivation layer ([0087] “The photoresist is exposed and developed to remove the photoresist on the surface of the first seed layer 5”); and
forming a dielectric layer (2nd passivation layer 8) on the upper surface of the wafer where the metal block (layer (5) is the metal layer formed into a metal block as shown in Applicants drawings Figs. 3 - 8) is formed.
Chunyang expressly discloses " removing the outwardly exposed metal layer other than the target position, wherein, except the target position, the surface of the wafer is not covered with the metal layer or the photoresist, "
However, Chunyang also mentions "([0087] “The photoresist is exposed and developed to remove the photoresist on the surface of the first seed layer 5, while retaining the photoresist in the area outside the first seed layer 5.)
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that the photoresist is removed from layer 5 after it is fully formed, and that any subsequent retaining of a photoresist is for a different layer of the device formed at a different time, as is stated in in the disclosure that what is retained is “in the area outside the first seed layer 5”.
It is well known in the art that once the photoresist is removed, the exposed portions of the seed layer are the result of a patterning process yielding the remaining portions of the seed layer, which were protected from etching through the photo resist process so as to use an industrially tested and accepted device/process.)
The Ito device discloses in [0043] that the exposure mask includes a predetermined pattern, developing, post-baking, wet-etching, and removing of the photoresist film. This reference is cited to show that the Chunyang device, like the Ito device, both perform the use of a photoresist process that includes the subsequent removal of that particular photoresist for that layer.
As to claim(s) 3, the Chunyang/Ito combination teaches the method for preparing the dielectric layer on the surface of the wafer according to claim 1, as discussed above, and further discloses wherein "removing the photoresist layer other than a target position" comprises:
shielding a photoresist layer at the target position by using a mask [0015];, and
exposing the photoresist layer other than the target position [0015-0016]; and
removing the photoresist other than the target position by means of a development technique ([0058] …and removing the first seed layer 5 outside the marking area and all redistribution areas by etching).
As to claim(s) 4, the Chunyang/Ito combination teaches the method for preparing the dielectric layer (layer 8) on the surface of the wafer according to claim 3, as discussed above, and further discloses wherein
the development technique is to dissolve the photoresist in a region other than the target position by using a chemical developer ([0064] The develop techniques: exposure development and wet etching involves using a chemical developer. “The marking opening 81 and the solder joint opening 82 can be formed by exposure development, laser etching or wet etching.”), so as to enable the metal layer under the photoresist to be exposed on the surface of the wafer.
As to claim(s) 5, the Chunyang/Ito combination teaches a wafer structure prepared by the method for preparing the dielectric layer on the surface of the wafer according to claim 1, as discussed above, and further discloses comprising
a substrate, a bonding pad formed on the substrate and a passivation layer, wherein
the bonding pad is exposed outwardly from a passivation layer opening in the passivation layer; and
an alignment mark ([0059-0060] initial mark 6 is formed) is formed on an upper surface of the passivation layer (4), and is a metal block (5) with a thickness of not less than 0.3 µm. ([0057] range of 0.2 -1 µm),
As to claim(s) 6, the Chunyang/Ito combination teaches the wafer structure according to claim 5, as discussed above, and further discloses wherein
the metal block is a UBM layer ([0011] (5) is UBM as a metal layer, See Fig. 12).
As to claim(s) 7, the Chunyang/Ito combination teaches a method for shaping a bump as discussed above, and further discloses a method comprising:
providing a wafer, wherein the wafer is provided with a substrate,
a bonding pad formed on the substrate and a passivation layer, and
the bonding pad is exposed outwardly from a passivation layer opening in the passivation layer;
covering an upper surface of the wafer with a metal layer having a thickness of not less than 0.3 µm, wherein
the metal layer is a UBM layer shaped on the upper surface of the wafer;
covering an upper surface of the metal layer with a photoresist to form a photoresist layer; ([0014] the first seed layer in the wafer other than the first seed layer for plating protection coverage may include: [0015] coating a photoresist on a side surface of the wafer formed with the first seed layer 5; exposing and developing the photoresist, removing the photoresist on the surface of the first seed layer 5.”)
removing the photoresist layer other than a target position, such that the remaining photoresist layer forms a photoresist block above the target position and the metal layer other than the target position is exposed outwardly;
removing the photoresist block after the outwardly exposed metal layer other than the target position is removed, so as to enable the metal layer at the target position to form a metal block which is used as an alignment mark on the upper surface of the wafer and is only arranged on the passivation layer;
forming a dielectric layer (layer 8) on the upper surface of the wafer ([0039] wafer (1)), where the alignment mark ([0059-0060] pattern of (5) that is under (6) is formed;
removing the dielectric layer above the passivation layer opening to outwardly expose the bonding pad ([0094] Fig. 8 “…the initial identifier 6, and a solder joint opening 82 is formed in the second passivation layer 8 at the position corresponding to the preset lead-out point of the rewiring circuit 7”…);
covering an upper surface of the dielectric layer (8) and an upper surface of the bonding pad (3) with a seed layer ([0066], 2nd seed layer 9) ; ([0013] “…coating a photoresist on the side surface of the wafer where the second seed layer is formed…”)
forming the photoresist layer on the seed layer ([0013] “…coating a photoresist on the side surface of the wafer where the second seed layer is formed…”), and
then removing the photoresist layer at the target position to form a photoresist layer pane for outwardly exposing the bonding pad
([0013] “…removing the photoresist from the surface of the wafer outside the solder joint opening.”); and
shaping a metal bump in the photoresist layer pane ([0016] “the formation of a second seed layer on the surface of the redistribution circuit at the solder joint opening”) .
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li Chunyang et al., herein referred to as Chunyang (CN 111799245), in view of Ito, Shingo (US 20190090359) herein referred to as Ito, and further in view of Chen et al. (US 20220319870) herein referred to as Chen.
As to claim(s) 2, the Chunyang/Ito combination teaches the method for preparing the dielectric layer on the surface of the wafer according to claim 1, wherein
the UBM layer ([0012] layer 5, 1st seed layer) The material of the first seed layer can be a single metal or a metal alloy. The second seed layer is made of copper or a titanium-copper alloy.) is the UBM layer comprises a chromium layer, a chromium-copper layer and a copper layer from bottom to top (obvious).
Chunyang does not appear to expressly disclose the UBM layer comprising a chromium layer, a chromium-copper layer and a copper layer from bottom to top but does explicitly state that the UBM layer is a metal or metal alloy.
However, Chen teaches in [0056] the UBM layer 20 includes a chromium layer, a chromium-copper (50%-50%) layer, or a copper layer from bottom to top.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the UBM layer of the Chunyang device, a chromium layer, a chromium-copper layer and a copper layer from bottom to top such as is used in the Chen device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SHAWN SHAW MUSLIM/
Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897