Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 9-15, in the reply filed on 01/20/2026 is acknowledged.
Claim Objections
Claim 11 is objected to because of the following informalities: The limitation of ‘the second conductivity type’ (last line in claim 11) was never previously disclosed in claim 11 or in its base claim 9. As per the context based from the withdrawn claim 4 and the specifications, it will be assumed that the second conductivity type stems from the well region’s material, therefore claim 11 will be rejected as such below.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fang et al. (CN-110310992-A referred as Fang) in view of Liu et al. (US-20180151579-A1 referred as Liu).
Regarding claim 9. Fang discloses a semiconductor device having a split gate structure, comprising:
a base, having a first surface formed with a trench ([pg. 5-6 of translation, paragraphs below S200], figure 3A, a base #100/110 having a first surface formed with a trench #120);
a trench wall oxide isolation dielectric, disposed on an inner surface of the trench ([pg. 8, second and third full paragraphs], figure 3F, a trench wall oxide isolation dielectric #125 is disposed on an inner surface of the trench #120);
a split gate, disposed at a bottom of the trench where the trench is not filled with the trench wall oxide isolation dielectric ([pg. 7 of translation, paragraphs below S250], figure 3F, a split gate #123 is disposed at a bottom of the trench #120 where the trench is not filled with the trench wall oxide isolation dielectric #125. Due to the properties of #123 functioning as a floating gate, it would also read on being used as a split gate for its versatility);
a control gate, located in the upper part of the trench ([pg. 7 of translation, paragraphs below S250], figure 3F, a control gate #126 located in the upper part of the trench #120); and
an isolation structure, located between the split gate and the control gate ([pg. 7 of translation, paragraphs below S250], figure 3F, an isolation structure #124 is located in between the split gate #123 and the control gate #126).
Fang lacks the isolation structure including a first oxide isolation dielectric disposed on the split gate, and a second oxide isolation dielectric disposed near the control gate, and a silicon nitride isolation dielectric disposed between the first oxide isolation dielectric and the second oxide isolation dielectric.
Liu discloses the isolation structure including a first oxide isolation dielectric disposed on the split gate ([0022], figure 1a, the isolation structure #136 includes a first oxide isolation dielectric #136L disposed on the split gate #134), and a second oxide isolation dielectric disposed near the control gate ([0022], figure 1a, a second oxide isolation dielectric #136u disposed near the control gate #138), and a silicon nitride isolation dielectric disposed between the first oxide isolation dielectric and the second oxide isolation dielectric ([0022], figure 1a, and a silicon nitride isolation dielectric #136m disposed between the first oxide isolation dielectric #136L and the second oxide isolation dielectric #136u).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Fang to further include the isolation structure with a silicon nitride isolation dielectric, first oxide isolation dielectric and a second oxide isolation dielectric as taught by Liu in order to enhance the devices electrical protection, reduced in erosion buildup, and to increase the devices lifetime.
Regarding claim 11. Fang as modified discloses a well region, having a second conductivity type, is formed outside the trench and on two sides of the control gate ([pg. 7 of translation, paragraphs below S250], figure 3G, a well region #130, having a second conductivity type of being P-type doping, is seen formed outside the trench #120 and on two sides of the control gate #126); and
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Annotated close up figure 3G
a source region, having a first conductivity type, and formed outside the trench, wherein the source region comprises a first region and a second region ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, a source region #131, having a first conductivity type of N-Type doping, is formed outside the trench #120 and wherein the source region #131 comprises a first region #RG1 and second region #RG2);
wherein the first region of the source region is formed on a surface of the well region ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the first region #RG1 of the source region #131 is formed on a surface of the well region #130), the second region of the source region is located close to sidewalls of the trench ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the second region #RG2 of the source region #131 is located close to the sidewalls of the trench #120), and the depth of the first region of the source region is less than that of the second region of the source region ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the vertical depth of the first region #RG1 is less than the depth of the second region #RG2 of the source region #131);
wherein the first conductivity type and the second conductivity type are opposite conductivity types ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the first conductivity type of N-Type doping and the second conductivity type of being P-type doping are opposite conductivity types).
Regarding claim 12. Fang as modified discloses wherein a top of the control gate is lower than a top of the trench, to form a height difference between the source region and the control gate ([pg. 7 of translation, paragraphs below S250], figure 3F, the top of the control gate #126 is lower than a top of the trench #120 which creates a height difference between the source region #131 and the control gate #126).
Regarding claim 13. Fang as modified discloses an interlayer dielectric, disposed on the base and the control gate ([pg. 7 of translation, paragraphs below S250], figure 3G, an interlayer dielectric #140 disposed on the base #110/100 and the control gate #126); and
a source electrode, disposed on the interlayer dielectric, and electrically connected to the source region through a conductive material filled in contact holes, wherein the contact holes extend downward through the interlayer dielectric into the source region ([pg. 7 of translation, paragraphs below S250], figure 3G, a source electrode #S disposed on the interlayer dielectric #140 and electrically connected to the source region #131 through the contact holes #141 which, with injecting doping, would allow conductivity).
Regarding claim 14. Fang as modified discloses a doped region of a second conductivity type, wherein the doped region of the second conductivity type is disposed within the well region and under the source region ([pg. 7 of translation, paragraphs below S250], figure 3G, a doped region #232 of the second conductive type being P-type is seen disposed within the well region #230 and under the source region #231);
wherein the contact holes extend downward through the source region into the doped region of the second conductivity type ([pg. 7 of translation, paragraphs below S250], figure 3G, the contact holes #241 extend downwards through the source region #231 and into the doped region #232).
Regarding claim 15. Fang as modified discloses wherein the semiconductor device is a vertical double-diffused metal oxide semiconductor field effect transistor ([pg. 2 of translation, paragraphs below Background], figure 3G, the semiconductor device is a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) as dsecribed), and wherein the semiconductor device further comprises a drain disposed on a second surface of the base, the second surface of the base being opposite to the first surface of the base ([pg. 7 of translation, paragraphs below S250], figure 3G, the semiconductor device further includes a drain #D disposed on a second surface of the base #200/210).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fang et al. (CN-110310992-A referred as Fang) and Liu et al. (US-20180151579-A1 referred as Liu) in further view of Liu et al. (CN-111430464-A referred as Liu #2).
Regarding claim 10. Fang as modified lacks wherein the silicon nitride isolation dielectric is disposed at a bottom and sides of the second oxide isolation dielectric.
Liu #2 discloses wherein the silicon nitride isolation dielectric is disposed at a bottom and sides of the second oxide isolation dielectric ([pg. 10 of translation, at the bottommost paragraph starting with “the dielectric isolation..”], figure 25, the silicon nitride isolation dielectric #12.2 is disposed at a bottom and sides of the second oxide isolation dielectric #12.3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Fang as modified to further include the silicon nitride isolation dielectric is disposed at a bottom and sides of the second oxide isolation dielectric as taught by Liu in order to enhance the devices electrical protection, reduce device failure, and to increase the devices lifetime.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Qiao et al. (CN-113078067-A) and Qi (CN-109216174-B) for the gate electrodes, the format of insulators, and the source/drain region.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818