Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 9-15, in the reply filed on 01/20/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fang et al. (CN-110310992-A referred as Fang) in view of Liu et al. (US-20180151579-A1 referred as Liu).
Regarding claim 9. Fang discloses a semiconductor device having a split gate structure, comprising:
a base, having a first surface formed with a trench ([pg. 5-6 of translation, paragraphs below S200], figure 3A, a base #100/110 having a first surface formed with a trench #120);
a trench wall oxide isolation dielectric, disposed on an inner surface of the trench ([pg. 8, second and third full paragraphs], figure 3F, a trench wall oxide isolation dielectric #125 is disposed on an inner surface of the trench #120);
a split gate, disposed at a bottom of the trench where the trench is not filled with the trench wall oxide isolation dielectric ([pg. 7 of translation, paragraphs below S250], figure 3F, a split gate #123 is disposed at a bottom of the trench #120 where the trench is not filled with the trench wall oxide isolation dielectric #125. Due to the properties of #123 functioning as a floating gate, it would also read on being used as a split gate for its versatility);
a control gate, located in the upper part of the trench ([pg. 7 of translation, paragraphs below S250], figure 3F, a control gate #126 located in the upper part of the trench #120); and
an isolation structure, located between the split gate and the control gate ([pg. 7 of translation, paragraphs below S250], figure 3F, an isolation structure #124 is located in between the split gate #123 and the control gate #126).
a well region, formed outside the trench and on two sides of the control pate ([pg. 7 of translation, paragraphs below S250], figure 3G, a well region #130 is formed outside the trench #120 and on two sides of the control gate #126); and
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Annotated close up figure 3G
a source region, formed outside the trench, wherein the source region comprises a first region and a second region ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, a source region #131 is formed outside the trench #120 and wherein the source region #131 comprises a first region #RG1 and second region #RG2); wherein the first region of the source region is formed on a surface of the well region ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the first region #RG1 of the source region #131 is formed on a surface of the well region #130), the second region of the source region is located close to sidewalls of the trench ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the second region #RG2 of the source region #131 is located close to the sidewalls of the trench #120), and a depth of the first region of the source region is less than that of the second region of the source region ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the vertical depth of the first region #RG1 is less than the depth of the second region #RG2 of the source region #131).
Fang lacks the isolation structure including a first oxide isolation dielectric disposed on the split gate, and a second oxide isolation dielectric disposed near the control gate, and a silicon nitride isolation dielectric disposed between the first oxide isolation dielectric and the second oxide isolation dielectric; wherein the silicon nitride isolation dielectric is of a same height as the first oxide isolation dielectric and the second oxide isolation dielectric.
Liu discloses the isolation structure including a first oxide isolation dielectric disposed on the split gate ([0022], figure 1a, the isolation structure #136 includes a first oxide isolation dielectric #136L disposed on the split gate #134), and a second oxide isolation dielectric disposed near the control gate ([0022], figure 1a, a second oxide isolation dielectric #136u disposed near the control gate #138), and a silicon nitride isolation dielectric disposed between the first oxide isolation dielectric and the second oxide isolation dielectric ([0022], figure 1a, and a silicon nitride isolation dielectric #136m disposed between the first oxide isolation dielectric #136L and the second oxide isolation dielectric #136u);
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Rotated and Annotated figure 1a
wherein the silicon nitride isolation dielectric is of a same height as the first oxide isolation dielectric and the second oxide isolation dielectric ([0022], annotated figure 1a above, when figure 1a is rotated clockwise, it is illustrated that the silicon nitride isolation dielectric #136m, first oxide isolation dielectric #136L, and the second oxide isolation dielectric #136u are all the same height as seen in line #h1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Fang to further include the isolation structure with a silicon nitride isolation dielectric, first oxide isolation dielectric and a second oxide isolation dielectric as taught by Liu in order to enhance the devices electrical protection, reduced in erosion buildup, and to increase the devices lifetime.
Regarding claim 11. Fang as modified discloses wherein the source region has a first conductivity type ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, a source region #131 having a first conductivity type of N-Type doping); wherein the well region has a second conductivity type ([pg. 7 of translation, paragraphs below S250], figure 3G, a well region #130, having a second conductivity type of being P-type doping); and wherein the first conductivity type and the second conductivity type are opposite conductivity types ([pg. 7 of translation, paragraphs below S250], annotated close up figure 3G above, the first conductivity type of N-Type doping and the second conductivity type of being P-type doping are opposite conductivity types).
Regarding claim 12. Fang as modified discloses wherein a top of the control gate is lower than a top of the trench, to form a height difference between the source region and the control gate ([pg. 7 of translation, paragraphs below S250], figure 3F, the top of the control gate #126 is lower than a top of the trench #120 which creates a height difference between the source region #131 and the control gate #126).
Regarding claim 13. Fang as modified discloses an interlayer dielectric, disposed on the base and the control gate ([pg. 7 of translation, paragraphs below S250], figure 3G, an interlayer dielectric #140 disposed on the base #110/100 and the control gate #126); and
a source electrode, disposed on the interlayer dielectric, and electrically connected to the source region through a conductive material filled in contact holes, wherein the contact holes extend downward through the interlayer dielectric into the source region ([pg. 7 of translation, paragraphs below S250], figure 3G, a source electrode #S disposed on the interlayer dielectric #140 and electrically connected to the source region #131 through the contact holes #141 which, with injecting doping, would allow conductivity).
Regarding claim 14. Fang as modified discloses a doped region of a second conductivity type, wherein the doped region of the second conductivity type is disposed within the well region and under the source region ([pg. 7 of translation, paragraphs below S250], figure 3G, a doped region #232 of the second conductive type being P-type is seen disposed within the well region #230 and under the source region #231);
wherein the contact holes extend downward through the source region into the doped region of the second conductivity type ([pg. 7 of translation, paragraphs below S250], figure 3G, the contact holes #241 extend downwards through the source region #231 and into the doped region #232).
Regarding claim 15. Fang as modified discloses wherein the semiconductor device is a vertical double-diffused metal oxide semiconductor field effect transistor ([pg. 2 of translation, paragraphs below Background], figure 3G, the semiconductor device is a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) as dsecribed), and wherein the semiconductor device further comprises a drain disposed on a second surface of the base, the second surface of the base being opposite to the first surface of the base ([pg. 7 of translation, paragraphs below S250], figure 3G, the semiconductor device further includes a drain #D disposed on a second surface of the base #200/210).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fang et al. (CN-110310992-A referred as Fang) and Liu et al. (US-20180151579-A1 referred as Liu) in further view of Liu et al. (CN-111430464-A referred as Liu #2).
Regarding claim 10. Fang as modified lacks wherein the silicon nitride isolation dielectric is disposed at a bottom and sides of the second oxide isolation dielectric.
Liu #2 discloses wherein the silicon nitride isolation dielectric is disposed at a bottom and sides of the second oxide isolation dielectric ([pg. 10 of translation, at the bottommost paragraph starting with “the dielectric isolation..”], figure 25, the silicon nitride isolation dielectric #12.2 is disposed at a bottom and sides of the second oxide isolation dielectric #12.3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Fang as modified to further include the silicon nitride isolation dielectric is disposed at a bottom and sides of the second oxide isolation dielectric as taught by Liu in order to enhance the devices electrical protection, reduce device failure, and to increase the devices lifetime.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Fang et al. (CN-110310992-A referred as Fang) and Liu et al. (US-20180151579-A1 referred as Liu) in further view of Lin et al. (TW-I715335-B referred as Lin – see attached machine translation for citations).
Regarding claim 16. Fang as modified lacks wherein each of the silicon nitride isolation dielectric and the first oxide isolation dielectric is a U- shaped structure, the first oxide isolation dielectric being disposed at a bottom and sides of the silicon nitride isolation dielectric.
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Flipped figure 13
Lin discloses wherein each of the silicon nitride isolation dielectric and the first oxide isolation dielectric is a U-shaped structure, the first oxide isolation dielectric being disposed at a bottom and sides of the silicon nitride isolation dielectric ([pg 3, paragraph 7 from Machine Translation], flipped figure 13 above, the first oxide isolation dielectric #137 is disposed at a bottom and sides of silicon nitride isolation dielectric #136. Which together form a U-shape structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Fang as modified to further include wherein each of the silicon nitride isolation dielectric and the first oxide isolation dielectric is a U-shaped structure as taught by Lin in order to enhance the devices electrical protection, reduce device failure, and to increase the devices lifetime.
Response to Amendment
Applicant's arguments filed 05/07/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art to Fang et al. as modified by Liu et al.. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Applicant has added the limitation “wherein the silicon nitride isolation dielectric is of a same height as the first oxide isolation dielectric and the second oxide isolation dielectric” and argued that the same height is not present in the reference cited. The secondary reference, Liu et al., does in fact disclose this feature as seen in the new rejection and annotated figure 1a above due to the rotation of the figure allowing a vertical height from a different perspective. Applicant has also added the limitation “a depth of the first region of the source region is less than that of the second region of the source region” which is disclosed by Fang et al. and also seen in the new rejection above.
Furthermore, applicant argues that the source region seen in Fang et al. figure does not describe the first and second region within the source region without function distinction. It is a fact that a region does not have any fixed characteristics within an element, therefore it is flexible for the region within the element to be annotated as seen in the figure and rejection above. If Applicant described in the claim more details of what structurally makes up the regions or how the regions are delineated from each other, this interpretation would be unavailable. But the claim language currently just describes the source region of having at least two regions/parts that really are just described as far as positioning.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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