DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 7, 11 and 12 in the Applicant’s response dated 4 May 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendment to the title of the instant application in the Applicant’s response dated 4 May 2026. The objection to the specification is therefore withdrawn.
The Examiner acknowledges the amendment to claim 7 in the Applicant’s response dated 4 May 2026 in lieu of the claim objection presented in the previous office action. The claim objection is therefore withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jun Tanaka et al. (US 2021/0013245 A1; hereinafter “Tanaka”) in view of Joon Seok Park et al. (US 2021/0036029 A1; hereinafter “Park”).
Regarding Claim 1, Tanaka teaches a semiconductor device comprising:
a first transistor (170, Fig. 4, para [0087] describes an oxide semiconductor transistor 170); and
a second transistor (230, Fig. 4, para [0100] describes an oxide semiconductor transistor 230),
wherein the first transistor comprises a third insulating layer (121, Fig. 4 viewed inverted vertically, para [0089] describes an interlayer insulating layer 121), a first semiconductor layer over the third insulating layer (173, Fig. 4 viewed inverted vertically, para [0081] describes an oxide semiconductor film layer 173 over the third insulating layer 121), a first insulating layer over the first semiconductor layer (219, Fig. 4 viewed inverted vertically, para [0101] describes an insulating layer 219 that is over the first semiconductor layer 173 when viewing Fig. 4 inverted vertically), a second insulating layer over the first insulating layer (117, Fig. 4 viewed inverted vertically, para [0083] describes an insulating layer 117 that is over the first insulating layer 219 when viewing Fig. 4 inverted vertically), and a first gate electrode over the second insulating layer (171, Fig. 4 viewed inverted vertically, para [0087] describes a gate electrode 171 that is over the second insulating layer 117 when viewing Fig. 4 inverted vertically),
wherein the second transistor comprises the third insulating layer (121, Fig. 4 viewed inverted vertically, para [0089] describes the third insulating layer 121), the first insulating layer over the third insulating layer (219 and 121, Fig. 4 viewed inverted vertically, para [0101] describes the first insulating layer 219 over the third insulating layer 121), a second semiconductor layer over the first insulating layer (133, Fig. 4 viewed inverted vertically, para [0081] describes an oxide semiconductor film layer 133 over the first insulating layer 219), the second insulating layer over the second semiconductor layer (117, Fig. 4 viewed inverted vertically, para [0083] describes wherein insulating layer 117 is over the second semiconductor layer 133 when viewing Fig. 4 inverted vertically), and a second gate electrode over the second insulating layer (131, Fig. 4 viewed inverted vertically, para [0085] describes a gate electrode 131 that is over the second insulating layer 117 when viewing Fig. 4 inverted vertically),
wherein a thickness of the third insulating layer in a region not overlapping with the first semiconductor layer is smaller than a thickness of the third insulating layer in a region overlapping with the first semiconductor layer (121, Fig. 4 viewed inverted vertically, para [0088] describes wherein source/drain electrodes 175 and 177 are provided above and in contact with the first insulating layer 219 wherein source/drain electrodes 175 and 177 are seen protruding out from the first semiconductor layer 173 resulting in portions of the third insulating layer 121 covering the source/drain electrodes 175 and 177 in a region not overlapping with the first semiconductor layer 173 being smaller than a thickness of the third insulating layer 121 in a region overlapping the first semiconductor layer 173 between the source/drain electrodes 175 and 177),
wherein each of the first semiconductor layer and the second semiconductor layer comprises indium (133 and 173, Fig. 4 viewed inverted vertically, para [0082] describes wherein first semiconductor film 173 and second semiconductor film 133 may be comprised of indium), and
wherein an atomic ratio of the indium in the second semiconductor layer to metal elements in the second semiconductor layer (133, para [0082] describe wherein second semiconductor layer 133 may be comprised of an oxide semiconductor layer comprising indium such as IGZTO) is different from an atomic ratio of the indium in the first semiconductor layer to metal elements in the first semiconductor layer (173, para [0082] describe wherein first semiconductor layer 173 may be comprised of an oxide semiconductor layer comprising indium such as IGZO wherein IGZO would have a different atomic ratio of indium to metal elements than the atomic ratio of indium to metal elements in the second IGZTO semiconductor layer 133).
Tanaka fails to explicitly disclose wherein a thickness of the first insulating layer in a region not overlapping with the second semiconductor layer is smaller than a thickness of the first insulating layer in a region overlapping with the second semiconductor layer.
However, Park teaches a similar semiconductor device wherein a thickness of the first insulating layer (130, Fig. 7, para [0104] describes a first gate insulating layer 130) in a region not overlapping with the second semiconductor layer (450, Fig. 7, para [0106] describes a second active layer 450 over the first insulating layer 130 wherein the first insulating layer 130 comprises a region not overlapping the second semiconductor layer 450 between a first semiconductor layer 350 and an oxide layer 370 therefore comprising a first thickness) is smaller than a thickness of the first insulating layer in a region overlapping with the second semiconductor layer (130, 350 and 450, Fig. 7 and Fig. 17, para [0106] describes the first semiconductor layer 350 wherein Fig. 17 depicts a portion of the first insulating layer 130 is between the first semiconductor layer and the first oxide layer 370 comprising a thickness that is smaller than a thickness of the first insulating layer 130 under and overlapping the second semiconductor layer 450 which does not have a thickness reduced by the first semiconductor layer 350).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Park to further disclose a semiconductor device wherein a thickness of the first insulating layer in a region not overlapping with the second semiconductor layer is smaller than a thickness of the first insulating layer in a region overlapping with the second semiconductor layer in order to provide the advantage of including a gate insulating layer over a first semiconductor layer increasing the number of carriers in the active layer increasing the mobility of the transistor and thus exhibiting excellent device characteristics (Park, para [0115]).
Regarding Claim 2, the combination of Tanaka and Park teaches the semiconductor device according to claim 1, wherein the first insulating layer comprises a first region in contact with a top surface of the first semiconductor layer (Tanaka, FR, annotated Fig. 4 depicts wherein a first region FR of the first insulating layer 219 is in contact with a top surface of the first semiconductor layer 173) and a second region in contact with a bottom surface of the second semiconductor layer (Tanaka, SR, annotated Fig. 4 depicts wherein a second region SR of the first insulating layer 219 is in contact with a bottom surface of the second semiconductor layer 133).
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Regarding Claim 7, Tanaka teaches the semiconductor device according to claim 1,
wherein each of the first semiconductor layer and the second semiconductor layer comprises an element M (Tanaka, 133 and 173, Fig. 4 viewed inverted vertically, para [0082] describes wherein first semiconductor film 173 and second semiconductor film 133 may be comprised of indium and at least one additional element such as gallium),
wherein the element M is one or more kinds selected from gallium, aluminum, yttrium, and tin (Tanaka, 133 and 173, Fig. 4 viewed inverted vertically, para [0082] describes wherein first semiconductor film 173 and second semiconductor film 133 may be comprised of indium and at least one additional element such as gallium), and
wherein an atomic ratio of the element M in the second semiconductor layer to metal elements in the second semiconductor layer (Tanaka, 133, para [0082] describe wherein second semiconductor layer 133 may be comprised of an oxide semiconductor layer comprising an element M including tin such as ITZO) is different than an atomic ratio of the element M in the first semiconductor layer to metal elements in the first semiconductor layer (Tanaka, 173, para [0082] describe wherein first semiconductor layer 173 may be comprised of an oxide semiconductor layer comprising an element M including gallium such as IGZO).
The combination of Tanaka and Park fail to explicitly disclose wherein an atomic ratio of the element M in the second semiconductor layer to metal elements in the second semiconductor layer is higher than an atomic ratio of the element M in the first semiconductor layer to metal elements in the first semiconductor layer.
However, Tanaka describes in para [0081] wherein a mobility of the second semiconductor layer (133) may be higher than a mobility of the first semiconductor layer (173) wherein it is well-known to one of ordinary skill in the art that in order to achieve a higher mobility it is common to increase an atomic ratio of a dopant element such as tin, such as may be found in the second semiconductor layer and representing the element M as described in claim 7.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different atomic ratios of tin in the second semiconductor layer resulting in an atomic ratio of the element M in the second semiconductor layer to metal elements in the second semiconductor layer being higher than an atomic ratio of the element M in a first semiconductor layer to metal elements in the first semiconductor layer in order to provide the advantage of increasing mobility in the second semiconductor layer resulting in producing a semiconductor device with high reliability and having the advantage of enabling a slim bezel to be manufactured (Tanaka, para [0081]).
Claims 3-6, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jun Tanaka et al. (US 2021/0013245 A1; hereinafter “Tanaka”) in view of Joon Seok Park et al. (US 2021/0036029 A1; hereinafter “Park”) and in further view of Hiroyuki Miyake et al. (US 2017/0186778 A1; hereinafter “Miyake”).
Regarding Claim 3, the combination of Tanaka and Park discloses all the limitations of claim 1.
Tanaka and Park fail to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than the atomic ratio of the indium in the first semiconductor layer to the metal elements in the first semiconductor layer.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the second semiconductor layer (128, Fig. 1B, para [0125] describes an oxide semiconductor film 128 of a second transistor Tr2) to the metal elements in the second semiconductor layer (128, para [0131] describes wherein the second semiconductor layer 128 may comprise a region wherein the atomic proportion of indium is larger than the atomic proportion of metals) is higher than the atomic ratio of the indium in the first semiconductor layer (108, Fig. 1B, para [0124] describes an oxide semiconductor film 108 of a first transistor Tr1) to the metal elements in the first semiconductor layer (108 and 128, para [0130] describes wherein the compositions of the first oxide semiconductor film 108 and the second oxide semiconductor film 208 may be different from each other, wherein the first oxide semiconductor film 108 may comprise a region in which the atomic proportion of indium is lower than the atomic proportion of metals as describes in para [0129] and further wherein the resulting second semiconductor layer 128 would have a higher proportion of indium to metals than the first semiconductor layer 108).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka and Park with Miyake to further disclose a semiconductor device wherein a second semiconductor layer may have a higher proportion of indium to metal elements than a first semiconductor layer in order to provide the advantage of providing for a second transistor which may have a higher proportion of indium than metal elements which provides the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]) and further providing for a first transistor which has a higher proportion of metal elements than indium which provides the advantage of producing a transistor with stable electrical characteristics due to the metal elements creating a lower chance of oxygen vacancy lowering undesirable and unpredictable results (Miyake, para [0240] and para [0243]).
Regarding Claim 4, the combination of Tanaka and Park discloses all the limitations of claim 1.
Tanaka and Park fail to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of indium to metal elements in a second semiconductor layer 128 may satisfy Indium > metal elements such as an atomic ratio of In:M:Zn=3:1:2 wherein a resulting atomic percentage of indium to the total metal elements is roughly 50% falling within the range of 30 atomic% to 100 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Miyake to further disclose a semiconductor device wherein a second semiconductor device may have an atomic percentage of indium to metal elements that is greater than or equal to 30% and less than or equal to 100% in order to provide the advantage of providing for a transistor which may have a higher proportion of indium than metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Regarding Claim 5, the combination of Tanaka and Park discloses all the limitations of claim 1.
Tanaka and Park fail to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the first semiconductor layer to metal elements in the first semiconductor layer is higher than the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the first semiconductor layer (108, Fig. 1B, para [0124] describes an oxide semiconductor film 108 of a first transistor Tr1) to metal elements in the first semiconductor layer (108, para [0131] describes wherein the first semiconductor layer 108 may comprise a region wherein the atomic proportion of indium is larger than the atomic proportion of metals) is higher than the atomic ratio of the indium in the second semiconductor layer (128, Fig. 1B, para [0125] describes an oxide semiconductor film 128 of a second transistor Tr2) to the metal elements in the second semiconductor layer (108 and 128, para [0130] describes wherein the compositions of the first oxide semiconductor film 108 and the second oxide semiconductor film 208 may be different from each other, wherein the second oxide semiconductor film 128 may comprise a region in which the atomic proportion of indium is lower than the atomic proportion of metals as describes in para [0129] and further wherein the resulting first semiconductor layer 108 would have a higher proportion of indium to metals than the second semiconductor layer 128).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka and Park with Miyake to further disclose a semiconductor device wherein a first semiconductor layer may have a higher proportion of indium to metal elements than a second semiconductor layer in order to provide the advantage of providing for a first transistor which may have a higher proportion of indium than metal elements which provides the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]) and further providing for a second transistor which has a higher proportion of metal elements than indium which provides the advantage of producing a transistor with stable electrical characteristics due to the metal elements creating a lower chance of oxygen vacancy lowering undesirable and unpredictable results (Miyake, para [0240] and para [0243]).
Regarding Claim 6, the combination of Tanaka and Park discloses all the limitations of claim 1.
Tanaka and Park fail to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of indium to metal elements in a first semiconductor layer 108 may satisfy the inequality indium > metal elements such as an atomic ratio of In:M:Zn=3:1:2 wherein a resulting atomic percentage of indium to the total metal elements is roughly 50% falling within the range of 30 atomic% to 100 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka and Park with Miyake to further disclose a semiconductor device wherein a first semiconductor device may have an atomic percentage of indium to metal elements that is greater than or equal to 30% and less than or equal to 100% in order to provide the advantage of providing for a transistor which may have a higher proportion of indium than metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Regarding Claim 8, the combination of Tanaka and Park discloses all the limitations of claim 7.
Tanaka and Park fail to explicitly disclose the semiconductor device according to claim 7, wherein the atomic ratio of the element M in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the element M in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of the element M, such as gallium, in a second semiconductor layer 128 may satisfy the atomic ratio of In:M:Zn=1:1:1 wherein a resulting atomic percentage of M in the second semiconductor layer 128 to the total metal elements is roughly 33% falling within the range of 20 atomic% to 60 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka and Park with Miyake to further disclose a semiconductor device wherein a second semiconductor device may have an atomic percentage of an element M to metal elements that is greater than or equal to 20% and less than or equal to 60% in order to provide the advantage of providing for a transistor which may have a higher than or equal proportion of indium to an element M and other metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Regarding Claim 10, the combination of Tanaka and Park discloses all the limitations of claim 7.
Tanaka and Park fail to explicitly disclose the semiconductor device according to claim 7, wherein the atomic ratio of the element M in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the element M in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of the element M, such as gallium, in a first semiconductor layer 108 may satisfy the atomic ratio of In:M:Zn=1:1:1 wherein a resulting atomic percentage of M in the first semiconductor layer 108 to the total metal elements is roughly 33% falling within the range of 20 atomic% to 60 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka and Park with Miyake to further disclose a semiconductor device wherein a first semiconductor device may have an atomic percentage of an element M to metal elements that is greater than or equal to 20% and less than or equal to 60% in order to provide the advantage of providing for a transistor which may have a higher than or equal proportion of indium to an element M and other metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jun Tanaka et al. (US 2021/0013245 A1; hereinafter “Tanaka”) in view of Joon Seok Park et al. (US 2021/0036029 A1; hereinafter “Park”) and in further view of Shinpei Matsuda et al. (US 2017/0236842 A1; hereinafter “Matsuda”).
Regarding Claim 11, the combination of Tanaka and Park discloses all the limitations of claim 1.
Tanaka and Park fail to explicitly disclose the semiconductor device according to claim 1, wherein the first transistor further comprises a third gate electrode, wherein the third gate electrode comprises a region overlapping with the first gate electrode with the first semiconductor layer therebetween, and wherein the third gate electrode comprises a region overlapping with the first semiconductor layer with the third insulating layer therebetween.
However, Matsuda teaches a similar semiconductor device, wherein the first transistor (100, Fig. 1A, para [0107] describes a transistor 100) further comprises a third gate electrode (105_1, Fig. 6D and Fig. 1A, para [0113] and para [0123] describes an electrode 105_1 that may be a gate electrode),
wherein the third gate electrode comprises a region overlapping with the first gate electrode with the first semiconductor layer therebetween (105_1, 112_1 and 109_1b, Fig. 13C, Fig. 14C and Fig. 1A, para [0121]-para [0123] describes a first gate electrode 112_1 which overlaps with the third gate electrode 105_1 and a first semiconductor layer 109_1b therebetween as shown in Fig. 13C, Fig. 14C and Fig. 1A wherein Fig. 1A is the final device of the methods involved in Fig. 13C and Fig. 14C), and
wherein the third gate electrode comprises a region overlapping with the first semiconductor layer with the third insulating layer therebetween (105_1, 106 and 109_1b, Fig. 6E, Fig. 14C and Fig. 1A, para [0121] - para [0123] wherein Fig. 1A depicts the third gate electrode 105_1 overlapping with the first semiconductor layer 109_1b and the third insulating layer 106 therebetween).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Matsuda to further disclose a semiconductor device that further comprises a third gate electrode and a third insulating layer in order to provide the advantage of increasing the on-state current and field-effect mobility of the transistor device further improving device integration (Matsuda, para [0126] and para [0127]).
Regarding Claim 12, the combination of Tanaka and Matsuda disclose all the limitations of claim 11.
Tanaka fails to explicitly disclose the semiconductor device of claim 11, wherein the second transistor further comprises a fourth gate electrode, wherein the fourth gate electrode comprises a region overlapping with the second gate electrode with the second semiconductor layer therebetween, and wherein the fourth gate electrode comprises a region overlapping with the second semiconductor layer with the first insulating layer and the third insulating layer therebetween.
However, Matsuda teaches a similar semiconductor device, wherein the second transistor (200, Fig. 1A, para [0107] describes a second transistor 200) further comprises a fourth gate electrode (105_2, Fig. 1A and Fig. 9C, para [0134] describes an electrode 105_2),
wherein the fourth gate electrode comprises a region overlapping with the second gate electrode (112_2 and 105_2, Fig. 13B, para [0134] wherein Fig. 1A depicts the fourth gate electrode 105_2 and a second gate electrode 112_2 are overlapping) with the second semiconductor layer therebetween (109_2b1 and 109_2b2, Fig. 8C and Fig. 1A, para [0134] describes a second semiconductor layer 109_2b1 and 109_2b2 between second gate electrode 112_2 and fourth gate electrode 105_2), and
wherein the fourth gate electrode comprises a region overlapping with the second semiconductor layer (Fig. 8C and Fig. 1A, depicts wherein second semiconductor layer 109_2b1 and 109_2b2 comprises a region overlapping with the fourth gate electrode 105_2) with the first insulating layer and the third insulating layer therebetween (Fig. 1A and Fig. 2B depict wherein the first insulating layer 107 and second insulating layer 106 is between the second semiconductor layer 109_2b1 and 109_2b2 and the fourth gate electrode 105_2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Matsuda to further disclose a semiconductor device that further comprises a fourth gate electrode and a fourth insulating layer in order to provide the advantage of increasing the on-state current and field-effect mobility of the transistor device further improving device integration (Matsuda, para [0126] and para [0127]).
Response to Arguments
Applicant’s arguments with respect to claims 1-8 and 10-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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