DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the preliminary amendments to claims 1-8 and 10-12 in the Applicant’s response dated 28 September 2023.
The Examiner acknowledges the cancellation of claims 9 and 13 in the Applicant’s response dated 28 September 2023.
Election/Restrictions
Applicant's election with traverse of Species II, drawn to Device Embodiment II, claims 1-8 and 10, in the reply filed on 12 January 2026 is acknowledged. The traversal is on the grounds that claims 1 and 2 appear to be generic to all Device Embodiments I to XV and that claims 11 and 12 appear to be generic to Device Embodiments II to XV. The Examiner conceded that claims 1 and 2 appear to be generic to all Device Embodiments I to XV and that claims 11 and 12 appear to be generic to Device Embodiments II to XV. Therefore, non-elected claims 11 and 12 will be examined on their merits.
However, the restriction requirement between Device Embodiments is still deemed proper and the Applicant’s election of Device Embodiment II is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4 December 2023 has been considered by the examiner and made of record in the application file.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING MULTIPLE SEMICONDUCTOR LAYERS WITH DIFFERENT INDIUM CONCENTRATIONS.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 7 is objected to because of the following informalities:
Amended Claim 7 states “… the second semiconductor layer is different an atomic ratio…”. For the purpose of examination the Examiner will interpret claim 7 to be “… the second semiconductor layer is different than an atomic ratio…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jun Tanaka et al. (US 2021/0013245 A1; hereinafter “Tanaka”).
Regarding Claim 1, Tanaka teaches a semiconductor device comprising:
a first transistor (170, Fig. 4, para [0087] describes an oxide semiconductor transistor 170); and
a second transistor (230, Fig. 4, para [0100] describes an oxide semiconductor transistor 230),
wherein the first transistor comprises a first semiconductor layer (173, Fig. 4 viewed inverted vertically, para [0081] describes an oxide semiconductor film layer 173), a first insulating layer over the first semiconductor layer (219, Fig. 4 viewed inverted vertically, para [0101] describes an insulating layer 219 that is over the first semiconductor layer 173 when viewing Fig. 4 inverted vertically), a second insulating layer over the first insulating layer (117, Fig. 4 viewed inverted vertically, para [0083] describes an insulating layer 117 that is over the first insulating layer 219 when viewing Fig. 4 inverted vertically), and a first gate electrode over the second insulating layer (171, Fig. 4 viewed inverted vertically, para [0087] describes a gate electrode 171 that is over the second insulating layer 117 when viewing Fig. 4 inverted vertically),
wherein the second transistor comprises a second semiconductor layer (133, Fig. 4 viewed inverted vertically, para [0081] describes an oxide semiconductor film layer 133), the second insulating layer over the second semiconductor layer (117, Fig. 4 viewed inverted vertically, para [0083] describes wherein insulating layer 117 is over the second semiconductor layer 133 when viewing Fig. 4 inverted vertically), and a second gate electrode over the second insulating layer (131, Fig. 4 viewed inverted vertically, para [0085] describes a gate electrode 131 that is over the second insulating layer 117 when viewing Fig. 4 inverted vertically),
wherein each of the first semiconductor layer and the second semiconductor layer comprises indium (133 and 173, Fig. 4 viewed inverted vertically, para [0082] describes wherein first semiconductor film 173 and second semiconductor film 133 may be comprised of indium), and
wherein an atomic ratio of the indium in the second semiconductor layer to metal elements in the second semiconductor layer (133, para [0082] describe wherein second semiconductor layer 133 may be comprised of an oxide semiconductor layer comprising indium such as IGZTO) is different from an atomic ratio of the indium in the first semiconductor layer to metal elements in the first semiconductor layer (173, para [0082] describe wherein first semiconductor layer 173 may be comprised of an oxide semiconductor layer comprising indium such as IGZO wherein IGZO would have a different atomic ratio of indium to metal elements than the atomic ratio of indium to metal elements in the second IGZTO semiconductor layer 133).
Regarding Claim 2, Tanaka teaches the semiconductor device according to claim 1, wherein the first insulating layer comprises a first region in contact with a top surface of the first semiconductor layer (FR, annotated Fig. 4 depicts wherein a first region FR of the first insulating layer 219 is in contact with a top surface of the first semiconductor layer 173) and a second region in contact with a bottom surface of the second semiconductor layer (SR, annotated Fig. 4 depicts wherein a second region SR of the first insulating layer 219 is in contact with a bottom surface of the second semiconductor layer 133).
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Regarding Claim 7, Tanaka teaches the semiconductor device according to claim 1,
wherein each of the first semiconductor layer and the second semiconductor layer comprises an element M (133 and 173, Fig. 4 viewed inverted vertically, para [0082] describes wherein first semiconductor film 173 and second semiconductor film 133 may be comprised of indium and at least one additional element such as gallium),
wherein the element M is one or more kinds selected from gallium, aluminum, yttrium, and tin (133 and 173, Fig. 4 viewed inverted vertically, para [0082] describes wherein first semiconductor film 173 and second semiconductor film 133 may be comprised of indium and at least one additional element such as gallium), and
wherein an atomic ratio of the element M in the second semiconductor layer to metal elements in the second semiconductor layer (133, para [0082] describe wherein second semiconductor layer 133 may be comprised of an oxide semiconductor layer comprising an element M including gallium such as IGZTO) is different an atomic ratio of the element M in the first semiconductor layer to metal elements in the first semiconductor layer (173, para [0082] describe wherein first semiconductor layer 173 may be comprised of an oxide semiconductor layer comprising an element M including gallium such as IGZO wherein IGZO would have a different atomic ratio of gallium to metal elements than the atomic ratio of gallium to metal elements in the second IGZTO semiconductor layer 133).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jun Tanaka et al. (US 2021/0013245 A1; hereinafter “Tanaka”) in view of Hiroyuki Miyake et al. (US 2017/0186778 A1; hereinafter “Miyake”).
Regarding Claim 3, Tanaka discloses all the limitations of claim 1.
Tanaka fails to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than the atomic ratio of the indium in the first semiconductor layer to the metal elements in the first semiconductor layer.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the second semiconductor layer (128, Fig. 1B, para [0125] describes an oxide semiconductor film 128 of a second transistor Tr2) to the metal elements in the second semiconductor layer (128, para [0131] describes wherein the second semiconductor layer 128 may comprise a region wherein the atomic proportion of indium is larger than the atomic proportion of metals) is higher than the atomic ratio of the indium in the first semiconductor layer (108, Fig. 1B, para [0124] describes an oxide semiconductor film 108 of a first transistor Tr1) to the metal elements in the first semiconductor layer (108 and 128, para [0130] describes wherein the compositions of the first oxide semiconductor film 108 and the second oxide semiconductor film 208 may be different from each other, wherein the first oxide semiconductor film 108 may comprise a region in which the atomic proportion of indium is lower than the atomic proportion of metals as describes in para [0129] and further wherein the resulting second semiconductor layer 128 would have a higher proportion of indium to metals than the first semiconductor layer 108).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Miyake to further disclose a semiconductor device wherein a second semiconductor layer may have a higher proportion of indium to metal elements than a first semiconductor layer in order to provide the advantage of providing for a second transistor which may have a higher proportion of indium than metal elements which provides the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]) and further providing for a first transistor which has a higher proportion of metal elements than indium which provides the advantage of producing a transistor with stable electrical characteristics due to the metal elements creating a lower chance of oxygen vacancy lowering undesirable and unpredictable results (Miyake, para [0240] and para [0243]).
Regarding Claim 4, Tanaka discloses all the limitations of claim 1.
Tanaka fails to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of indium to metal elements in a second semiconductor layer 128 may satisfy Indium > metal elements such as an atomic ratio of In:M:Zn=3:1:2 wherein a resulting atomic percentage of indium to the total metal elements is roughly 50% falling within the range of 30 atomic% to 100 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Miyake to further disclose a semiconductor device wherein a second semiconductor device may have an atomic percentage of indium to metal elements that is greater than or equal to 30% and less than or equal to 100% in order to provide the advantage of providing for a transistor which may have a higher proportion of indium than metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Regarding Claim 5, Tanaka discloses all the limitations of claim 1.
Tanaka fails to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the first semiconductor layer to metal elements in the first semiconductor layer is higher than the atomic ratio of the indium in the second semiconductor layer to the metal elements in the second semiconductor layer.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the first semiconductor layer (108, Fig. 1B, para [0124] describes an oxide semiconductor film 108 of a first transistor Tr1) to metal elements in the first semiconductor layer (108, para [0131] describes wherein the first semiconductor layer 108 may comprise a region wherein the atomic proportion of indium is larger than the atomic proportion of metals) is higher than the atomic ratio of the indium in the second semiconductor layer (128, Fig. 1B, para [0125] describes an oxide semiconductor film 128 of a second transistor Tr2) to the metal elements in the second semiconductor layer (108 and 128, para [0130] describes wherein the compositions of the first oxide semiconductor film 108 and the second oxide semiconductor film 208 may be different from each other, wherein the second oxide semiconductor film 128 may comprise a region in which the atomic proportion of indium is lower than the atomic proportion of metals as describes in para [0129] and further wherein the resulting first semiconductor layer 108 would have a higher proportion of indium to metals than the second semiconductor layer 128).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Miyake to further disclose a semiconductor device wherein a first semiconductor layer may have a higher proportion of indium to metal elements than a second semiconductor layer in order to provide the advantage of providing for a first transistor which may have a higher proportion of indium than metal elements which provides the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]) and further providing for a second transistor which has a higher proportion of metal elements than indium which provides the advantage of producing a transistor with stable electrical characteristics due to the metal elements creating a lower chance of oxygen vacancy lowering undesirable and unpredictable results (Miyake, para [0240] and para [0243]).
Regarding Claim 6, Tanaka discloses all the limitations of claim 1.
Tanaka fails to explicitly disclose the semiconductor device according to claim 1, wherein the atomic ratio of the indium in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the indium in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 30 atomic% and lower than or equal to 100 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of indium to metal elements in a first semiconductor layer 108 may satisfy the inequality indium > metal elements such as an atomic ratio of In:M:Zn=3:1:2 wherein a resulting atomic percentage of indium to the total metal elements is roughly 50% falling within the range of 30 atomic% to 100 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Miyake to further disclose a semiconductor device wherein a first semiconductor device may have an atomic percentage of indium to metal elements that is greater than or equal to 30% and less than or equal to 100% in order to provide the advantage of providing for a transistor which may have a higher proportion of indium than metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Regarding Claim 8, Tanaka discloses all the limitations of claim 7.
Tanaka fails to explicitly disclose the semiconductor device according to claim 7, wherein the atomic ratio of the element M in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the element M in the second semiconductor layer to the metal elements in the second semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of the element M, such as gallium, in a second semiconductor layer 128 may satisfy the atomic ratio of In:M:Zn=1:1:1 wherein a resulting atomic percentage of M in the second semiconductor layer 128 to the total metal elements is roughly 33% falling within the range of 20 atomic% to 60 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Miyake to further disclose a semiconductor device wherein a second semiconductor device may have an atomic percentage of an element M to metal elements that is greater than or equal to 20% and less than or equal to 60% in order to provide the advantage of providing for a transistor which may have a higher than or equal proportion of indium to an element M and other metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Regarding Claim 10, Tanaka discloses all the limitations of claim 7.
Tanaka fails to explicitly disclose the semiconductor device according to claim 7, wherein the atomic ratio of the element M in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic%.
However, Miyake teaches a similar semiconductor device, wherein the atomic ratio of the element M in the first semiconductor layer to the metal elements in the first semiconductor layer is higher than or equal to 20 atomic% and lower than or equal to 60 atomic% (para [0195] and para [0196] describes wherein an atomic ratio of the element M, such as gallium, in a first semiconductor layer 108 may satisfy the atomic ratio of In:M:Zn=1:1:1 wherein a resulting atomic percentage of M in the first semiconductor layer 108 to the total metal elements is roughly 33% falling within the range of 20 atomic% to 60 atomic%).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Miyake to further disclose a semiconductor device wherein a first semiconductor device may have an atomic percentage of an element M to metal elements that is greater than or equal to 20% and less than or equal to 60% in order to provide the advantage of providing for a transistor which may have a higher than or equal proportion of indium to an element M and other metal elements further providing the advantage of producing a transistor with a high field-effect mobility which may increase the display quality in a display device (Miyake, para [0131] and para [0132]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jun Tanaka et al. (US 2021/0013245 A1; hereinafter “Tanaka”) in view of Shinpei Matsuda et al. (US 2017/0236842 A1; hereinafter “Matsuda”).
Regarding Claim 11, Tanaka discloses all the limitations of claim 1.
Tanaka fails to explicitly disclose the semiconductor device according to claim 1, wherein the first transistor further comprises a third insulating layer and a third gate electrode, wherein the third gate electrode comprises a region overlapping with the first gate electrode with the first semiconductor layer therebetween, and wherein the third gate electrode comprises a region overlapping with the first semiconductor layer with the third insulating layer therebetween.
However, Matsuda teaches a similar semiconductor device, wherein the first transistor (100, Fig. 1A, para [0107] describes a transistor 100) further comprises a third insulating layer (106, Fig. 6E and Fig. 1A, para [0113] describes an insulating layer 106) and a third gate electrode (105_1, Fig. 6D and Fig. 1A, para [0113] and para [0123] describes an electrode 105_1 that may be a gate electrode),
wherein the third gate electrode comprises a region overlapping with the first gate electrode with the first semiconductor layer therebetween (105_1, 112_1 and 109_1b, Fig. 13C, Fig. 14C and Fig. 1A, para [0121]-para [0123] describes a first gate electrode 112_1 which overlaps with the third gate electrode 105_1 and a first semiconductor layer 109_1b therebetween as shown in Fig. 13C, Fig. 14C and Fig. 1A wherein Fig. 1A is the final device of the methods involved in Fig. 13C and Fig. 14C), and
wherein the third gate electrode comprises a region overlapping with the first semiconductor layer with the third insulating layer therebetween (105_1, 106 and 109_1b, Fig. 6E, Fig. 14C and Fig. 1A, para [0121] - para [0123] wherein Fig. 1A depicts the third gate electrode 105_1 overlapping with the first semiconductor layer 109_1b and the third insulating layer 106 therebetween).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Matsuda to further disclose a semiconductor device that further comprises a third gate electrode and a third insulating layer in order to provide the advantage of increasing the on-state current and field-effect mobility of the transistor device further improving device integration (Matsuda, para [0126] and para [0127]).
Regarding Claim 12, the combination of Tanaka and Matsuda disclose all the limitations of claim 11.
Tanaka fails to explicitly disclose the semiconductor device of claim 11, wherein the second transistor further comprises the first insulating layer, the third insulating layer, and a fourth gate electrode, wherein the fourth gate electrode comprises a region overlapping with the second gate electrode with the second semiconductor layer therebetween, and wherein the fourth gate electrode comprises a region overlapping with the second semiconductor layer with the first insulating layer and the third insulating layer therebetween.
However, Matsuda teaches a similar semiconductor device, wherein the second transistor (200, Fig. 1A, para [0107] describes a second transistor 200) further comprises the first insulating layer (107, Fig. 2B and Fig. 1A, para [0113] describes an insulating layer 107), the third insulating layer (106, Fig. 2B and Fig. 1A, para [0113] describes the third insulating layer 106), and a fourth gate electrode (105_2, Fig. 1A and Fig. 9C, para [0134] describes an electrode 105_2),
wherein the fourth gate electrode comprises a region overlapping with the second gate electrode (112_2 and 105_2, Fig. 13B, para [0134] wherein Fig. 1A depicts the fourth gate electrode 105_2 and a second gate electrode 112_2 are overlapping) with the second semiconductor layer therebetween (109_2b1 and 109_2b2, Fig. 8C and Fig. 1A, para [0134] describes a second semiconductor layer 109_2b1 and 109_2b2 between second gate electrode 112_2 and fourth gate electrode 105_2), and
wherein the fourth gate electrode comprises a region overlapping with the second semiconductor layer (Fig. 8C and Fig. 1A, depicts wherein second semiconductor layer 109_2b1 and 109_2b2 comprises a region overlapping with the fourth gate electrode 105_2) with the first insulating layer and the third insulating layer therebetween (Fig. 1A and Fig. 2B depict wherein the first insulating layer 107 and second insulating layer 106 is between the second semiconductor layer 109_2b1 and 109_2b2 and the fourth gate electrode 105_2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanaka with Matsuda to further disclose a semiconductor device that further comprises a fourth gate electrode and a fourth insulating layer in order to provide the advantage of increasing the on-state current and field-effect mobility of the transistor device further improving device integration (Matsuda, para [0126] and para [0127]).
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898