Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/10/2024 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2013-138177 A and further in view of JP 2013-211091 A.
JP 2013-138177 A (ELPIDA MEMORY INC.) 11 July 2013 (2013-07-11), paragraphs [0015]-[0124], fig. 1-17 teaches:
a semiconductor device (corresponding to the semiconductor device of the present invention (correspondences indicated similarly below)) which has a logic element (first peripheral circuit) formed on a logic semiconductor chip 113 (first substrate), and first and second semiconductor chips 35-39 which are memory semiconductor chips mounted in a perpendicular direction on the logical semiconductor chip 113, the second semiconductor chips 35-39 including a semiconductor substrate 47 (second substrate) and
a circuit element layer 48 (first circuit layer), a DRAM element (first memory cell) being provided on the circuit element layer 48, and the logical semiconductor chip 113 and the first and second semiconductor chips 35-39 being electrically connected by means of a through electrode 54 (first through electrode).
JP 2013-138177 A fails to teach:
a structure having a first transistor and a first capacitor, the first transistor having a semiconductor layer having a metal oxide in a channel forming region, whereas the cited invention does not include a description of this kind.
JP 2013-211091 A (SEMICONDUCTOR ENERGY LABORATORY CO., LTD.) 10 October 2013 (2013-10-10) paragraphs [0158], [0159] teaches: for example, using a transistor and a capacitor as a structure for forming a memory cell and further describes using a transistor having an oxide semiconductor (a transistor having a semiconductor layer having a metal oxide in the channel forming region).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because it is conventionally done in the art because the transistor of a memory cell that enables power consumption to be reduced.
In regards to claim 3;
JP 2013-138177 A teaches wherein the first memory cell layer comprises a plurality of the first element layers provided to be stacked in a direction perpendicular or substantially perpendicular to the surface of the first substrate. paragraphs [0015]-[0124], fig. 1-17
In regards to Claim 7, JP 2013-211091 A further teaches (paragraphs [0158] and [0159]) describes using an In-Ga-Zn-O material for the oxide semiconductor layer.
Claim(s) 2, 8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2013-138177 A and JP 2013-211091 A and in further view of JP 2019-61677 A.
JP 2013-138177 A (ELPIDA MEMORY INC.) 11 July 2013 (2013-07-11), paragraphs [0015]-[0124], fig. 1-17 & US 2013/0137216 A1, paragraphs [0025]-[0220], fig. 1-17 teaches:
a semiconductor device (corresponding to the semiconductor device of the present
invention (correspondences indicated similarly below)) which has a logic element (first peripheral circuit)
formed on a logic semiconductor chip 113 (first substrate), and first and second semiconductor chips 35-39 which are memory semiconductor chips mounted in a perpendicular direction on the logical semiconductor chip 113, the second semiconductor chips 35-39 including a semiconductor substrate 47 (second substrate) and
a circuit element layer 48 (first circuit layer), a DRAM element (first memory cell) being provided on the circuit element layer 48, and the logical semiconductor chip 113 and the first and second semiconductor chips 35-39 being electrically connected by means of a through electrode 54 (first through electrode).
JP 2013-138177 A fails to teach:
a structure having a first transistor and a first capacitor, the first transistor having a semiconductor layer having a metal oxide in a channel forming region, whereas the cited invention does not include a description of this kind.
JP 2013-211091 A (SEMICONDUCTOR ENERGY LABORATORY CO., LTD.) 10 October 2013 (2013-10-10) paragraphs [0158], [0159] teaches: for example, using a transistor and a capacitor as a structure for forming a memory cell and further describes using a transistor having an oxide semiconductor (a transistor having a semiconductor layer having a metal oxide in the channel forming region).
JP 2019-61677 A (SAMSUNG ELECTRONICS CO., LTD.) 18 April 2019 (2019-04-18), paragraphs [0012]-[0045], fig. 1-6 describes first to fourth memory semiconductor dies 1100-1400 (second substrate) which are stacked, wherein read-out data is output after being amplified relative to the output of a memory cell.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because processing efficiency and power consumption can be optimized when the external device requests multiple accesses to the stacked memory device.
In regards to claim 8;
JP 2013-138177 A teaches wherein the first memory cell layer comprises a plurality of the first element layers provided to be stacked in a direction perpendicular or substantially perpendicular to the surface of the first substrate. paragraphs [0015]-[0124], fig. 1-17
In regards to Claim 12, JP 2013-211091 A further teaches (paragraphs [0158] and [0159]) describes using an In-Ga-Zn-O material for the oxide semiconductor layer.
Allowable Subject Matter
Claims 4-6 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art references fail to teach:
the first substrate provided with a second peripheral circuit configured to drive a second memory cell; and a third substrate provided with a second memory cell layer comprising a second element layer comprising the second memory cell, wherein the first memory cell layer is provided between the first substrate and the second memory cell layer, wherein the second memory cell comprises a second transistor and a second capacitor, wherein the second transistor comprises a semiconductor layer comprising silicon in its channel formation region, and wherein the second peripheral circuit and the second memory cell are electrically connected to each other through a second through electrode provided in the second substrate, the third substrate, the first element layer, and the second element layer
And:
the first substrate provided with a second peripheral circuit configured to drive a second memory cell; and a second memory cell layer comprising a third substrate and a second element layer comprising the second memory cell, wherein the first memory cell layer is provided between the first substrate and the second memory cell layer, wherein the second memory cell comprises a third transistor to a fifth transistor and a third capacitor, wherein the third transistor to the fifth transistor comprise semiconductor layers comprising a metal oxide in their channel formation regions, and wherein the second peripheral circuit and the second memory cell are electrically connected to each other through a second through electrode provided in the second substrate, the third substrate, the first element layer, and the second element layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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