DETAILED ACTION
This correspondence is in response to the communications received February 17, 2026. Claims 1-8 and 14-23 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 9-13 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II method claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 17, 2026.
Relevant Prior Art
Koike et al. (US 2008/0278649) Fig. 13, shown below. Where 46 is an oxide layer, ¶ 0127.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 3B, a semiconductor device comprising:
an oxide semiconductor layer (18) over a substrate (11);
a source electrode (12a) and a drain electrode (12b) being apart from each other over the oxide semiconductor layer (18);
a mask layer (19, metals shown in ¶ 0074, dielectrics shown in ¶ 0075, metal oxides shown in ¶ 0077) in contact with a top surface of one of the source electrode and the drain electrode (12a);
a first insulating layer (16) covering the oxide semiconductor layer (11), the source electrode (12a), the drain electrode (12b), and the mask layer (19); and
a gate electrode (20) being over the first insulating layer (over 16) and overlapping with the oxide semiconductor layer (20 overlaps 11),
wherein the first insulating layer (16) is in contact with a top surface and a side surface of the mask layer (19), a side surface of the one of the source electrode and the drain electrode (side of 12a), a top surface and a side surface of the other of the source electrode and the drain electrode (top and side surface of 12b), and a top surface of the oxide semiconductor layer (top of 18), and
wherein the semiconductor device comprises a region in which a distance between opposite end portions of the source electrode and the drain electrode is less than or equal to 1 micron (¶ 0081).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6, 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Le et al. (US 2019/0393356).
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Regarding claim 1, the prior art of Seon discloses in Fig. 7, a semiconductor device (¶ 0006) comprising:
an oxide semiconductor layer (C3, which is analogous to C2 as described in ¶ 0129, where C2 is shown to be an oxide semiconductor in ¶ 0121) over a substrate (SUB3);
a source electrode (S3, ¶ 0128) and a drain electrode (D3, ¶ 0128) being apart from each other over the oxide semiconductor layer (S3 and D3 show spaced apart from each other);
a first insulating layer (“gate insulating layer GI3”, ¶ 0128) covering the oxide semiconductor layer (covering C3), the source electrode (covering S3), the drain electrode (covering D3); and
a gate electrode (“gate electrode G3”, ¶ 0127) being over the first insulating layer (over GI3) and overlapping with the oxide semiconductor layer (G3 overlaps with C3),
wherein the first insulating layer (GI3) is in contact with a side surface of the one of the source electrode and the drain electrode (GI3 is in contact with side surfaces of both S3 and D3), a top surface and a side surface of the other of the source electrode and the drain electrode (GI3 is in contact with top surfaces of both S3 and D3), and a top surface of the oxide semiconductor layer (GI3 is in contact with C3).
First, Seon does not disclose,
“a mask layer in contact with a top surface of one of the source electrode and the drain electrode;
a first insulating layer covering the oxide semiconductor layer, the source electrode, the drain electrode, and the mask layer; and” (italicized portion)
…
“wherein the first insulating layer is in contact with a top surface and a side surface of the mask layer”.
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Yamazaki discloses in Fig. 5A,
a mask layer (404a, 404b, “metal oxide regions 404a and 404b are formed between the source electrode layer 405a and the oxide insulating layer 407 and between the drain electrode layer 405b and the oxide insulating layer 407 respectively in some cases. The metal oxide regions 404a and 404b may be in the form of a film in some cases.”, ¶ 0170) in contact with a top surface of one of the source electrode (top of “source electrode layer 405a”, ¶ 0170) and the drain electrode (top of “drain electrode layer 405b”, ¶ 0170);
a first insulating layer (“oxide insulating layer 407”, ¶ 0170) covering the oxide semiconductor layer (covering analogous “oxide semiconductor layer 403”, ¶ 0170), the source electrode (covering 405a), the drain electrode (covering 405b), and the mask layer (covering 405a and 405b); and”
…
wherein the first insulating layer (407) is in contact with a top surface and a side surface of the mask layer (407 is in contact with top and side surfaces of the mask layer 404a, 404b).
After the combination of Yamazaki’s mask layers (404a, 404b) to cover Seon’s source and drains (S3 and D3), then the limitation of, “wherein the first insulating layer is in contact with … a top surface and a side surface of the other of the source electrode and the drain electrode (Seon’s GI3 will be in “indirect” contact with top surfaces of both S3 and D3), and a top surface of the oxide semiconductor layer (Seon’s GI3 will be in contact with combined layer of Yamazaki’s mask layers 404a, 404b)”, are then satisfied.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a mask layer in contact with a top surface of one of the source electrode and the drain electrode;
a first insulating layer covering … the mask layer”
…
“wherein the first insulating layer is in contact with a top surface and a side surface of the mask layer”, as disclosed by Yamazaki in the system of Seon, for the purpose of protecting the source and drain electrodes during the subsequent manufacturing steps and particularly during the formation of the covering oxide insulating layer. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Seon fails to disclose,
“wherein the semiconductor device comprises a region in which a distance between opposite end portions of the source electrode and the drain electrode is less than or equal to 1 micron”.
Le discloses in paragraph 0039, “In embodiments, the source electrode 103, the drain electrode 105, the gate electrode 107, the gate electrode 109, may have a width equal to a minimal feature width for the TFT 100, e.g., around 10 nanometers (nms) in width or 10 nms in length. In some embodiments, the source electrode 103, the drain electrode 105, the gate electrode 107, the gate electrode 109 may have a length of about 100 nms.” In both potential interpretations of this teaching, either 1.) the entirety of elements of source, drain, channel, gate total to 10 or 100 nanometers, or 2.) each feature are 10-100 nanometers each, which would be 3x the largest dimension (source plus channel/gate plus drain dimensions laterally aligned down the transistor/channel length) would equal at most 300 nm. Both instances would fall well below the one micron requirement.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the semiconductor device comprises a region in which a distance between opposite end portions of the source electrode and the drain electrode is less than or equal to 1 micron”, as disclosed by Le in the system of Seon, for the purpose of creating devices which can provide increasingly diminutive dimensions to increase device functionality and display resolution. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, Seon et al. disclose the semiconductor device according to claim 1, and Seon shows a top gate only variant in Fig. 7, which clearly does not disclose,
“further comprising:
a second gate electrode; and
a second insulating layer,
wherein the second gate electrode is provided between the oxide semiconductor layer and the substrate, and
wherein the second insulating layer is provided between the oxide semiconductor layer and the second gate electrode.”
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The same reference Seon, discloses in Fig. 22,
further comprising:
a second gate electrode (G6, ¶ 0164); and
a second insulating layer (GI6, ¶ 0164),
wherein the second gate electrode (G6, ¶ 0164) is provided between the oxide semiconductor layer (C6, ¶ 0164) and the substrate (SUB6), and
wherein the second insulating layer (GI6) is provided between the oxide semiconductor layer (C6) and the second gate electrode (G6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising:
a second gate electrode; and
a second insulating layer,
wherein the second gate electrode is provided between the oxide semiconductor layer and the substrate, and
wherein the second insulating layer is provided between the oxide semiconductor layer and the second gate electrode”, as disclosed by Fig. 22 of Seon in the system of Seon’s Fig. 6, for the purpose of adding further control functionality to the thin film transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 4, Seon et al. disclose the semiconductor device according to claim 1, and Yamazaki discloses in Fig. 5A, wherein the mask layer comprises a metal oxide (404a, 404b, “metal oxide regions 404a and 404b”, ¶ 0170), and wherein the source electrode and the drain electrode comprise a metal (405a, 405b are metal, ¶ 0174).
Regarding claim 6, Seon et al. disclose the semiconductor device according to claim 4, and Yamazaki discloses, wherein the metal comprises tungsten (405a, 405b are tungsten, ¶ 0174).
Regarding claim 7, Seon et al. disclose display apparatus comprising the semiconductor device according to claim 1 (Seon discloses a display, ¶ 0025).
Regarding claim 14, Seon et al. disclose display apparatus comprising the semiconductor device according to claim 1, however Seon does not explicitly disclose the particular material for the oxide semiconductor as, “wherein the oxide semiconductor layer comprises at least one of indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zinc.”
Yamazaki discloses in ¶ 0153, where “the oxide semiconductor layer 403 … such as an In—Ga—Zn—O-based oxide semiconductor” (among others).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the oxide semiconductor layer comprises at least one of indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zinc”, as disclosed Yamazaki in the system of Seon, for the purpose of utilizing materials which have improved switching signal performance properties. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Le et al. (US 2019/0393356) in view of Hosaka et al. (US 2018/0350994).
Regarding claim 3, Seon et al. disclose the semiconductor device according to claim 2, however Seon does not disclose, “wherein an opening is formed in the first insulating layer and the second insulating layer, and wherein the first gate electrode is in contact with the second gate electrode through the opening.”
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Hosaka discloses in Fig. 1B and 1C, wherein an opening is formed in the first insulating layer (110, ¶ 0119) and the second insulating layer (104, ¶ 0119), and wherein the first gate electrode (114, ¶ 0119) is in contact with the second gate electrode (106, ¶ 0119) through the opening (143).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein an opening is formed in the first insulating layer and the second insulating layer, and wherein the first gate electrode is in contact with the second gate electrode through the opening”, as disclosed Hosaka in the system of Seon, for the purpose of increasing the field effect on the channel for better control of the switching function of the thin film transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Le et al. (US 2019/0393356) in view of Cheng et al. (US 2017/0045791).
Regarding claim 5, Seon et al. disclose the semiconductor device according to claim 4, however Seon does not disclose, “wherein the metal oxide comprises indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zinc.” It is noted that Yamazaki shows the use of , “the conductive film to be the source electrode layer and the drain electrode layer may be formed using a conductive metal oxide. As conductive metal oxide, indium oxide (In.sub.2O.sub.3), tin oxide (SnO.sub.2), zinc oxide (ZnO), indium oxide-tin oxide alloy (In.sub.2O.sub.3—SnO.sub.2, which is abbreviated to ITO), indium oxide-zinc oxide alloy (In.sub.2O.sub.3—ZnO)”, ¶ 0069.
Cheng discloses in ¶ 0077, “The material of the transparent conductive metal oxide film is … IGZO (indium gallium zinc oxide)”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the metal oxide comprises indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zin”, as disclosed Cheng in the system of Seon, for the purpose of utilizing transparent conductors which are useful in a display setting as they are less likely to contribute to unwanted internal reflections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Le et al. (US 2019/0393356) in view of Cha et al. (US 2021/0158751) in view of Wang et al. (US 2021/0202644).
Regarding claim 8, Seon et al. disclose the semiconductor device according to claim 7, however Seon does not disclose,
“further comprising:
a first pixel; and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer,
wherein the second pixel comprises a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer, and
wherein the display apparatus comprises a region in which a distance between the first pixel electrode and the second pixel electrode is less than or equal to 8 micrometers.”
First, Seo does not disclose,
“further comprising:
a first pixel; and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer,
wherein the second pixel comprises a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer”.
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Cha discloses in Figs. 10 and 13, further comprising:
a first pixel (PX11, ¶ 0155, which is a red pixel); and
a second pixel (PX21, ¶ 0155, which is a green pixel) adjacent to the first pixel (diagonally adjacent),
wherein the first pixel (PX11 which is equivalent to PXA in Fig. 13) comprises a first pixel electrode (AE), a first EL layer (EML) over the first pixel electrode (on AE), and a common electrode (CE) over the first EL layer (over EML),
wherein the second pixel (PX21 which is equivalent to PXA in Fig. 13) comprises a second pixel electrode (AE), a second EL layer (EML) over the second pixel electrode (over AE), and the common electrode (CE) over the second EL layer (over EML).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising:
a first pixel; and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer,
wherein the second pixel comprises a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer”, as disclosed Cha in the system of Seon, for the purpose of providing full color information functionality to the display device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Seo does not disclose, “wherein the display apparatus comprises a region in which a distance between the first pixel electrode and the second pixel electrode is less than or equal to 8 micrometers”.
Wang discloses in ¶ 0043, “the pixel size is usually about 5 micrometers (um), and the distance between the pixels is about 1 um or less”, and discloses that this arrangement is for usage in OLED format, ¶ 0085.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the display apparatus comprises a region in which a distance between the first pixel electrode and the second pixel electrode is less than or equal to 8 micrometers”, as disclosed Wang in the system of Seon, for the purpose of creating devices which can provide increasingly diminutive dimensions to increase device functionality and display resolution. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 15, 16, 18, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Choi et al. (US 2005/0255257) in view of Le et al. (US 2019/0393356).
Regarding claim 15, the prior art of Seon discloses in Fig. 7, a semiconductor device (¶ 0006) comprising:
an oxide semiconductor layer (C3, which is analogous to C2 as described in ¶ 0129, where C2 is shown to be an oxide semiconductor in ¶ 0121) over a substrate (SUB3);
a source electrode (S3, ¶ 0128) and a drain electrode (D3, ¶ 0128) being apart from each other over the oxide semiconductor layer (S3 and D3 show spaced apart from each other);
a first insulating layer (“gate insulating layer GI3”, ¶ 0128) covering the oxide semiconductor layer (covering C3), the source electrode (covering S3), the drain electrode (covering D3); and
a first gate electrode (“gate electrode G3”, ¶ 0127) being over the first insulating layer (over GI3) and overlapping with the oxide semiconductor layer (G3 overlaps with C3),
wherein the first insulating layer (GI3) is in contact with a side surface of the one of the source electrode and the drain electrode (GI3 is in contact with side surfaces of both S3 and D3), a top surface and a side surface of the other of the source electrode and the drain electrode (GI3 is in contact with top surfaces of both S3 and D3), and a top surface of the oxide semiconductor layer (GI3 is in contact with C3).
First, Seon does not disclose,
“a mask layer in contact with a top surface of one of the source electrode and the drain electrode;
a first insulating layer covering … the mask layer; and”
…
“wherein the first insulating layer is in contact with a top surface and a side surface of the mask layer”.
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Yamazaki discloses in Fig. 5A,
a mask layer (404a, 404b, “metal oxide regions 404a and 404b are formed between the source electrode layer 405a and the oxide insulating layer 407 and between the drain electrode layer 405b and the oxide insulating layer 407 respectively in some cases. The metal oxide regions 404a and 404b may be in the form of a film in some cases.”, ¶ 0170) in contact with a top surface of one of the source electrode (top of “source electrode layer 405a”, ¶ 0170) and the drain electrode (top of “drain electrode layer 405b”, ¶ 0170);
a first insulating layer (“oxide insulating layer 407”, ¶ 0170) covering the oxide semiconductor layer (covering analogous “oxide semiconductor layer 403”, ¶ 0170), the source electrode (covering 405a), the drain electrode (covering 405b), and the mask layer (covering 405a and 405b); and”
…
wherein the first insulating layer (407) is in contact with a top surface and a side surface of the mask layer (407 is in contact with top and side surfaces of the mask layer 404a, 404b).
After the combination of Yamazaki’s mask layers (404a, 404b) to cover Seon’s source and drains (S3 and D3), then the limitation of, “wherein the first insulating layer is in contact with a top surface and a side surface of the mask layer (Seon’s GI3 will be in contact with the combined in mask layer 404a, 404b, since the mask will be on top of the source drain regions 405a, 405b analogous to Seon’s S3 and D3)”, will be satisfied.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a mask layer in contact with a top surface of one of the source electrode and the drain electrode;
a first insulating layer covering the oxide semiconductor layer, the source electrode, the drain electrode, and the mask layer; and” (italicized portion)
…
“wherein the first insulating layer is in contact with a top surface and a side surface of the mask layer”, as disclosed by Yamazaki in the system of Seon, for the purpose of protecting the source and drain electrodes during the subsequent manufacturing steps and particularly during the formation of the covering oxide insulating layer. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Seon does not disclose, “wherein in the oxide semiconductor layer, a thickness of a first region that overlaps with neither the source electrode nor the drain electrode is smaller than a thickness of a second region that overlaps with the other of the source electrode and the drain electrode.”
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Choi discloses in Fig. 4B,
wherein in the oxide semiconductor layer (404 being the equivalent to the “oxide semiconductor layer”), a thickness of a first region that overlaps with neither the source electrode nor the drain electrode is smaller than a thickness of a second region that overlaps with the other of the source electrode and the drain electrode (the central region of 404 is thinner than the region overlapping the source drain regions 405).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein in the oxide semiconductor layer, a thickness of a first region that overlaps with neither the source electrode nor the drain electrode is smaller than a thickness of a second region that overlaps with the other of the source electrode and the drain electrode”, as disclosed by Choi in the system of Seon, for the purpose of over etching the channel to improve charge transfer sensitivity and performance. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Seon does not disclose, “wherein a length of the first region of the oxide semiconductor layer is less than or equal to 1 µm.”
Le discloses in paragraph 0039, “In embodiments, the source electrode 103, the drain electrode 105, the gate electrode 107, the gate electrode 109, may have a width equal to a minimal feature width for the TFT 100, e.g., around 10 nanometers (nms) in width or 10 nms in length. In some embodiments, the source electrode 103, the drain electrode 105, the gate electrode 107, the gate electrode 109 may have a length of about 100 nms.” In both potential interpretations of this teaching, either 1.) the entirety of elements of source, drain, channel, gate total to 10 or 100 nanometers, or 2.) each feature are 10-100 nanometers each, which would have the channel/oxide semiconductor layer is between 10-100 nm. Both instances would fall well below the one micron requirement.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein a length of the first region of the oxide semiconductor layer is less than or equal to 1 µm”, as disclosed by Le in the system of Seon, for the purpose of creating devices which can provide increasingly diminutive dimensions to increase device functionality and display resolution. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 16, Seon et al. disclose the semiconductor device according to claim 15, and Seon shows a top gate only variant in Fig. 7, which clearly does not disclose,
“further comprising:
a second gate electrode; and
a second insulating layer,
wherein the second gate electrode is provided between the oxide semiconductor layer and the substrate, and
wherein the second insulating layer is provided between the oxide semiconductor layer and the second gate electrode.”
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The same reference Seon, discloses in Fig. 22,
further comprising:
a second gate electrode (G6, ¶ 0164); and
a second insulating layer (GI6, ¶ 0164),
wherein the second gate electrode (G6, ¶ 0164) is provided between the oxide semiconductor layer (C6, ¶ 0164) and the substrate (SUB6), and
wherein the second insulating layer (GI6) is provided between the oxide semiconductor layer (C6) and the second gate electrode (G6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising:
a second gate electrode; and
a second insulating layer,
wherein the second gate electrode is provided between the oxide semiconductor layer and the substrate, and
wherein the second insulating layer is provided between the oxide semiconductor layer and the second gate electrode”, as disclosed by Fig. 22 of Seon in the system of Seon’s Fig. 6, for the purpose of adding further control functionality to the thin film transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 18, Seon et al. disclose the semiconductor device according to claim 15, and Yamazaki discloses in Fig. 5A, wherein the mask layer comprises a metal oxide (404a, 404b, “metal oxide regions 404a and 404b”, ¶ 0170), and wherein the source electrode and the drain electrode comprise a metal (405a, 405b are metal, ¶ 0174).
Regarding claim 20, Seon et al. disclose the semiconductor device according to claim 18, and Yamazaki discloses, wherein the metal comprises tungsten (405a, 405b are tungsten, ¶ 0174).
Regarding claim 21, Seon et al. disclose display apparatus comprising the semiconductor device according to claim 15, however Seon does not explicitly disclose the particular material for the oxide semiconductor as, “wherein the oxide semiconductor layer comprises at least one of indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zinc.”
Yamazaki discloses in ¶ 0153, where “the oxide semiconductor layer 403 … such as an In—Ga—Zn—O-based oxide semiconductor” (among others).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the oxide semiconductor layer comprises at least one of indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zinc”, as disclosed Yamazaki in the system of Seon, for the purpose of utilizing materials which have improved switching signal performance properties. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 22, Seon et al. disclose display apparatus comprising the semiconductor device according to claim 15 (Seon discloses a display, ¶ 0025).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Choi et al. (US 2005/0255257) in view of Le et al. (US 2019/0393356) in view of Hosaka et al. (US 2018/0350994).
Regarding claim 17, Seon et al. disclose the semiconductor device according to claim 16, however Seon does not disclose, “wherein an opening is formed in the first insulating layer and the second insulating layer, and wherein the first gate electrode is in contact with the second gate electrode through the opening.”
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Hosaka discloses in Fig. 1B and 1C, wherein an opening is formed in the first insulating layer (110, ¶ 0119) and the second insulating layer (104, ¶ 0119), and wherein the first gate electrode (114, ¶ 0119) is in contact with the second gate electrode (106, ¶ 0119) through the opening (143).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein an opening is formed in the first insulating layer and the second insulating layer, and wherein the first gate electrode is in contact with the second gate electrode through the opening”, as disclosed Hosaka in the system of Seon, for the purpose of increasing the field effect on the channel for better control of the switching function of the thin film transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Choi et al. (US 2005/0255257) in view of Le et al. (US 2019/0393356) in view of Cheng et al. (US 2017/0045791).
Regarding claim 19, Seon et al. disclose the semiconductor device according to claim 18, however Seon does not disclose, “wherein the metal oxide comprises indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zinc.” It is noted that Yamazaki shows the use of , “the conductive film to be the source electrode layer and the drain electrode layer may be formed using a conductive metal oxide. As conductive metal oxide, indium oxide (In.sub.2O.sub.3), tin oxide (SnO.sub.2), zinc oxide (ZnO), indium oxide-tin oxide alloy (In.sub.2O.sub.3—SnO.sub.2, which is abbreviated to ITO), indium oxide-zinc oxide alloy (In.sub.2O.sub.3—ZnO)”, ¶ 0069.
Cheng discloses in ¶ 0077, “The material of the transparent conductive metal oxide film is … IGZO (indium gallium zinc oxide)”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the metal oxide comprises indium, an element M (the element M is one or more selected from gallium, aluminum, and yttrium), and zin”, as disclosed Cheng in the system of Seon, for the purpose of utilizing transparent conductors which are useful in a display setting as they are less likely to contribute to unwanted internal reflections. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Seon et al. (US 2015/0280000) in view of Yamazaki et al. (US 2021/0313193) in view of Choi et al. (US 2005/0255257) in view of Le et al. (US 2019/0393356) in view of Cha et al. (US 2021/0158751) in view of Wang et al. (US 2021/0202644).
Regarding claim 23, Seon et al. disclose the semiconductor device according to claim 22, however Seon does not disclose,
“further comprising:
a first pixel; and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer,
wherein the second pixel comprises a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer, and
wherein the display apparatus comprises a region in which a distance between the first pixel electrode and the second pixel electrode is less than or equal to 8 micrometers.”
First, Seo does not disclose,
“further comprising:
a first pixel; and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer,
wherein the second pixel comprises a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer”.
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480
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476
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Cha discloses in Figs. 10 and 13, further comprising:
a first pixel (PX11, ¶ 0155, which is a red pixel); and
a second pixel (PX21, ¶ 0155, which is a green pixel) adjacent to the first pixel (diagonally adjacent),
wherein the first pixel (PX11 which is equivalent to PXA in Fig. 13) comprises a first pixel electrode (AE), a first EL layer (EML) over the first pixel electrode (on AE), and a common electrode (CE) over the first EL layer (over EML),
wherein the second pixel (PX21 which is equivalent to PXA in Fig. 13) comprises a second pixel electrode (AE), a second EL layer (EML) over the second pixel electrode (over AE), and the common electrode (CE) over the second EL layer (over EML).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising:
a first pixel; and
a second pixel adjacent to the first pixel,
wherein the first pixel comprises a first pixel electrode, a first EL layer over the first pixel electrode, and a common electrode over the first EL layer,
wherein the second pixel comprises a second pixel electrode, a second EL layer over the second pixel electrode, and the common electrode over the second EL layer”, as disclosed Cha in the system of Seon, for the purpose of providing full color information functionality to the display device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Seo does not disclose, “wherein the display apparatus comprises a region in which a distance between the first pixel electrode and the second pixel electrode is less than or equal to 8 micrometers”.
Wang discloses in ¶ 0043, “the pixel size is usually about 5 micrometers (um), and the distance between the pixels is about 1 um or less”, and discloses that this arrangement is for usage in OLED format, ¶ 0085.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the display apparatus comprises a region in which a distance between the first pixel electrode and the second pixel electrode is less than or equal to 8 micrometers”, as disclosed Wang in the system of Seon, for the purpose of creating devices which can provide increasingly diminutive dimensions to increase device functionality and display resolution. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893