DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-6 & 10-18 in the reply filed on 05/28/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 & 10-18 are2 rejected under 35 U.S.C. 103 as being unpatentable over Katti (US Patent 10,762,942) in view of YAN et al. (US Pub. 2023/0309411) and SUN (CN 112259139).
Regarding claim 1, Katti teaches an SOT-MRAM memory cell (Fig. 1-5 and associated text), comprising:
a bottom electrode 112 (Fig. 1);
a magnetic tunnel junction layer 124 located on the bottom electrode 112 (Fig. 1);
a Hall effect layer 102 located on the magnetic tunnel junction layer 124 (Fig. 1); and
a second transistor 114, wherein a drain of the second transistor is connected to the bottom electrode 112 (Fig. 1).
Katti is silent on (i) wherein the Hall affect layer is an orbital Hall affect layer; and (ii) wherein a first transistor, wherein a drain of the first transistor is connected to the orbital Hall effect layer.
Regarding (i), YAN teaches an orbital Hall affect layer 751 located on a magnetic tunnel junction layer 710 (the MTJ 710, a thin heavy metal 701 along with the metal component 751 generate an orbital Hall affect, Fig. 7). This has the advantages of reducing the use of excessive heavy metal while still generating usable spin current. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Katti with the orbital Hall affect layer, as taught by YAN, so as to reduce the excessive use of costly heavy metal while still generate sufficient spin current.
Regarding (ii), SUN teaches an SOT-MRAM device comprising a Hall affect layer 10; and a first transistor, wherein a drain of the first transistor is connected to the Hall affect layer (see Fig. 2, also note a second transistor, wherein a drain of the second transistor is connected to a bottom electrode). This has the advantages providing a switching mechanism, fast writing and reading speed and lower power consumption for the device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Katti and YAN with the switching mechanism, as taught by SUN, so as to obtain an improved SOT-MRAM memory unit.
Regarding claim 2, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 1, further comprising: a heavy metal layer 701 located between the magnetic tunnel junction layer 710 and the orbital Hall effect layer 751 (e.g. YAN’s Fig. 7).
Regarding claim 3, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 2, wherein the orbital Hall effect layer 102/751 and the heavy metal layer 701 are configured to conduct a write current; wherein the orbital Hall effect layer 751 is configured to convert the write current into an orbital-polarized orbital current through an orbital Hall effect; the heavy metal layer 701 is configured to convert the write current into a spin- polarized spin current through a spin-orbit coupling (YAN’s Fig. 2, 5-7 and associated text. Furthermore, because the prior art teaches the claim structural features, the device is capable of said functionality).
Regarding claim 4, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 3, wherein the orbital current that diffuses into the heavy metal layer 701 is converted into a spin current under a strong spin-orbit coupling effect of the heavy metal layer (Fig. 1-7 and associated text. Furthermore, because the prior art teaches the claim structural features, the device is capable of said functionality).
Regarding claim 5, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 4, wherein the spin current generated by the heavy metal layer 701 has an opposite polarity to a polarity of the spin current converted from the orbital current, so as to form a competition spin current, wherein the competition spin current is configured to achieve a deterministic magnetization reversal without assisted by an external magnetic field assistance (Fig. 1-7 and associated text. Furthermore, because the prior art teaches the claim structural features, the device is capable of said functionality).
Regarding claim 6, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 1, wherein the magnetic tunnel junction layer comprises: a ferromagnetic reference layer, a non- magnetic barrier layer and a ferromagnetic free layer from bottom to top (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2).
Regarding claim 10, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 1, further comprising: a source line SL and a bit line BL, wherein the source line is connected to the orbital Hall effect layer; and wherein the bit line is connected to a source of the first transistor and a source of the second transistor, respectively (e.g. SUN’s Fig. 2).
Regarding claim 11, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 2, wherein the heavy metal layer 701 is of one or more of Pt, Ta, W, or Gd (YAN’s Para [0021]).
Regarding claim 12, the combination of Katti, YAN and SUN teaches the SOT-MRAM memory cell according to claim 6, wherein the ferromagnetic reference layer is made of Co, CoFeB or Co/Pt, or comprises a synthetic antiferromagnetic structure; the bottom electrode is made of one or more of Pt, Ta, or W; the non-magnetic barrier layer is made of MgO or A12O3; the ferromagnetic free layer is made of Co, CoFe, or CoFeB; the orbital Hall effect layer is made of Cu or Cr (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2 and associated texts).
Regarding claim 13, the combination of Katti, YAN and SUN teaches 13. (Currently Amended) An SOT-MRAM memory, comprising the SOT-MRAM memory cell according to claim 1 (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2).
Regarding claim 14, the combination of Katti, YAN and SUN teaches an operation method of the SOT-MRAM memory according to claim 13, comprising: controlling a voltage bias applied to a first transistor and a voltage bias applied to a second transistor in the SOT-MRAM memory, and performing a data writing operation and a data reading operation on the SOT-MRAM memory, respectively (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2 and respective texts. Furthermore, because the prior art teaches the claim structural features, the device is capable of said functionality).
Regarding claim 15, the combination of Katti, YAN and SUN teaches the operation method according to claim 14-3,wherein the performing a data reading operation on the SOT-MRAM memory comprises: controlling the first transistor to be turned off and the second transistor to be turned on, so as to read data stored in the SOT-MRAM memory through a tunnel magnetoresistance effect (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2 and respective texts. Furthermore, because the prior art teaches the claim structural features, the device is capable of said functionality).
Regarding claim 16, the combination of Katti, YAN and SUN teaches the operation method according to claim 14, wherein the performing a data writing operation on the SOT-MRAM memory comprises: controlling the first transistor to be turned on and the second transistor to be turned off, so as to form a competition spin current through an orbital Hall effect and a spin Hall effect to write data into the SOT-MRAM memory (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2 and respective texts. Furthermore, because the prior art teaches the claim structural features, the device is capable of said functionality).
Regarding claim 17, the combination of Katti, YAN and SUN teaches an SOT-MRAM memory array, comprising: a plurality of SOT-MRAM memory cells according to claim 1, wherein the plurality of SOT-MRAM memory cells are is arranged periodically (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2).
Regarding claim 18, the combination of Katti, YAN and SUN teaches an SOT-MRAM memory, comprising the SOT-MRAM memory array according to claim 17 (Katti’s Fig. 1, YAN’s Fig. 7 and SUN’s Fig. 2).
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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