DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on May 15, 2026 is acknowledged. The traversal is on the ground that independent claims 1, 9, and 12 have been amendment to include technical features that the prior art, Pan, does not disclose. This is not found persuasive because all three independent claims share a technical feature that does not make a contribution over Pan, i.e., a chip interposer (11) comprising of a wiring structure (114) configured to be connected to an external wiring (116). Hence, unity of invention is lacking a posteriori. See MPEP § 1850 (II).
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, wiring spacing of the plurality of first-type wirings (3051) is smaller than the wiring spacing of the plurality of second-type wirings (3052), as required by claims 3 and 4, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
As shown below, Fig. 3 shows the wiring spacing (S1) of the plurality of first-type wirings is larger than the wiring spacing (S2) of the plurality of second-type wirings, which contradicts the claims and ¶ [0047] of specification. For the purpose of compact prosecution, the examiner will cite prior art that teaches the wiring spacing dimensions as disclosed by Fig. 3.
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 4 is objected to because of the following informalities:
Claim 4 has a typographical error: a cross-sectional area of a first-type wiring of the plurality of first-type wirings is smaller than a cross-sectional area of a second-type wiring of the plurality of first-type wirings [sic: second-type wirings]. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Pan (CN 115579298 A; see NPL for English translation).
Regarding claim 1, Pan teach a chip assembly (1; see Fig. 2), comprising:
a first chip (left 12);
a second chip (right 12); and
a chip interposer (11), connected with the first chip and the second chip (Fig. 2 shows both chips on top of 11), respectively,
wherein the chip interposer comprises a wiring structure (113&114) configured to be connected to an external wiring (wiring 23 & 211 & 24 of substrate 2 in Fig. 5), and
the wiring structure is connected with the first chip and the second chip (Fig. 2 shows 113&114 connected to both chips), respectively;
the chip interposer further comprises a body part (112) having a cavity (space occupied by 114; ¶ [0032] of English translation: “first interconnect structure 114 is formed within the first dielectric layer 112”), and the body part comprises an opening (opening at the top surface of 112 in which 117 is set; see Fig. 2 and ¶ [0032] ) which is connected with the cavity (Fig. 2 shows cavity of 114 connected to opening of 117) and penetrates through a surface (top surface of 112 contains the opening) of the body part;
the wiring structure comprises a wiring layer (114) and a plurality of bonding parts (117) connected with the wiring layer;
the wiring layer is disposed in the cavity (Fig. 2 shows 114 within each cavity of 112), and the plurality of bonding parts are exposed from the surface of the body part through the opening (see Fig. 2 and ¶ [0030] ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Pan (CN 115579298 A) as applied to claim 1 above, and further in view of Huang (CN 114823380 A; see NPL for English translation).
Regarding claim 3, Pan teaches the chip assembly according to claim 1, but does not explicitly teach: wherein the wiring layer comprises a plurality of first-type wirings and a plurality of second-type wirings, a cross-sectional area of a first-type wiring of the plurality of first-type wirings is smaller than a cross-sectional area of a second-type wiring of the plurality of second-type wirings, and a wiring spacing of the plurality of first-type wirings is smaller than a wiring spacing of the plurality of second-type wirings; the first-type wiring is connected with the second-type wiring, and the first-type wiring or the second-type wiring is connected with a bonding part of the plurality of the bonding parts.
Huang, in the same field of invention, teaches a chip assembly (Figs. 1-9) having an interposer (200) wherein the wiring layer comprises a plurality of first-type wirings (22 collectively; see Fig. 3) and a plurality of second-type wirings (21 collectively), a cross-sectional area (cross-sectional area of any given 22) of a first-type wiring (any given 22) of the plurality of first-type wirings is smaller than a cross-sectional area (cross-sectional area of any given 21) of a second-type wiring (any given 21) of the plurality of second-type wirings, and a wiring spacing (spacing between any two adjacent 22) of the plurality of first-type wirings is smaller (see drawings objection above) than a wiring spacing (spacing between any two adjacent 21) of the plurality of second-type wirings;
the first-type wiring is connected with the second-type wiring (see Fig. 3), and the first-type wiring or the second-type wiring is connected with a bonding part (any given 23 in Fig. 9) of the plurality of the bonding parts (Fig. 9 shows 22 connected to pad 23; pad 23 is analogous to the bonding parts of Pan since 23 is used to connect to chip 30).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the device of Pan to have the wiring layer be comprised of a plurality of first-type wiring and a plurality of second-type wiring, with the first-type wiring having a smaller cross-sectional area than the latter, which results with a first-type wiring spacing that is different than the spacing of the latter, with the first-type wiring and second-type wiring connected to bonding parts. The ordinary artisan would have been motivated to modify Pan in the manner set forth above for at least the purpose of using the first-type wiring as an interconnect plug to connect different levels of second-type wiring, as the method of making the chip interposer requires different levels of dielectric materials and conductive materials (see Huang Figs. 3-4, ¶ [0039] of English translation ), for the further purpose of increasing the device density and reducing the cost of manufacturing the device (¶ [0003] ). Also, the ordinary skilled artisan would note that Pan teaches the same wiring layer structure (see structure of 114 in Pan Fig. 2 & 5).
Regarding claim 4, Pan teaches the chip assembly according to claim 1, but does not teach: wherein the wiring layer comprises a plurality of first-type wirings and a plurality of second-type wirings, a cross-sectional area of a first-type wiring of the plurality of first-type wirings is smaller than a cross-sectional area of a second-type wiring of the plurality of first-type wirings, and a wiring spacing of the plurality of first-type wirings is smaller than a wiring spacing of the plurality of second-type wirings; the first-type wiring and the second-type wiring are connected with different bonding parts of the plurality of bonding parts, respectively.
Huang, in the same field of invention, teaches a chip assembly (Figs. 1-9) having an interposer (200) wherein the wiring layer comprises a plurality of first-type wirings (22 collectively; see Fig. 3) and a plurality of second-type wirings (21 collectively), a cross-sectional area (cross-sectional area of any given 22) of a first-type wiring (any given 22) of the plurality of first-type wirings is smaller than a cross-sectional area (cross-sectional area of any given 21) of a second-type wiring (any given 21) of the plurality of first-type wirings, and a wiring spacing (spacing between any two adjacent 22) of the plurality of first-type wirings is smaller (see drawings objection above) than a wiring spacing (spacing between any two adjacent 21) of the plurality of second-type wirings;
the first-type wiring and the second-type wiring are connected with different bonding parts (23 is analogous to the bonding parts of Pan; see Fig. 9 where 23 is used to connect to chip 30) of the plurality of bonding parts, respectively (Fig. 9 shows any given 21 and 22 electrically connected to a specific 23).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the device of Pan to have the wiring layer be comprised of a plurality of first-type wiring and a plurality of second-type wiring, with the first-type wiring having a smaller cross-sectional area than the latter, which results with a first-type wiring spacing that is different than the latter and with the first-type wiring and second-type wiring connected with different bonding parts. The ordinary artisan would have been motivated to modify Pan in the manner set forth above for at least the purpose of using the first-type wiring as an interconnect plug to connect different levels of second-type wiring, as the method of making the chip interposer requires different levels of dielectric materials and conductive materials (see Huang Figs. 3-4, ¶ [0039] of English translation), for the further purpose of increasing the device density and reducing the cost of manufacturing the device (¶ [0003] ). Also, the ordinary skilled artisan would note that Pan teaches the same wiring layer structure (see structure of 114 in Pan Fig. 2 & 5).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (CN 115579298 A) as applied to claim 1 above, and further in view of Choi (US 2022/0399316 A1).
Regarding claim 5, Pan teaches the chip assembly according to claim 1, wherein the first chip comprises a first wiring layer (left 123; Fig. 2), and the second chip comprises a second wiring layer (right 123);
the first wiring layer and the second wiring layer are connected with different bonding parts of the plurality of bonding parts, respectively (Fig. 2 shows different sets of 117 connected to left 123 and right 123).
However, Pan, does not teach the device wherein the first chip comprises a first channel layer, with the first wiring layer connected with the first channel layer; and wherein the second chip comprises a second channel layer, with the second wiring layer connected with the second channel layer.
Choi, in the same field of invention, teaches a chip assembly (Fig. 1) wherein the first chip (200a) comprises a first channel layer (10a&20a; ¶ [0025]: 20a comprises transistors; transistors are known in the art to have channels to conduct between a source and a drain), with the first wiring layer (50a&15a) connected with the first channel layer (¶ [0025]); and wherein the second chip (200b) comprises a second channel layer (10b&20b; ¶ [0032]: 20b comprises transistors), with the second wiring layer (50b&15b) connected with the second channel layer (¶ [0032]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the device of Pan to add a first channel layer that is connected to the first wiring layer of the first chip and add a second channel layer that is connected to the second wiring layer of the second chip. The ordinary artisan would have been motivated to modify Pan in the manner set forth above for at least the purpose of using transistors having channels to be the active device inside the first chip and second chip (Choi ¶ [0025], [0032] ) and to further use the first wiring layer and second wiring layer to as a power distribution network that supplies power to the first chip and the second chip (¶ [0046]), for the further purpose of increasing the device density (¶ [0003], [0077] ).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (CN 115579298 A) in view of Choi (US 2022/0399316 A1) as applied to claim 5 above, and further in view of Waidhas (US 2023/0317621 A1).
Regarding claim 6, Pan et al. teach the chip assembly according to claim 5, and further teach: wherein the first wiring layer (50a&15a; Choi Fig. 1) comprises a first power wiring (¶ [0046]: power delivery network which comprises 50a that is electrically connected to wiring pattern 132), and the first power wiring comprises an embedded power line (50a; Fig. 1 and ¶ [0023] illustrate 50a being embedded inside 52a) and a through via wiring (15a; ¶ [0022] ) connected with the embedded power line;
the through via wiring penetrates through the first channel layer (¶ [0022]: 15a penetrates 10a) and is connected with the bonding part (132; Fig. 1 shows 15a being electrically connected to bonding part 132 through pads 50a; also see ¶ [0023]: Cu-Cu bonding ).
However, Pan et al. do not teach: the first wiring layer comprising of a first signal wiring.
Waidhas, in the same field of invention, teaches a first wiring layer (traces 218a inside RDL 218; see ¶ [0030] and Fig. 2 ) comprising of a first power wiring and/or a first signal wiring (¶ [0031] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Waidhas into the device of Pan et al. to have the first wiring layer be comprised of both the first power wiring and a first signal wiring. The ordinary artisan would have been motivated to modify Pan et al. in the manner set forth above for at least the purpose of routing input/output signals between first die (left 204; Waidhas Fig. 2) and the second die (right 204) and/or between each die and the external wiring (substrate 210; see Waidhas ¶ [0030] ),for the further purpose of increasing the device density (¶ [0002] ).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (CN 115579298 A) in view of Choi (US 2022/0399316 A1) and Waidhas (US 2023/0317621 A1) as applied to claim 6 above, and further in view of Chen (US 2018/0294212 A1).
Regarding claim 7, Pan teaches the chip assembly according to claim 6, but does not teach the device further comprising a third chip; wherein the third chip comprises a third channel layer and a third wiring layer connected with the third channel layer; the third wiring layer is connected with the first signal wiring.
Chen, in the same field of invention, teaches a chip assembly comprising a third chip (168A; Fig. 20);
wherein the third chip comprises a third substrate layer (170A) and a third wiring layer (172A) connected with the third substrate layer; the third wiring layer is connected (through 71A) with the first signal wiring (74A; see ¶ [0037] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chen into the device of Pan to add a third chip having a third substrate layer and a third wiring layer, with the third wiring layer connected to the first signal wiring. The ordinary artisan would have been motivated to modify Pan in the manner set forth above for at least the purpose of increasing the device density of the chip assembly by adding a third chip on top of the first chip (Chen ¶ [0002] ).
However, Chen does not teach the third substrate layer to be a third channel layer.
Choi further teaches a chip (200a) having substrate layer (10a&20a) with a channel layer (20a; ¶ [0025]: 20a made of transistors; transistors are known in the art to have channels to conduct between source and drain).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the device of Pan in view of Chen to add a channel layer to the third substrate layer. The ordinary artisan would have been motivated to modify Pan in view of Chen in the manner set forth above for at least the purpose of using transistors as active devices in semiconductor packages (Choi ¶ [0025]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (CN 115579298 A) in view of Sun (US 2023/0420330 A1).
Regarding claim 8, Pan teaches the chip assembly according to claim 1, and further teaches: wherein the first chip and the second chip are disposed on a same side (top side of 11; see Pan Fig. 2) of the chip interposer. However, Pan does not teach: comprising a blank die; wherein the blank die is disposed between the first chip and the second chip.
Sun, in the same field of invention, teaches a chip assembly (Fig. 22) comprising a blank die (502; ¶ [0090]: “the scribe fill structures 502 may be considered ‘dummy die’ ”); wherein the blank die is disposed between the first chip (left 150) and the second chip (right 150).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sun into the device of Pan to add a blank die in between the first chip and the second chip. The ordinary artisan would have been motivated to modify Pan in the manner set forth above for at least the purpose of reducing cracking or damage to the scribe region (501; Sun Fig. 22) of the assembly during a singulation process (Sun ¶ [0089]; see Fig. 23 ).
Conclusion
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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