DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Claim Rejections - 35 USC § 112 3
A. Claims 1-6, 9, and 22 are rejected under 35 U.S.C. 112(a) because the specification, while being enabling for nickel metal, does not reasonably provide enablement for all metals. 3
B. Claim 16 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 5
IV. Claim Rejections - 35 USC § 103 5
A. Claims 1, 3-7, 9, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over KR-2012045570-A (“Kim”) in view of US 2013/0115768 (“Pore”). 6
B. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Pore, as applied to claim 1 above, and further in view of US 5,926,737 (“Ameen”). 14
C. Claim 10, 12-18, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0121665 (“Fang”) in view of Kim and Pore. 16
D. Claims 10, 12-18, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Fang in view of Kim, Pore, and US 2015/0243565 (“Nieh”). 26
E. Claims 11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over (1) Fang in view of Kim, and (2) Fang in view of Kim and Nieh, each as applied to claims 10 and 18 above, and further in view of Ameen. 27
V. Response to Arguments 28
Conclusion 29
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 02/16/2026 has been entered.
III. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claims 1-6, 9, and 22 are rejected under 35 U.S.C. 112(a) because the specification, while being enabling for nickel metal, does not reasonably provide enablement for all metals.
The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make or use the invention commensurate in scope with these claims.
Claim 1 was amended to require, after the first reacting of the elemental metal film with the exposed semiconductor region at the first temperature, to be 24 μΩ∙cm and after the annealing at the second temperature to be 10.5 μΩ∙cm. However, the Instant Application indicates that this is the case for nickel forming nickel silicide (Instant Specification: ¶ 49), while, by contrast, for titanium forming titanium silicide, the first and second resistivities are indicated to be about 100 μΩ∙cm and 15 μΩ∙cm (id.).
Moreover, it is generally known, that the resistivity of a given silicide is a characteristic property of a given metal silicide, as evidenced, e.g., US 2024/0274834 (“Mui”) is provided:
PNG
media_image1.png
328
406
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Greyscale
(Mui-834: Table 1 on p. 4, ¶ 36)
Examiner would certainly consider any evidence Applicant may provide to show that the method disclosed and claimed in the Instant Application is capable of producing the resistivities required in claim 1 for other metals disclosed and claimed in the Instant Application, e.g., the specific metals recited in claim 6 that are required to attain the resistivities of 24 μΩ∙cm and 10.5 μΩ∙cm for the indicated process steps.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
B. Claim 16 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 16, which depends from claim 10, recites the limitation “any remaining titanium metal film” and “elemental nickel film”. There is insufficient antecedent basis for these limitations in the claim.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 3-7, 9, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over KR-2012045570-A (“Kim”) in view of US 2013/0115768 (“Pore”).
KR- 2012045570-A (“Kim”) is cited in the IDS filed 08/07/2023. All citations to figures refer to the original KR patent and citations to text are from the machine translation attached with the Non-Final Rejection mailed 08/26/2025.
Claim 1 reads,
1. (Currently Amended) A method of forming a device, the method comprising:
[1] providing a substrate containing an exposed semiconductor region;
[2] forming a metal oxide film over the exposed semiconductor region;
[3] forming an oxygen-scavenging metal film over the metal oxide film;
[4] chemically reducing the metal oxide film to an elemental metal film by scavenging oxygen from the metal oxide film into the oxygen-scavenging metal film; and
[5a] reacting, at a first temperature, the elemental metal film with the exposed semiconductor region to form an intermediate layer containing atoms from the elemental metal film and atoms from the semiconductor region,
[5b] the intermediate layer having a first resistivity of 24 micro-ohm*cm;
[6] removing remaining portions of the elemental metal film and the oxygen-scavenging metal film after forming the intermediate layer; and
[7a] after the removing, annealing at a second temperature above the first temperature to convert the intermediate layer to form a metal-semiconductor layer,
[7b] the metal-semiconductor layer having a second resistivity of 10.5 micro-ohm*cm,
[7c] the metal-semiconductor layer forming a source/drain contact region of a transistor.
With regard to claim 1, Kim discloses, generally in Figs. 2A-2C and at p. 2, line 18 to p. 3, line 23,
1. (Currently Amended) A method of forming a device [title], the method comprising:
[1] providing a substrate 21 containing an exposed semiconductor region 21 [¶. 2, line 27];
[2] forming a metal oxide film 22 [e.g. NiO (p. 2, lines 33-34)] over the exposed semiconductor region 21;
[3] forming an oxygen-scavenging metal film 23(24) [p. 2, lines 26, 36, 46, 49 e.g. Ti] over the metal oxide film 22;
[4] chemically reducing the metal oxide film 22 to an elemental metal film 25 by scavenging oxygen from the metal oxide film 22 into the oxygen-scavenging metal film 23(24) [23(24), e.g. Ti, becomes “sacrificial oxide film 26”, e.g. TiOx; p. 2, line 44 to p. 3, line 2];
[5a] reacting, at a first temperature, the elemental metal film 25 with the exposed semiconductor region 21 to form an intermediate layer 27 containing atoms from the elemental metal film [e.g. Ni] and atoms from the semiconductor region 21 [e.g. Si] [i.e. a nickel silicide];
[5b] … [not taught] …
[6] removing … the oxygen-scavenging metal film 26 after forming the intermediate layer 27 [p. 3, lines 25-26: “Although not illustrated in the present embodiment, the sacrificial oxide film 26 formed from the titanium film 24 may optionally be removed …”]; and
[7a]-[7c] … [not taught] …
With regard to feature [3], note that the machine language translation, inexplicably, uses reference character 23 and 24 to denote the “sacrificial film”, which is shown in Figs. 2A-2C to be only 23.
With regard to features [5a], [5b], [6], [7a], and [7b] of claim 1,
[5a] reacting, at a first temperature, the elemental metal film with the exposed semiconductor region to form an intermediate layer containing atoms from the elemental metal film and atoms from the semiconductor region;
[5b] the intermediate layer having a first resistivity of 24 micro-ohm*cm;
[6] removing remaining portions of the metal oxide film and the oxygen-scavenging metal film after forming the intermediate layer; and
[7a] after the removing, annealing at a second temperature above the first temperature to convert the intermediate layer to form a metal-semiconductor layer,
[7b] the metal-semiconductor layer having a second resistivity of 10.5 micro-ohm*cm,
Kim does not teach a silicidation process that is performed with first and second annealing steps with a cleaning process between that removes any unreacted elemental metal film (Ni) 25, unreduced metal oxide (NiO) 21, or oxygen-scavenging film 23(24), as claimed in features [5a], [6], and [7a], or the resistivities of the intermediate nickel silicide or the final nickel silicide after the reacting at the first temperature and the annealing at the second temperature, as claimed in features [5b] and [7b].
Pore teaches that it is known to form a nickel silicide film 370 specifically on exposed regions of the semiconductor substrate, e.g. Si, that are source/drain regions 330, 340 using a similar process to that used in Kim, i.e. depositing NiO 365 on the source/drain regions 330, 340 (step 230 in Fig. 2B), reducing the nickel oxide to nickel metal (step 240a in Fig. 2B) using a first anneal, albeit in a gaseous reducing atmosphere at 300 ℃ (Pore: ¶¶ 64, 69) rather than using the overlying Ti metal layer, as in Kim, and then performing a separate silicidation anneal at e.g. 400 ℃ to form a higher resistivity nickel silicide (step 240b in Fig. 2B), as well as removing any unreacted material after the silicidation anneal 240b (step 250 in Fig. 2B). (See Pore: title, abstract, Figs. 2B, Figs. 3A-3C, Fig. 10; ¶¶ 63-72). Pore further teaches that, after each of the silicidation anneal 240b and the removal of the unreacted materials 250, a third anneal 260 is performed to convert the higher resistivity nickel silicide (e.g. Ni2Si) formed in the silicidation anneal 240b into a lower resistivity nickel silicide (i.e. NiSi) (Pore: ¶¶ 10, 67).
Pore further teaches that after the silicidation anneal and the etching step can remove residual NiO that has not be reduced as well as any other reaction products:
[0068] One embodiment for forming NiSi using an Sb interlayer is illustrated schematically in FIG. 10. A Sb interlayer 810 is deposited over a Si substrate 800, for example by ALD. A NiO layer 820 is subsequently deposited 840 directly over the Sb layer 810, such as by ALD and a salicidation reaction 850 is carried out by annealing, for example by heating to 500℃. In the silicidation reaction at least a portion of the nickel from the NiO layer 820 reacts with silicon in the Si layer 800 to form NiSi 830. Any remaining unreacted Ni or NiO is removed and the NiSi layer 830 exposed by etching 860, as described above, leaving a layer of NiSi 830 over the Si substrate 800. An example of such a deposition process is provided in Example 4.
(Pore: ¶ 68; emphasis added)
Thus, Pore teaches each of the limitations of features [4], [5], [6], and [7a] of claim 1, as follows:
[4] chemically reducing the metal oxide film 365 to an elemental metal film [not separately shown in Figs. 3B-3C] by scavenging oxygen from the metal oxide film 365 … [step 240a in Fig. 2B]; and
[5] reacting, at a first temperature [e.g. 400 ℃ (Pore: ¶¶ 9, 69)], the elemental metal film [not separately labeled] with the exposed semiconductor region 340 to form an intermediate layer 370 [higher-resistivity metal silicide, e.g. Ni2Si (Pore: ¶¶ 10, 67)] containing atoms from the elemental metal film e.g. Ni] and atoms from the semiconductor region 340 [i.e. the “silicidation anneal” 240b in Fig. 2B];
[6] removing remaining portions of the metal oxide film [e.g. NiO film 820 (Pore: ¶ 68; Fig. 10)] … after forming the intermediate layer 370 [step 250 in Fig. 2B]; and
[7a] after the removing, annealing at a second temperature [e.g. 450 ℃ (Pore: ¶ 10) or greater (Pore: ¶¶ 7, 19)] above the first temperature [e.g. 400 ℃] to convert the intermediate layer 370 [e.g. higher-resistivity Ni2Si] to form a metal-semiconductor layer 370 [e.g. lower-resistivity NiSi],
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use, in place of the single high-temperature silicidation anneal in Kim, the lower-temperature silicidation anneal 240b of, e.g. 400 ℃, and the higher temperature anneal resistivity-reducing anneal 260 of, e.g. 450 ℃, taught in Pore, with the cleaning/etching removal of the oxidized oxygen-scavenging TiOx layer 26, any unreacted NiO film 22 that may be present, between said lower- and higher-temperature annealing steps, because it would allow the prevention of the agglomeration during the silicidation anneal that Kim desires (Kim: p. 3, 14-19), while also allowing a separate higher-temperature anneal to reduce the higher-resistivity Ni2Si to lower-resistivity NiSi. In addition, the lower temperature annealing in Pore (e.g. 450 ℃) versus Kim (700 ℃ to 800 ℃ RTA [Kim: p. 3, lines 7-12]) may provide a lower thermal budget to achieve a lower-resistivity NiSi film. As such, Pore may be seen as an improvement to Kim in these aspects. (See MPEP 2143.)
Further with regard to features [5b] and [7b], it is held, absent evidence to the contrary, that the two-step annealing process of Pore used in Kim would result inherently in a resistivity 24 μΩ∙cm for the Ni2Si layer as a result of the “reacting, at a first temperature” of, e.g. 400 ℃, and a resistivity of 10.5 μΩ∙cm for the NiSi layer as a result of the “annealing at a second higher temperature above the first temperature”, e.g. 450 ℃. As evidence, see the Instant Application, which states,
At temperatures above about 200° C., the elemental metal film 106 may react with the semiconductor region 102 forming metal silicide compounds such as nickel silicide compounds. Crystalline nickel silicide formed at temperatures below about 450° C. has high resistance [i.e. Ni2Si]. Metal silicide 110 such as nickel silicide may be annealed at temperatures around 500° C. or more and converted to a lower resistance crystalline form [i.e. NiSi].
(Instant Specification: ¶ 31; emphasis added)
In other words, the same process would be expected to result in the same intermediate and final resistivities. Based on the foregoing, the burden of proof is shifted to Applicant to prove the contrary. i.e. that the resistivities of the nickel silicide of Kim/Pore does not have the intermediate resistivity of 24 μΩ∙cm and final resistivity of 10.5 μΩ∙cm. (See MPEP 2112(I)-(V).)
With regard to feature [7c] of claim 1, Kim does not teach that the semiconductor region is a source/drain region of a transistor such that the metal silicide forms a contact to said source/drain region.
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the silicon layer in the process of Kim a source/drain region or, in other words, the use of the process of Kim to make NiSi contacts to the source/drain regions of a field effect transistor, because Pore teaches that it is known to use essentially the same process as that in Kim specifically for forming NiSi contacts to source/drain regions.
This is all of the limitations of claim 1.
With regard to claim 3, Kim further discloses,
3. (Original) The method of claim 1, wherein the semiconductor region comprises silicon, germanium, carbon, tin, gallium, indium, or arsenic, or mixtures thereof [p. 2, line 27].
With regard to claims 4 and 5, Kim modified according to Pore, as explained above, further teaches,
4. (Original) The method of claim 1, wherein the chemically reducing step and the reacting step are performed simultaneously using a heat-treating step [p. 3, lines 21-23].
5. (Original) The method of claim 4, wherein the heat-treating step is performed at a substrate temperature between about 400ºC and about 750ºC.
With regard to claim 4, Kim states,
The primary heat treatment 201 for forming the sacrifice oxide film 26 and the secondary 22 heat treatment 202 for forming the metal silicide film 27 can be independently performed or 23 simultaneously formed in one heat treatment process.
(Kim translation: p. 3, lines 21-23; emphasis added )
Pore further teaches in the process in Fig. 2A (versus in 2B) that a single anneal step 240 can be used to reduce the NiO to metal and perform the silicidation reaction, at a temperature that may be greater than about 400 ℃ (Pore: ¶ 64), which is consistent with Kim.
With regard to claim 5, the heat treatment temperature for the primary heat treatment 201 is performed in a temperature range of 400 ℃ to 550 ℃ (Kim: p. 2, line 44 to p. 3, line 2), and the secondary heat treatment 201 is performed in a temperature range of 700 ℃ to 800 ℃ (p. 3, lines 7-12). Therefore, the temperature range for both processes is 400 ℃ to 800 ℃.
Pore further teaches in the process in Fig. 2A (versus in 2B) that a single anneal step 240 can be used simultaneously to reduce the NiO to Ni metal and perform the silicidation reaction between the Ni and the Si, at a temperature than may be greater than about 400 ℃ (Pore: ¶ 64), which is consistent with Kim and claim 5.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.) Here there are none because both of Kim/Pore and the Instant Application use a single anneal for NiO reduction and silicidation.
This is all of the limitations of claims 4 and 5.
With regard to claims 6, 7, and 9, Kim further discloses,
6. (Previously Presented) The method of claim 1, wherein the metal in the elemental metal film, in the metal oxide film, and in the metal-semiconductor layer is a metal selected from a group consisting of Ni, Os, Co, Ru, Ir, Pd, Pt, and Rh.
7. (Previously Presented) The method of claim 1, wherein the metal oxide 22 film includes a nickel oxide film, the elemental metal film 23 includes elemental nickel metal, and the metal-semiconductor layer 27 includes a nickel silicide.
9. (Previously Presented) The method of claim 1, wherein the oxygen-scavenging metal film 23(24) is a metal selected from a group consisting of Ti, Sc, Y, La and lanthanides, Zr, Hf, V, Nb, and Ta.
Claim 22 reads,
22. (Previously Presented) The method of claim 1, wherein a thickness of the oxygen-scavenging metal film is two times or more of a thickness of the metal oxide film.
Kim further teaches that each of the NiO and the Ti can be formed to a thickness of from several nanometers to several tens of nanometers:
The metal oxide 22 and the sacrificial film 23 are continuously formed in-situ. That is, the metal oxide 22 is formed to a thickness of several to several tens of nanometers by using any one of deposition methods selected from the group consisting of physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD) And can be deposited using a source or a precursor used in the process. After the formation of the metal oxide 22, the metal oxide 22 [sic; should be “sacrificial film 23”] is continuously deposited in the in-situ state to a thickness of several nanometers to several tens of nanometers.
(Kim: p. 2, lines 36-42; emphasis added)
Fig. 2A of Kim taken with the paragraph from Kim, above, makes clear that the layer deposited on the metal oxide film 22 is the sacrificial film 23. Therefore, the sacrificial film 23 is also formed to “a thickness of several nanometers to several tens of nanometers”. As such, Kim includes the possibility that the Ti layer 23 could be greater than twice the thickness of the NiO layer 22—as required by feature [3b]. In other words, the NiO could be several nanometers, e.g., 3, 4, or 5 nm, and the Ti layer could be several tens of nanometers, e.g. 30, 40, or 50 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the metal oxide film 22, e.g. NiO, to several nanometers thick and the oxygen-scavenging Ti film 23 to several tens of nanometers thick because Kim suggests thicknesses for each of these layers in this range. Moreover, one having ordinary skill in the art would reasonably make the Ti layer significantly thicker than the NiO layer in order to ensure that there is sufficient volumetric/molar quantity of Ti to reduce the NiO in the NiO layer to Ni metal.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.) Here there is no evidence of unexpected results because the intended effect of the Ti layer is to reduce the NiO to Ni metal is the same in each of Kim and the Instant Application.
This is all of the limitations of claim 22.
B. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Pore, as applied to claim 1 above, and further in view of US 5,926,737 (“Ameen”).
Claim 2 reads,
2. (Original) The method of claim 1, wherein
[1] the oxygen-scavenging metal film is a titanium metal film
further including
[2] forming the titanium metal film by reacting TiCl4 with hydrogen and
[3] removing unreacted titanium film by etching in a TiCl4 ambient.
The prior art of Kim in view of Pore, as explained above, teaches each of the features of claim 1. As explained above, Kim discloses Ti as the oxygen-scavenging metal film. Kim further teaches that PVD, CVD, and ALD can be used to deposit the Ti film, but does not indicate specifically indicate “reacting TiCl4 with hydrogen”.
Ameen teaches a method of making a titanium silicide contact to a semiconductor substrate (Fig. 2A-2C). The Ti metal film is deposited by CVD using TiCl4 with hydrogen (Ameen: col. 5, lines 26-46—especially lines 43-46). After the formation of the TiSi, the excess Ti is etched away using TiCl4 (Ameen: title, abstract, col. 5, line col. 63 to col. 6, line 43; Figs. 3-5).
Inasmuch as Kim discloses that that Ti film 23(24) can be deposited using CVD and that excess Ti can be removed after the silicidation reaction, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the process of deposition (i.e. TiCl4 with hydrogen) and subsequent excess Ti removal of (TiCl4) because Ameen teaches that these complementary deposition and removal processes are (1) very old and well known and (2) simplify the process by using the same compound, i.e. TiCl4, for both deposition and removal of Ti, and (3) are appropriate in association with formation of silicides.
This is all of the limitations of claim 2.
C. Claim 10, 12-18, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0121665 (“Fang”) in view of Kim and Pore.
Again, KR-2012045570-A (“Kim”) is cited in the IDS filed 08/07/2023. All citations to figures refer to the original KR patent and citations the text are to the machine translation attached with the Non-Final Rejection mailed 08/26/2025.
Claim 10 reads,
10. (Currently Amended) A method of forming source/drain regions, comprising:
[1] providing a substrate containing first and second semiconductor regions;
[2] selectively forming a metal oxide film over the first semiconductor region;
[3a] forming an oxygen-scavenging metal film over the first and second semiconductor regions,
[3b] wherein a thickness of the oxygen-scavenging metal film is two times or more of a thickness of the metal oxide film;
[4] chemically reducing the metal oxide film to an elemental metal film by scavenging oxygen from the metal oxide film into the oxygen-scavenging metal film;
[5] reacting the elemental metal film with the first semiconductor region to form a metal semiconductor film;
[6] reacting the oxygen-scavenging metal film with the second semiconductor region to form an oxygen-scavenging metal semiconductor film; and
[7] annealing to reduce resistivities of the metal semiconductor film and the oxygen- scavenging metal semiconductor film.
With regard to claim 10, Fang discloses, generally in Figs. 10-13 and 18, and paragraphs [0036]-[0038] and [0045],
10. (Currently Amended) A method of forming source/drain regions, comprising:
[1] providing a substrate 202 containing first 240(204) [NFET, implying p-type well 204] and second 230(203) [PFET, implying n-type well 203] semiconductor regions;
[2] selectively forming a metal … film 221 [e.g. Ni (¶¶ 38, 45)] over the first semiconductor region 240(204);
[3a] forming an … metal film 223 [e.g. Ti (¶¶ 38, 45)] over the first 240(204) and second 230(203) semiconductor regions,
[3b] … [not taught] …
[4] … [not taught] …
[5] reacting the … metal film 221 [e.g. Ni] with the first semiconductor region 240(204) to form a metal semiconductor film 206 [i.e. nickel silicide]; and
[6] reacting the … metal film 223 [e.g. Ti] with the second semiconductor region 230(203) to form an … metal semiconductor film 216 [i.e. titanium silicide]; and
[7] … [not taught] …
With regard to feature [1] of claim 1, although the example in Figs. 10-13 have the p-type well 204 of the NFET region 240 region and the n-type well 203 for the PFET region 230, Fang explicitly states that this can be reversed:
[0046] In one embodiment, the first well region 203 is configured as a NFET well region and the second well region 204 is configured as a PFET well region. In another embodiment, the first well region 203 is configured as a PFET well region and the second well region 204 is configured as a NFET well region.
(Fang: ¶ 46; emphasis added)
As such, Fang teaches that it is obvious to make the claimed “first semiconductor region” 240 to be the PFET region and therefore have an n-type well 204 with p-type source/drain regions 228.
With regard to features [2]-[4] of claim 10, Fang does not indicate that the first metal film 221 (e.g. Ni) is a metal oxide film, as required by feature [2], and that the second metal film 223 (e.g. Ti) is an oxygen-scavenging film, as required by features [3a]-[3b]. Accordingly, feature [4] is also not taught.
Kim, like Fang, is drawn to formation of silicides. Kim teaches that a Ni metal film for silicide formation is deposited as a metal oxide, i.e. NiO, over which is deposited an oxygen-scavenging metal film of Ti, followed by a thermal treatment 201 to reduce the NiO to Ni—as required by features [2], [3a], and [4] of claim 10. Kim explains that the benefit of this process is to prevent agglomeration or coagulation or aggregation phenomenon in the formation of NiSi (Kim: p. 1, lines 26-41 and p. 2, lines 6-9 and p. 4, line 46 to p. 5, line 2). Kim further teaches that each of the NiO and the Ti can be formed to a thickness of from several nanometers to several tens of nanometers:
The metal oxide 22 and the sacrificial film 23 are continuously formed in-situ. That is, the metal oxide 22 is formed to a thickness of several to several tens of nanometers by using any one of deposition methods selected from the group consisting of physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD) And can be deposited using a source or a precursor used in the process. After the formation of the metal oxide 22, the metal oxide 22 [sic; should be “sacrificial film 23”] is continuously deposited in the in-situ state to a thickness of several nanometers to several tens of nanometers.
(Kim: p. 2, lines 36-42; emphasis added)
Fig. 2A of Kim taken with the paragraph from Kim, above, makes clear that the layer deposited on the metal oxide film 22 is the sacrificial film 23. Therefore, the sacrificial film 23 is also formed to “a thickness of several nanometers to several tens of nanometers”.
As such, Kim includes the possibility that the Ti layer 23 could be greater than twice the thickness of the NiO layer 22—as required by feature [3b]. In other words, the NiO could be several nanometers, e.g., 3, 4, or 5 nm, and the Ti layer could be several tens of nanometers, e.g. 30, 40, or 50 nm. Moreover, one having ordinary skill in the art would reasonably make the Ti layer significantly thicker than the NiO layer in order to ensure that there is sufficient volumetric/molar quantity of Ti to reduce all of the NiO in the NiO layer to Ni metal. Thus, Kim teaches the following features of claim 10:
10. (Currently Amended) A method of forming …[a silicide region in a semiconductor device]… [Kim: abstract; Figs. 2A-2C], comprising:
[1] providing a substrate 21 containing … semiconductor region 21… [p. 2, line 27];
[2] selectively forming a metal oxide film 22 [e.g. NiO (p. 2, lines 33-34)] over the … semiconductor region [Kim: Fig. 2A];
[3a] forming an oxygen-scavenging metal film 23(24) [p. 2, lines 26, 36, 46, 49 e.g. Ti] over the … semiconductor region… [Kim: Fig. 2A],
[3b] wherein a thickness of the oxygen-scavenging metal film 23(24) is two times or more of a thickness of the metal oxide film 22 [as explained above];
[4] chemically reducing the metal oxide film 22 to an elemental metal film 25 by scavenging oxygen from the metal oxide film 22 into the oxygen-scavenging metal film 23(24) [23(24), e.g. Ti, becomes “sacrificial oxide film 26”, e.g. TiOx; p. 2, line 44 to p. 3, line 2];
[5] reacting the elemental metal film 25 with the … semiconductor region 21 to form a metal semiconductor film 27 [e.g. NiSi; p. 3, lines 4-23]; and
[6] … [not taught] …
[7] … [not taught] …
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first metal layer 221 in Fang of a metal oxide, e.g. NiO, of several nanometers thickness and the second metal layer 223 as Ti of several tens of nanometers, and to perform the thermal treatment to reduce the NiO to Ni using the Ti to scavenge the O from the NiO, as taught in Kim because (1) Fang teaches that the first 221 and second 223 metals can be Ni and Ti, respectively, as consistent with Kim, and (2) Kim teaches the benefit of preventing the agglomeration or coagulation or aggregation phenomenon in the formation of NiSi by forming the first silicide forming metal as a metal oxide, e.g. NiO, and then reducing the NiO to Ni metal by depositing an overlying metal film of Ti to scavenge the oxygen during a thermal anneal performed before or simultaneously with the formation of the NiSi. As such, Kim may be seen as an improvement to Fang in this aspect. (See MPEP 2143.)
So modified, each of features [2]-[4] of claim 10 are taught.
The features of claim [5] and [6] are also taught because the Ni film 221 in Fang is the elemental Ni film of Fang/Kim and the Ti film 223 of Fang is the oxygen-scavenging film of Fang/Kim.
Finally with regard to feature [3b] of claim 15, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.) Here there is no evidence of unexpected results because the intended effect of the Ti layer is to reduce the NiO to Ni metal is the same in each of Kim and the Instant Application.
With regard to feature [7] of claim 10,
[7] annealing to reduce resistivities of the metal semiconductor film and the oxygen- scavenging metal semiconductor film.
Fang does not disclose two separate annealing processes for forming the nickel and titanium silicides, and Kim does not teach two separate annealing processes for forming the nickel silicide. As such, neither of Fang and Kim teaches the process in feature [7].
However, as explained above, Pore teaches that it is known to form a nickel silicide film 370 specifically on exposed regions of the semiconductor substrate, e.g. Si, that are source/drain regions 330, 340 using a similar process to that used in Kim, i.e. depositing NiO 365 on the source/drain regions 330, 340 (step 230 in Fig. 2B), reducing the nickel oxide to nickel metal (step 240a in Fig. 2B) using a first anneal, albeit in a gaseous reducing atmosphere at 300 ℃ (Pore: ¶¶ 64, 69) rather than using the overlying Ti metal layer, as in Kim, and then performing a separate silicidation anneal at e.g. 400 ℃ to form a higher resistivity nickel silicide, e.g. Ni2Si, (step 240b in Fig. 2B), as well as removing any unreacted material after the silicidation anneal 240b (step 250 in Fig. 2B). (See Pore: title, abstract, Figs. 2B, Figs. 3A-3C, Fig. 10; ¶¶ 63-72). Pore further teaches that, after each of the silicidation anneal 240b and the removal of the unreacted materials 250, a third anneal 260 is performed to convert the higher resistivity nickel silicide (e.g. Ni2Si) formed in the silicidation anneal 240b into a lower resistivity nickel silicide (i.e. NiSi) (Pore: ¶¶ 10, 67).
Pore further teaches that after the silicidation anneal, the etching step can remove residual Ni and NiO that has not be reduced as well as any other reaction products:
[0068] One embodiment for forming NiSi using an Sb interlayer is illustrated schematically in FIG. 10. A Sb interlayer 810 is deposited over a Si substrate 800, for example by ALD. A NiO layer 820 is subsequently deposited 840 directly over the Sb layer 810, such as by ALD and a salicidation reaction 850 is carried out by annealing, for example by heating to 500℃. In the silicidation reaction at least a portion of the nickel from the NiO layer 820 reacts with silicon in the Si layer 800 to form NiSi 830. Any remaining unreacted Ni or NiO is removed and the NiSi layer 830 exposed by etching 860, as described above, leaving a layer of NiSi 830 over the Si substrate 800. An example of such a deposition process is provided in Example 4.
(Pore: ¶ 68; emphasis added)
Thus, in addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use, in place of the single high-temperature silicidation anneal in Kim (used in Fang), the lower-temperature silicidation anneal 240b of, e.g. 400 ℃, and the higher temperature anneal resistivity-reducing anneal 260 of, e.g. 450 ℃, taught in Pore, with the cleaning/etching removal of the oxidized oxygen-scavenging TiOx layer 26, any unreacted elemental Ni film that may be present, between said lower- and higher-temperature annealing steps (of Kim and Pore), because it would allow the prevention of the agglomeration during the silicidation anneal that Kim desires (Kim: p. 3, 14-19), while also allowing a separate higher-temperature anneal to reduce the higher-resistivity Ni2Si to lower-resistivity NiSi. In addition, the lower temperature annealing in Pore (e.g. 450 ℃) versus Kim (700 ℃ to 800 ℃ RTA [Kim: p. 3, lines 7-12]) may provide a lower thermal budget to achieve a lower-resistivity NiSi film. As such, Kim and Pore may be seen as improvements to Fang in these aspects. (See MPEP 2143.)
Because the nickel silicides and the titanium silicides on the source/drain regions of adjacent MOSFETs are formed simultaneously in Fang, the modifications of the two-step anneal with the cleaning step in between the annealing steps would remove unreacted titanium along with the TiOx as well as perform a two-step anneal on the Ti layer 223 of Fang to produce, by the first anneal, the higher-resistivity phase of Ti silicide and, by the second anneal, the lower resistivity phase of Ti silicide.
This is all of the limitations of claim 10.
With regard to claim 12, Fang in view of Kim further teaches,
12. (Original) The method of claim 10, wherein the chemically reducing step and the reacting the elemental metal film and the oxygen-scavenging metal film steps are performed simultaneously by heating the substrate.
Again, Kim teaches this at p. 3, lines 21-23 as quoted above under the rejection of claim 4 over Kim in view of Pore.
As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form each of the NiSi film 206 and TiSi film 216 of Fang/Kim in a single anneal step that reduces the NiO to Ni metal by the oxygen-scavenging of Ti in order to reduce the annealing process to a single step, which saves proves time.
With regard to claims 13-15, Fang modified according to Kim, as explained under claim 10 above, further teaches,
13. (Original) The method of claim 10, wherein the metal in the elemental metal film 221 [of Fang/Kim], in the metal oxide film, and in the metal semiconductor film 206 [of Fang] is a metal selected from a group consisting of Ni, Os, Co, Ru, Ir, Pd, Pt, and Rh.
14. (Original) The method of claim 10, wherein the oxygen-scavenging metal [film] 223 [of Fang/Kim] is a metal selected from a group consisting of Ti, Sc, Y, La and lanthanides, Zr, Hf, V, Nb, and Ta.
15. (Original) The method of claim 10, wherein the metal oxide film includes a nickel oxide film, the elemental metal film includes elemental nickel metal, and the metal semiconductor film includes nickel silicide [supra].
With regard to claim 16, each of Fang (Fig. 13; ¶ 38) and Kim (p. 3, lines 25-26) teaches,
16. (Original) The method of claim 10, further comprising: removing any remaining titanium metal film, elemental nickel metal, or both, from the substrate.
With regard to claim 17, each of Fang (¶ 33) and Kim (p. 2, line 27) teaches,
17. (Original) The method of claim 10, wherein the first semiconductor region is p-type silicon or p-type silicon germanium and wherein the second semiconductor region is n-type silicon or n-type silicon germanium or n-type carbon doped silicon.
As explained under claim 1, although the example in Figs. 10-13 have the p-type well 204 of the NFET region 240 region and the n-type well 203 for the PFET region 230, Fang explicitly states that this can be reversed:
[0046] In one embodiment, the first well region 203 is configured as a NFET well region and the second well region 204 is configured as a PFET well region. In another embodiment, the first well region 203 is configured as a PFET well region and the second well region 204 is configured as a NFET well region.
(Fang: ¶ 46; emphasis added)
As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the claimed “first semiconductor region” 240 to be the PFET region and therefore have an n-type well 204 with p-type source/drain regions 228 because Fang explicitly suggests this option.
As such, the NiSi would be formed on the p-type source/drain regions 228 in the first regions 240(204), and the TiSi would be formed on the n-type source/drain regions 229 in the second region 230(203).
This is all of the features of claim 17.
With regard to claim 21, Fang modified according to Kim, as explained under claim 10 above, further teaches,
21. (Previously presented) The method of claim 10, wherein selectively forming the metal oxide film [i.e. the Ni film 221 of Fang made of NiO as taught by Kim] over the first semiconductor region 240(204) includes
[1] forming the metal oxide film [i.e. the Ni film 221 of Fang made of NiO as taught by Kim] over the first 240(204) and the second 230(203) semiconductor region [Fig. 10 of Fang] and
[2] removing the metal oxide film from the second semiconductor regions 230(203) by masking the first semiconductor region 240(204) and removing the metal oxide from the second semiconductor region 230(203) using an etching process [Fang: ¶ 37; Fig. 11].
Fang states “Then, as shown in FIG. 11, a first (and only) lithographic pattern and etching process (preferably an anisotropic dry etching process) is performed to remove a portion of the metal layer 221 and cap layer 222 over the PFET region 230 of the device 201” (Fang: ¶ 37; emphasis added). Although the mask is not shown, it is necessarily inherently present over the NFET region 240(204) because the process is lithography and the metal 221 and capping 222 layers are blanket deposited and would therefore be removed if not covered with a lithographically patterned mask preventing the etchant from reaching 221 and 222 in the first region 240(204). As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
Claim 18 reads,
18. (Currently Amended) A method of forming a device, the method comprising:
[1] providing a substrate containing first and second semiconductor regions;
[2] selectively forming a nickel oxide film over the first semiconductor region;
[3] forming a titanium metal film over the first and second semiconductor regions;
[4] chemically reducing the nickel oxide film to an elemental nickel metal film by oxygen scavenging from the nickel oxide film to the titanium metal film;
[5] reacting the elemental nickel metal film with the first semiconductor region to form a nickel semiconductor film; and
[6] reacting the titanium metal film with the second semiconductor region to form a titanium semiconductor film,
[7] wherein the chemically reducing step and the reacting steps include a heat-treating step;
[8] removing unreacted portions of the elemental nickel metal film and unreacted portions of the titanium metal film after forming the nickel semiconductor film and the titanium semiconductor film; and
[9a] annealing to:
[9b] convert the titanium semiconductor film to a titanium silicide layer, the titanium silicide layer comprising a lower resistance than a resistance of the titanium semiconductor film; and
[9c] convert the nickel semiconductor film to a nickel silicide layer, the nickel silicide layer comprising a lower resistance than a resistance of the nickel semiconductor film,
[9c] the annealing being performed at a higher temperature than the heat-treating step.
Claim 18 is distinguished from claim 10 in requiring (1) the metal oxide to be nickel oxide and therefore (2) the elemental metal film to be nickel, and (3) the oxygen-scavenging metal to be titanium. As such, each of the limitations of claim 18 have been addressed above under claims 10 or 10 and 12.
Claim 20 reads,
20. (Original) The method of claim 18, wherein the first semiconductor region comprises p-type silicon, p-type silicon germanium, p-type germanium, or p-type germanium-tin and wherein the second semiconductor region comprises n-type silicon, n-type carbon doped silicon, or n-type germanium.
See discussion under claim 17, above, which is incorporated here.
D. Claims 10, 12-18, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Fang in view of Kim, Pore, and US 2015/0243565 (“Nieh”).
The prior art of Fang in view of Kim and Pore, as explained above, teaches each of the features of claims 10, 12-18, 20, and 21.
Although Fang does not limit the silicide (1) that is formed as the p-type source/drain contacts the PFET to only NiSi and (2) that is formed as the n-type source/drain contacts of the NFET to Ti/Si, Nieh specifically forms NiSi as the p-type source/drain contacts of a PFET and TiSi as the n-type source/drain contacts (Nieh: Fig. 2K).
Thus, Nieh further supports forming the first silicide forming metal oxide 221 of Fang/Kim as NiO on the p-type source/drain regions and the second metal as Ti on the NiO and on the n-type source/drain regions, in order to specifically form NiSi as the p-type source/drain contacts of a PFET and TiSi as the n-type source/drain contacts, as taught to be known in Nieh. (Nieh: Fig. 2K).
This is all of the limitations of claims 10, 12-18, 20, and 21.
E. Claims 11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over (1) Fang in view of Kim, and (2) Fang in view of Kim and Nieh, each as applied to claims 10 and 18 above, and further in view of Ameen.
Claims 11 and 19 read,
11. (Original) The method of claim 10, wherein
[1] the oxygen-scavenging metal film is a titanium-containing film further including
[2] forming the titanium-containing film by reacting TiCl4 with H2 and
[3] removing a portion of the titanium-containing film by etching in a TiCl4 ambient.
19. (Currently Amended) The method of claim 18, further including
[1] forming the titanium metal film by reacting TiCl4 with H2 and
[2] removing the unreacted portions of the titanium metal film by etching in a TiCl4 ambient.
The prior art of (1) Fang in view of Kim and Pore, and (2) Fang in view of Kim, Pore, and Nieh, as explained above, teaches each of the features of claims 10 and 18.
As also explained above, Ameen teaches a method of making a titanium silicide contact to a semiconductor substrate (Fig. 2A-2C). The Ti metal film is deposited by CVD using TiCl4 with hydrogen (Ameen: col. 5, lines 26-46—especially lines 43-46). After the formation of the TiSi, the excess Ti is etched away using TiCl4 (Ameen: title, abstract, col. 5, line col. 63 to col. 6, line 43; Figs. 3-5).
Inasmuch as (1) each of Fang and Kim teaches that that the second metal film can be Ti and (2) Kim further teaches that the Ti film can be deposited using CVD and (3) each of Fang and Kim teaches that excess Ti can be removed after the silicidation reaction, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the process of deposition (i.e. TiCl4 with hydrogen) and subsequent excess Ti removal of (TiCl4) because Ameen teaches that these complementary deposition and removal processes are (1) very old and well known and (2) simplify the process by using the same compound, i.e. TiCl4, for both deposition and removal of Ti, and (3) are appropriate in association with formation of TiSi.
This is all of the limitations of claims 11 and 19.
V. Response to Arguments
Applicant's arguments filed 02/16/2026 have been fully considered but they are not persuasive.
With regard to claim 1, Applicant argues that Kim in view of Pore does not disclose the new limitations requiring the specific first and second resistivities (Remarks: p. 8). Examiner respectfully disagrees for the reasons indicated in the rejection, above, which points out that, because the process of Kim in view of Pore, is the same as the disclosed and claimed process in claim 1, the claimed resistivities resulting from the (1) reacting at the first temperature and (2) the annealing at the second temperature would be expected to be the same, making the claimed resistivities inherent and the burden of proof shifted to Applicant to prove the contrary.
With regard to claims 10 and 18, Applicant argues that the combination of Fang in view of Kim and Pore does not teach the newly added feature requiring an annealing step to reduce the resistivity of both of the initially formed Ni silicide and Ti silicide because Pore does not mention annealing a Ti silicide (Remarks: p. 8-9). Examiner respectfully disagrees because, at stated in the rejection, because the nickel silicides and the titanium silicides on the source/drain regions of adjacent MOSFETs are formed simultaneously in Fang, the modifications of the two-step anneal with the cleaning step in between the annealing steps would remove unreacted titanium along with the TiOx, as well as perform a two-step anneal on the Ti layer 223 of Fang to produce, by the first anneal, the higher-resistivity phase of Ti silicide and, by the second anneal, the lower resistivity phase of Ti silicide.
Based on the foregoing, Applicant’s arguments are not found persuasive.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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