Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 12/29/2025, in which: claims 1, 17, and 18 are amended; and the rejection of the claims are traversed. Claims 1-18 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 filed 12/29/2025 have been fully considered and are persuasive. The rejection of claims 1 and 17 has been withdrawn.
Applicant’s arguments filed 12/29/2025 with respect to the rejection(s) of claim 18 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Jo et al, US 20210202631.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 18 is/are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Jo et al, US 20210202631, hereafter ‘Jo’.
Regarding claim 18, Jo discloses : An electronic device comprising: a pixel circuit including(Fig. 4a, #PX) : a driving transistor(#DT); and a switching transistor(#ST); and a light emitting element electrically connected to the pixel circuit(#LD), the light emitting element including : an anode electrode(#AE); a light emitting layer(#EML); and a cathode electrode(#CE), wherein a first gate electrode of the driving transistor is electrically connected to the switching transistor to be applied with a gate signal(#GE2 with #ST connected to #DT through #BE [0093]), the pixel circuit includes at least two electrode patterns to which the gate signal is applied(#BE connected to #GE2 [0099] and #GL1i electrically connected to gate electrodes [0183]), and the at least two electrode patterns overlap the anode electrode in a plan view(#BE and #GL1i shown to overlap #AE).
Allowable Subject Matter
Claims 1 and 17 allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, Jo et al, US 20210202631, hereafter ‘Jo’ discloses : A display device comprising: a pixel circuit layer including a base layer and a pixel circuit disposed on the base layer(Circuit layer to include circuit element layer [0115] with #SUB and #PXij); and a light emitting element layer disposed on the pixel circuit layer(#EML), the light emitting element layer including a light emitting element(#LD), wherein the pixel circuit layer includes: a lower auxiliary electrode layer(first conductive layer disposed on #SUB [0117]); an active layer(#ACT may be formed on #SUB [0117]); and an interlayer conductive layer(second conductive layer to include a plurality of electrodes [0126-0128]), the pixel circuit includes a driving transistor(#DT), the lower auxiliary electrode layer forms a first overlapped lower layer and a second overlapped lower layer(#LS and #BE).
Jo does not disclose : the interlayer conductive layer includes a first conductive portion that forms a gate electrode of the driving transistor and a second conductive portion that forms an anode connection layer electrically connected to an anode of the light emitting element, the first overlapped lower layer overlaps the gate electrode in a plan view and physically contacts the anode connection layer, and the second overlapped lower layer is electrically isolated from the first overlapped lower layer. Therefore, claim 1 is allowed and claims 2-16 are allowed at least on their dependencies.
Regarding claim 17, Jo discloses : A display device(Fig. 4A) comprising: a pixel circuit(#PX) including: a driving transistor(#DT); a switching transistor(#ST); and a storage capacitor(#CST); and a light emitting element(#LD) electrically connected to the pixel circuit, the light emitting element including: an anode electrode(#AE); a light emitting layer(#EML); and a cathode electrode(#CE), wherein the storage capacitor includes an upper electrode(#UE) and a lower electrode(#BE), a gate electrode of the driving transistor(#GE2) is electrically connected to the switching transistor(#DT electrically connected to #ST through #BE [0094], the pixel circuit includes an overlapped lower layer disposed with the lower electrode in a same layer(#LS disposed on same layer as #BE), the overlapped lower layer overlapping the gate electrode in a plan view(#LS shown to overlap #GE2), and the gate electrode(#GE2) is electrically connected to the lower electrode, and is not electrically connected to the overlapped lower layer(#GE2 connected to #BE [0085]).
Jo does not disclose : the interlayer conductive layer includes a first conductive portion that forms a gate electrode of the driving transistor and a second conductive portion that forms an anode connection layer electrically connected to the anode electrode of the light emitting element, and the overlapped lower electrode layer physically contacts the anode connection layer. Therefore, claim 17 is allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897