DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Georgakos et al. (United States Patent Application Publication No. US 2003/0007386 A1, hereinafter “Georgakos”).
In reference to claim 11, Georgakos discloses a structure which meets the claim in figures 2-5. Figure 3 of Georgakos discloses a memory device which comprises a plurality of first memory cells (along channel layer (AA) on the left) arranged along a first lateral direction (top to bottom). There is a plurality of second memory cells (along channel layer (AA) on the right) arranged along the first lateral direction (top to bottom) and separated apart from the plurality of first memory cells along a second lateral direction (left to right) perpendicular to the first lateral direction (top to bottom). Fig. 10B is a cross-section of the plurality of second memory cells. Fig. 3 shows that each of the plurality of first and second memory cells comprises a first via-like structure (K on D1, topmost unlabeled contact on D2) and a second via-like structure (K on S1, topmost unlabeled contact on S2). The first via-like structure (K on D1, topmost unlabeled contact on D2) and second via-like structure (K on S1, topmost unlabeled contact on S2) are laterally separated apart along a third lateral direction that is clockwise tilted from the first lateral direction (top to bottom) with a first positive angle. With fig. 5 of Georgakos turned upside down, the second via-like structure (K on S1, topmost unlabeled contact on S2) is disposed directly above a conductive layer (4 - which represent source lines S1 or S2 in fig. 3) in an axial direction.
With regard to claim 12, fig. 3 shows that there is a first bit line (D1) extending along the first lateral direction (top to bottom) and in electrical connection with the first via-like structure (K on D1) of each of the plurality of first memory cells. There is a second bit line (D2) extending along the first lateral direction (top to bottom) and in electrical connection with the first via-like structure (topmost unlabeled contact on D2) of each of the plurality of second memory cells.
In reference to claim 13, fig. 3 shows that each of the plurality of first and second memory cells comprises a third via-like structure (note unlabeled contacts on D1 and D2 along line V-V), in direct contact with the channel layer (AA) that is disposed along the first edge of the channel layer (AA). The second via-like structure (K on S1, topmost unlabeled contact on S2) and the third via-like structure (note unlabeled contacts on D1 and D2 along line V-V) are laterally separated apart along a fourth lateral direction that is counterclockwise tilted from the second lateral direction (top to bottom) with a second positive angle.
With regard to claim 14, the first and second positive angles are each less than 90 degrees.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Georgakos in view of Lam (USPN 6,352,895 B1, hereinafter “Lam”).
In reference to claim 15, fig. 2-5 of Georgakos show that the plurality of first memory cells (along channel layer (AA) on the left) and the plurality of second memory cells (along channel layer (AA) on the right) each includes multiple non-volatile memory transistors. Fig. 4 shows the cross-section of each single non-volatile memory transistor with floating and control gates. Georgakos does not disclose implementing a non-volatile memory transistor with a capacitor in the plurality of first memory cells (along channel layer (AA) on the left) and the plurality of second memory cells (along channel layer (AA) on the right). However Lam discloses implementing a non-volatile memory transistor with a capacitor which enhances coupling the source to the floating gate (column 1, lines 7-16) in order to attain read current uniformity and a functioning floating gate channel in a memory cell with a small size. Lam further discloses that these are known goals in the art (column 1, lines 66-67, column 2, lines 1-26). In view of Lam, it would therefore be obvious to implement a non-volatile memory transistor with a capacitor in the plurality of first memory cells and the plurality of second memory cells disclosed by Georgakos.
With regard to claim 16, in the device of Georgakos constructed in view of Lam, a first end of the transistor is connected to the first via-like structure (fig. 2-5 of Lam: K on D1, topmost unlabeled contact on D2), and a second end of the transistor is coupled to the capacitor through the second via-like structure (fig. 2-5 of Lam: K on S1, topmost unlabeled contact on S2).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Georgakos in view of Lam as applied to claim 15 above and further in view of Tsai et al. (United States Patent Application Publication No. US 2024/0099035 A1, hereinafter “Tsai”).
In reference to claim 17, in the device of Georgakos constructed in view of Lam, the memory transistor and the capacitor are formed over a semiconductor substrate (1 – fig. 4 of Georgakos). Neither Georgakos nor Lam discloses implementing devices in a back-end-of-line (BEOL) network. However Tsai discloses that forming memory devices in a back-end-of-line (BEOL) network leads to increased memory density (p. 1-2, paragraph 19) which is desirable in the art (p. 1, paragraph 3). In view of Tsai, it would therefore be obvious to implement the memory transistor and the capacitor in a back-end-of-line (BEOL) network in the device of Georgakos constructed in view of Lam.
Allowable Subject Matter
Claims 1-10 and 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device which comprises a conductive layer which extends along a first lateral direction, a gate dielectric layer disposed over the conductive layer, a channel layer disposed over the gate dielectric layer which extends along a second lateral direction perpendicular to the first lateral direction, in combination with the suggested positioning of first and second via-like structures that are in direct contact with the channel layer as described by the applicant in claim 1. In the examiner’s opinion, it would also not be obvious to implement a semiconductor device which comprises a conductive layer which extends along a first lateral direction, a gate dielectric layer disposed over the conductive layer, first and second channel layers disposed over the gate dielectric layer which extend along a second lateral direction perpendicular to the first lateral direction, in combination with the suggested positioning of first and second via-like structures as described by the applicant in claim 18.
Response to Arguments
Applicant's arguments filed April 8, 2026 have been fully considered but they are not persuasive. The applicant has amended claim 11 to further state that, “at least one of the first via-like structure or the second via-like structure is disposed directly above a conductive layer in an axial direction.” The examiner notes that the previous iteration of claim 11 did not describe a conductive layer. The applicant argues that the control layer (CG) in fig. 3 of Georgakos does not meet the newly claimed conductive layer limitation in claim 11 (p. 9-10 of the response). However the above Office action does not use control layer (CG) in fig. 3 of Georgakos as the conductive layer. Instead the above rejection of claim 11 points out fig. 3 and 5 of Georgakos which disclose a conductive layer in the form of any one of the source lines (4 - which represent S1 or S2 in fig. 3) that does anticipate amended claim 11. Therefore claims 11-17 stand rejected in the above Office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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