DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-19 in the reply filed on 1/22/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/6/2023, 6/3/2024 and 9/27/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 and 12-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Adam et al. US 2007/0284674.
Re claim 1, Adam teaches a structure (fig2) comprising:
a semiconductor substrate (120, fig3, [19]);
a device (102, fig2, [18]) comprising an active region (106 and 150 under 160, fig6 and 8, [18, 22]); and
a porous semiconductor material (168, fig8, [23]) within the semiconductor substrate and surrounding the active region of the device (region with 106 and 150 under 160, fig8, [18]).
Re claim 2, Adam teaches the structure of claim 1, wherein the porous semiconductor material comprises porous Si material (168, fig8, [23]).
Re claim 3, Adam teaches the structure of claim 2, further comprising trench isolation structures (182, fig9B, [24]) surrounding the porous semiconductor material (168, fig9B, [23]).
Re claim 4, Adam teaches the structure of claim 1, wherein the device comprises a heterojunction bipolar transistor (102, fig2, [18]) and the active region comprises a collector region (left and right 106, fig2 and 4, [19]) surrounding the porous semiconductor material (168, fig8, [23]).
Re claim 5, Adam teaches the structure of claim 4, wherein the collector region comprises defect free single crystalline semiconductor material (center 106 with defect remove anneal 154, fig6, [22]).
Re claim 6, Adam teaches the structure of claim 1, wherein the device comprises a heterojunction bipolar transistor (102, fig2, [18]) comprising a collector region (center 106, fig2 and 8, [18]) separated from an extrinsic base region (190, fig2, [25]) by an intrinsic base region (104, fig2, [25]), wherein at least the intrinsic base region (104, fig2, [25]) comprises the active region surrounded by the porous semiconductor material (168, fig9B, [23]).
Re claim 7, Adam teaches the structure of claim 6, wherein the collector region comprises a defect free single crystalline semiconductor material (center 106 with defect remove anneal 154, fig6, [22]) and the intrinsic base region comprises a single crystalline semiconductor material (104, fig8, [6, 23]) in contact with the collector region.
Re claim 8, Adam teaches the structure of claim 6, wherein the porous semiconductor material is under the active region (168 under 150 between 160 and 106, fig6 and 8, [23]).
Re claim 9, Adam teaches the structure of claim 6, further comprising defective semiconductor material (150 after porous etching without the defect removing anneal, fig6, [22]) in contact with the porous semiconductor material (124/168, fig6 and 8, [23]) and separating the porous semiconductor material (124/168, fig6 and 8, [23]) from the intrinsic base region (160/104, fig2 and 8, [25]).
Re claim 12, Adam teaches a structure (fig2) comprising:
a semiconductor material (120, fig3, [19]);
a heterojunction bipolar transistor (102, fig2, [18]) comprising:
a collector region (center 106 with defect remove anneal 154, fig6, [22]) of defect free single crystalline semiconductor material over the semiconductor material;
an intrinsic base region (104, fig2, [25]) above the collector region;
an extrinsic base region (190, fig2, [25]) above the intrinsic base region; and
an emitter (192, fig2, [25]) above the intrinsic base region; and
porous semiconductor material (168, fig8, [23]) over the semiconductor material and surrounding at least the collector region (center 106, fig2, [22]).
Re claim 13, Adam teaches the structure of claim 12, wherein the porous semiconductor material (168, fig8, [23]) is under the intrinsic base region (104, fig8, [25]) and comprises porous Si material ([23]).
Re claim 14, Adam teaches the structure of claim 13, wherein the intrinsic base region comprises a single crystalline semiconductor material (104, fig8, [6, 23]).
Re claim 15, Adam teaches the structure of claim 12, wherein the porous semiconductor material (124/168, fig8, [23]) surrounds the intrinsic base region (104, fig8, [6, 23]).
Re claim 16, Adam teaches the structure of claim 12, further comprising defective semiconductor material (150 after porous etching, fig6, [22]) between the porous semiconductor material (124/168, fig8, [23]) and the intrinsic base region (104, fig8, [25]).
Re claim 17, Adam teaches the structure of claim 12, further comprising trench isolation structures (182, fig9B, [24]) surrounding the porous semiconductor material (168, fig9B, [23]).
Re claim 18, Adam teaches the structure of claim 17, wherein the semiconductor material (106, fig9B, [19]) surrounds the porous semiconductor material (168, fig9B, [23]) and includes a collector contact region (right side 106, fig2 and 4) which is electrically connected to a contact (fig2), outside of the shallow trench isolation structures (182, fig2 and 9B, [24]).
Re claim 19, Adam teaches the structure of claim 12, wherein the extrinsic base material (190, fig2, [25]) surrounds the emitter (192, fig2, [25]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Voldman US 2008/0111154 and Adam et al. US 2007/0284674.
Re claim 10, Voldman teaches a heterojunction bipolar transistor (20, fig1, [72]) and a transistor (FET of 40, fig1, [72]) and the active region (24 and 41, fig1, [70, 72]) comprises at least a channel region (region between 52 and 54, fig1, [72]) of a gate structure (58, fig1, [72]).
Voldman does not explicitly show detail of the HBT structure.
Adam teaches a HBT structure (fig2) comprising:
a semiconductor substrate (120, fig3, [19]);
a device (102, fig2, [18]) comprising an active region (106 and 150 under 160, fig6 and 8, [18, 22]); and
a porous semiconductor material (168, fig8, [23]) within the semiconductor substrate and surrounding the active region of the device (region with 106 and 150 under 160, fig8, [18]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Voldman and Adam to replace the HBT of Voldman with the HBT of Adam and form porous layer as STI region. The motivation to do so is to achieve low base resistance and low collector to base capacitance (Adam, [25]).
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2013/0285112 and Adam et al. US 2007/0284674.
Re claim 11, Lee teaches a structure (fig1) comprising:
a semiconductor substrate (102, fig1, [15]);
a device (SCR 100-1, fig1, [15]) comprising an active region (region between STI 116-3 and 116-4, fig1, [19]); and
wherein the device comprises a silicon controlled rectifier (SCR 100-1, fig1, [15]) and the active region comprises at least wells (106, 108, fig1, [17]) connecting to an anode (110, fig1, [19]) and a cathode (112, fig1, [19]).
Lee does not explicitly show a porous semiconductor material within the semiconductor substrate and surrounding the active region of the device .
Adam teaches a porous semiconductor material (168, fig8, [23]) within the semiconductor substrate and surrounding the active region of the device (region with 106 and 150 under 160, fig8, [18]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee and Adam to form porous layer around STI region to adjust the size of 110, 112 and 114 formed. The motivation to do so is to adjust anode/cathode contacts independent to the size of the isolation region and achieve low resistance for the contacts (Adam, [25]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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