DETAILED ACTION
This Office Action is in response to the Election and Amendment filed on October 20, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 17-20 and new claims 21-36 in the reply filed on October 20, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17, 21, and 24-36 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matsuo (WO 2023/105935 A1).
In re claim 17, Matsuo discloses (figs. 4, 5, 7, 14); Translation, excerpt below) a method of forming an integrated circuit (IC) device, comprising: implanting dopants (41, PD) in a first substrate (10) in a first IC chip to form a photodetector array (PD1, PD2, PD3, etc.) having a plurality of pixel blocks disposed in rows and columns; forming a first interconnect structure (15, 16, 17, 18) over the first substrate, the first interconnect structure comprising a first plurality of conductive pads (17) surrounded by a first dielectric layer (19); forming a first plurality of corrugated shield lines (16; read excerpt 1 below) respectively directly between the conductive pads (17 and another 17) and within a single row of the plurality of pixel blocks; forming a second interconnect structure (24, 25, 26, 27) on a second IC chip (20) , the second interconnect structure comprising a second plurality of conductive pads (24) and a second plurality of corrugated shield lines (27; read excerpt below) surrounded by a second dielectric layer (28); turning the first IC chip over and placing the first IC chip on the second IC chip such that the first plurality of conductive pads (17) is facing the second plurality of conductive pads (24); and bonding the first IC chip to the second IC chip at a bonding interface (between 19 and 28), wherein the second plurality of conductive pads is bonded to the first plurality of conductive pads at the bonding interface, and wherein the first and second plurality pluralities of corrugated shield lines isolate portions of the first and second plurality of conductive pads from one another (see the excerpt 2 below; the lines (16, 27 provide EM shielding).
This Excerpt 1 is provided below because the translation does not use page, paragraph or line numbers.
FIG. 4 shows an example of a cross-sectional configuration in the vertical direction of the imaging device 1. As shown in FIG. FIG. 4 illustrates a cross-sectional configuration of a portion facing the pixel region 13 (sensor pixel 12 ) and a cross-sectional configuration of a peripheral region of the pixel region 13 in the imaging device 1 . The imaging device 1 is configured by laminating a first substrate 10, a second substrate 20 and a third substrate 30 in this order. 40 and a receiving lens 50 . For example, one color filter layer 40 and one light receiving lens 50 are provided for each sensor pixel 12 . In other words, the imaging device 1 is a back-illuminated imaging device.
The first substrate 10 is configured by laminating an insulating layer 19 on a semiconductor substrate 11 . The first substrate 10 has an insulating layer 19 as an interlayer insulating film. The insulating layer 19 is provided between the semiconductor substrate 11 and the second substrate 20 . The first substrate 10 has a plurality of drive wirings 14 within an insulating layer 19 . The plurality of drive wirings 14 are provided for each row in the plurality of sensor pixels 12 arranged in a matrix. The semiconductor substrate 11 is composed of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well region 41 on a part of the surface and its vicinity, and has a conductivity different from that of the p-well region 41 in other regions (regions deeper than the p-well region 41). type photodiode PD. The p-well region 41 is composed of a p-type semiconductor region. The photodiode PD is composed of a semiconductor region of a conductivity type (specifically, n-type) different from that of the p-well region 41 . The semiconductor substrate 11 has a floating diffusion FD within the p-well region 41 as a semiconductor region of a conductivity type (specifically, n-type) different from that of the p-well region 41 .
The first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12 and has a floating diffusion FD for each one or more sensor pixels 12 . The first substrate 10 has a configuration in which a transfer transistor TR and a floating diffusion FD are provided on the front surface side of the semiconductor substrate 11 (the side opposite to the light incident surface side, the second substrate 20 side). The first substrate 10 has an element isolation portion that isolates each sensor pixel 12 . The element isolation portion is formed extending in the normal direction of the semiconductor substrate 11 (the direction perpendicular to the surface of the semiconductor substrate 11). The element isolation portion is provided between two sensor pixels 12 adjacent to each other. The element isolation section electrically isolates the sensor pixels 12 adjacent to each other. The element isolation part is made of silicon oxide, for example. The first substrate 10 further has, for example, a fixed charge film in contact with the back surface of the semiconductor substrate 11 . The fixed charge film is negatively charged in order to suppress the generation of dark current due to the interface level on the light receiving surface side of the semiconductor substrate 11 . The fixed charge film is formed of, for example, an insulating film having negative fixed charges. Examples of materials for such insulating films include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. A hole accumulation layer is formed at the interface on the light receiving surface side of the semiconductor substrate 11 by the electric field induced by the fixed charge film. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter layer 40 is provided on the back side of the semiconductor substrate 11 . The color filter layer 40 is provided, for example, in contact with the fixed charge film, and is provided at a position facing the sensor pixel 12 via the fixed charge film. The light-receiving lens 50 is provided, for example, in contact with the color filter layer 40 and is provided at a position facing the sensor pixels 12 via the color filter layer 40 and the fixed charge film.
The first substrate 10 has a plurality of FD through-wirings 15 and a plurality of VSS through-wirings 16 in the insulating layer 19 . A plurality of FD through-wirings 15 and a plurality of VSS through-wirings penetrate the insulating layer 19 . Each VSS through wire 16 is arranged in a gap between two adjacent FD through wires 15 among the plurality of FD through wires 15 . The first substrate 10 further has a plurality of FD junction electrodes 17 and a plurality of VSS junction electrodes 18 within the insulating layer 19 . Both the FD junction electrodes 17 and the VSS junction electrodes 18 are exposed on the surface of the insulating layer 19 . The FD junction electrode 17 corresponds to a specific example of the "first junction electrode" of the present disclosure. The VSS junction electrode 18 corresponds to a specific example of the "third junction electrode" of the present disclosure. A plurality of FD through-wirings 15 and a plurality of VSS through-wirings 16 are provided in a region facing the pixel region 13 . Each VSS junction electrode 18 is formed in the same plane as each FD junction electrode 17 . The VSS junction electrode 18 is arranged in a gap between two adjacent FD junction electrodes 17 among the plurality of FD junction electrodes 17 .
When one floating diffusion FD is provided for a plurality of sensor pixels 12 sharing the readout circuit 22, a plurality of FD through-wirings 15 are provided for each of the plurality of sensor pixels 12 sharing the readout circuit 22. One is provided. When one floating diffusion FD is provided for one sensor pixel 12 , a plurality of FD through-wirings 15 are provided for each sensor pixel 12 .
Each FD through-wiring 15 is connected to the floating diffusion FD and the FD junction electrode 17 . When one floating diffusion FD is provided for a plurality of sensor pixels 12 sharing the readout circuit 22, a plurality of VSS through wires 16 are provided for each of the plurality of sensor pixels 12 sharing the readout circuit 22. One is provided. When one floating diffusion FD is provided for one sensor pixel 12 , a plurality of VSS through wires 16 are provided for each sensor pixel 12 . Each VSS through wire 16 is connected to the p-well region 41 and the VSS junction electrode 18 . In either case, one VSS through wire 16 is provided for each readout circuit 22 .
The second substrate 20 is configured by laminating an insulating layer 28 on a semiconductor substrate 21 . The second substrate 20 has an insulating layer 28 as an interlayer insulating film. The insulating layer 28 is provided between the semiconductor substrate 21 and the first substrate 10 . The semiconductor substrate 21 is composed of a silicon substrate. The second substrate 20 has one readout circuit 22 for every four sensor pixels 12 . The second substrate 20 has a configuration in which a readout circuit 22 is provided on the surface side portion of the semiconductor substrate 21 . The second substrate 20 is bonded to the first substrate 10 with the surface of the semiconductor substrate 21 facing the front surface of the semiconductor substrate 11 .
The second substrate 20 has a plurality of FD through-wirings 26 and a plurality of VSS through-wirings 27 in an insulating layer 28 . A plurality of FD through-wires 26 and a plurality of VSS through-wires 27 penetrate the insulating layer 28 . Each VSS through wire 27 is arranged in a gap between two adjacent FD through wires 26 among the plurality of FD through wires 26 . The second substrate 20 further has a plurality of FD junction electrodes 24 and a plurality of VSS junction electrodes 25 within the insulating layer 28 . Both the FD junction electrodes 24 and the VSS junction electrodes 25 are exposed on the surface of the insulating layer 28 . The FD junction electrode 24 corresponds to a specific example of the "second junction electrode" of the present disclosure. The VSS junction electrode 25 corresponds to a specific example of the "fourth junction electrode" of the present disclosure. The plurality of FD junction electrodes 24 are provided one by one for each FD junction electrode 17 of the first substrate 10 . The FD junction electrode 24 is electrically connected to the FD junction electrode 17 . The FD junction electrode 24 and the FD junction electrode 17 are made of copper, for example, arranged to face each other, and joined to each other. The VSS junction electrode 25 is electrically connected to the VSS junction electrode 18 of the first substrate 10 . The VSS junction electrode 25 and the VSS junction electrode 18 are made of copper, for example, arranged to face each other, and joined to each other. Each VSS junction electrode 25 is formed, for example, in the same plane as each FD junction electrode 24 . The VSS junction electrode 25 is arranged in a gap between two adjacent FD junction electrodes 24 among the plurality of FD junction electrodes 24 . The sensor pixel 12 and the readout circuit 22 are electrically connected to each other by bonding the FD junction electrodes 17 and 24 together.
This Excerpt 2 is provided below because the translation does not use page, paragraph or line numbers.
(2-3. Modification 3)
FIG. 14 schematically shows another example of the vertical cross-sectional configuration of the imaging device 1 corresponding to line BB' shown in FIG. In the above embodiment, the VSS junction electrodes 18 and 25 are exposed on the surfaces of the insulating layers 19 and 28 and joined to each other, but the present invention is not limited to this.
For example, as shown in FIG. 14, the via V3 between the VSS junction electrode 25 on the second substrate 20 side and the wiring layer M2 may be omitted. Even with such a configuration, the VSS through-wirings 16 and 27 can function as shields for reducing signal interference between the FD through-wirings 15 adjacent to each other. and signal interference between the FD penetrating wires 15 and 26 connected thereto can be reduced.
In re claim 21, Matsuo discloses (figs. 4, 5, 7, 14); Translation, excerpt above) a method of forming an integrated device, comprising: forming a first interconnect structure over a first substrate (10), the first interconnect structure comprising a first plurality of conductive contacts (15, 17) in a first dielectric layer (19) and spaced from each other in a first direction; forming a first corrugated shield line (16, 18) concurrent with forming the first plurality of conductive contacts, the first corrugated shield line having a first shield node (18) between and in a line with a first conductive pad (17) and a second conductive pad (another 17) of the first plurality of conductive contacts in the first direction, second shield nodes (another 18) in lines with the first conductive pad and the second conductive pad in a second direction perpendicular to the first direction and in a line with a third conductive pad (another 17) in the first direction, and shield line segments (fig. 7, line U between 18) extending between the first shield node (18) and the second shield nodes (18); forming a second interconnect structure on a second substrate (20), the second interconnect structure comprising a second plurality of conductive contacts (24) in a second dielectric layer (28); and bonding the second plurality of conductive contacts to the first plurality of conductive contacts at a bonding interface (between 19 and 28; read he excerpt 1 above for the method including bonding).
In re claim 24, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) forming a second corrugated shield line in the second dielectric concurrent with forming second plurality of conductive contacts, wherein the first corrugated shield line and the second corrugated shield line are bonded at the bonding interface concurrent with the bonding of the first and second plurality of conductive contacts.
In re claims 25-27, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt below) a a line drawn at a 45 degree angle from the first direction on the first conductive pad also extends onto the second conductive pad (since the drawn line can extend to any of the pads in the array of pads). The line drawn at the 45 degree angle extending on the first conductive pad and the second conductive pad also extends across a shield line segment extending between the first shield node and one of the second shield nodes. The first shield node is spaced from the second shield nodes in the first direction and in the second direction (since there are multiple shield nodes throughout the array_.
In re claim 28, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) a method of forming an integrated device, comprising: implanting dopants in a first substrate to form a photodetector array (PD1, PD2, PD3, etc) having a plurality of pixel blocks disposed a row extending in a first direction; forming a first interconnect structure over the first substrate (10), the first interconnect structure (15, 16, 17, 18) comprising a first plurality of conductive pads (17, 18) surrounded by a first dielectric layer (19), wherein a first portion of the first plurality of conductive pads (17) are in a first line extending in the first direction, and wherein a second portion of the first plurality of conductive pads (another 17) are in a second line extending in the first direction that is spaced from the first line in a second direction perpendicular to the first direction; and forming a first shield line (16, 18) having first shield nodes in the first line between conductive pads of the first portion, second shield nodes (another 16, 18) in the second line between conductive pads of the second portion, and shield segments (line U) extending between the first shield nodes and the second shield nodes to form a continuous structure extending between the first portion of the first plurality of conductive pads and the second portion of the first plurality of conductive pads.
In re claim 29, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) the first shield line and the first plurality of conductive pads are formed concurrently.
In re claim 30, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) pixel blocks of the row alternate between being coupled to a conductive pad of the first portion of the plurality of conductive pads in the first line and being coupled to a conductive pad of the second portion of the plurality of conductive pads in the second line.
In re claim 31, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) wherein first shield nodes of the first line are coupled by the shield segments to the second shield nodes in the second line, and wherein shield nodes of the first line are separated in the first direction and in the second direction from shield nodes of the second line.
In re claim 32, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) wherein a first conductive pad is closer to three shield nodes of the first shield line than other conductive pads of the plurality of conductive pads.
In re claim 33, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) comprising implanting dopants into the first substrate to form a floating diffusion region (FD) coupled to more than one photodetector of the photodetector array before forming the first interconnect structure wherein after forming the first plurality of conductive pads, the floating diffusion region is coupled to a conductive pad of the first plurality of conductive pads.
In re claim 34, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) forming a second interconnect structure (24, 25) on a second substrate (20) and comprising a second plurality of conductive pads (24) surrounded by a second dielectric layer (28); and bonding the first plurality of conductive pads (17) to the second plurality of conductive pads (24).
In re claim 35, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) 35. forming a second shield line (25, 27) concurrent with forming the second plurality of conductive pads; and bonding the second shield line to the first shield line concurrent with bonding the first plurality of conductive pads to the second plurality of conductive pads.
In re claim 36, Matsuo discloses (figs. 4, 5, 7); Translation, excerpt above) forming a second interconnect structure (24, 25) on a second substrate (20) and comprising a plurality of contacts surrounded by a second dielectric layer (28); and bonding the plurality of contacts to the first plurality of conductive pads.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo (WO 2023/105935 A1) as applied to claims 17 and 21 above, and further in view of the cited case law.
In re claim 18, Matsuo does not specifically disclose the first dielectric layer is bonded to the second dielectric layer with van der Waals forces, and wherein the bonding of the first IC chip to the second IC chip further comprises performing an anneal to bond the second plurality of conductive pads to the first plurality of conductive pads. However bonding using van der Waals forces and performing an anneal to bond are typical methods in the art of semiconductors to manufacture a semiconductor device.
In re claim 19, Matsuo does not specifically disclose the eight photodetectors of the photodetector array are electrically coupled to one conductive pad, wherein the eight photodetectors are within two 2-by-2 photodetector subarrays respectively coupled to a first and second floating diffusion node. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form any amount of photodetectors in any type of subarray, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 22, Matsuo shows all of the elements of the claims except wherein forming the first plurality of conductive contacts and the first corrugated shield line further comprises: forming and patterning a masking layer over the first dielectric layer, wherein the masking layer is patterned to have openings corresponding to top-down profiles of the first plurality of conductive contacts and the first corrugated shield line to be formed. The methods of forming and patterning a masking layer, then etching to form the contacts are typical methods used in the art of semiconductors to form interconnections between devices.
Allowable Subject Matter
Claims 20 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yanagita (US 9,508,770 B2), Fuji (US Pub. 2025/0228029 A1), Yang (US Pub. 2024/0355859 A1), Yang (US Pub. 2024/0347576 A1), Park (US Pub. 2024/0250104-A1), Wei (US Pub. 2022/0367391 A1), Onuki (US Pub. 2021/0305303 A1), Wei (US Pub. 2019/0096830 A1), Ito (WO 2020175712 A2), and Yamashita (WO 2020100806 A1) also disclose various elements of the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815