DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 22 objected to because of the following informalities: the claim appears to have a typographical error "the p-doped portion of the semiconductor substrate that is that is more lightly p-doped than the deep p-well”. For the purpose of examination, the examiner will interpret the above limitation as " the p-doped portion of the semiconductor substrate more lightly p-doped than the deep p-well ".
Claim 25 objected to because of the following informalities: the claim appears to have a typographical error " the deep n-well is disposed between the drain region and the deep n-well". For the purpose of examination, the examiner will interpret the above limitation as "the deep n-well is disposed between the drain region and the deep p-well ".
Claim 35 objected to because of the following informalities: the claim appears to have a typographical error " the n-well is disposed between the drain region and the n-well ". For the purpose of examination, the examiner will interpret the above limitation as " the n-well is disposed between the drain region and the p-well "
Appropriate correction is required.
Election/Restrictions
Applicant’s election without traverse of claims 19-20 in the reply filed on 10/1/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/7/2023 and 6/26/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 34-38 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. US 2015/0048449.
Re claim 34, Jeon teaches a method of forming an integrated circuit device (fig3), the method comprising:
forming a transistor (LDMOS, fig3) on a semiconductor substrate (1 and 15, fig3, [45]) having a p-doped region (p-type 1, fig3, [45]), the transistor comprising a gate electrode (G, fig3, [45]), a drain region (D, fig3, [48]), a drift region (n-type 15 around D and 21, fig3, [48]), and a channel region (region between S and D under gate G, fig3, [48]), wherein;
the drift region (n-type 15 around D and 21, fig3, [48]), the drain region (D, fig3, [48]), and the channel region (region between S and D, fig3, [48]) are in the semiconductor substrate (1 and 15, fig3, [45]);
the drift region (n-type 15 around D and 21, fig3, [48]) is directly over the p-doped region (p-type 1, fig3, [45]);
the drift region (n-type 15 around D and 21, fig3, [48]) and the drain region (D, fig3, [48]) have n-type doping;
the channel region has n-type doping (part of n- 15 directly under G, fig3); and
the drift region (n-type 15 around D and 21, fig3, [48]) and the p-doped region (p-type 1, fig3, [45]) of the semiconductor substrate provide a first vertical PN junction that is beneath the gate electrode (G, fig3, [48]); and
forming a second vertical PN junction (5/13, fig3, [51]), wherein:
the second vertical PN junction is formed by an n-well (5, fig3, [51]) over a p-well (13, fig3, [51]);
the drain region (D, fig3, [48]) is disposed directly over the second vertical PN junction (5/13, fig3, [51]);
the n-well (5, fig3, [51]) is distinct from the drain region (D, fig3, [48]);
the n-well has a higher dopant concentration than the drift region (5 with greater concentration than 15, fig3, [51]);
the p-well has a higher dopant concentration than the p-doped region (13 with greater concentration than 1, fig3, [51]); and
the p-well (13, fig3, [51]) extends to the p-doped region (p-type 1, fig3, [45]).
Re claim 35, Jeon modified above teaches the method of claim 34, wherein a portion of the drift region (n- 15 around D and 21, fig3, [48]) having a lower dopant concentration than the drain region (N+ D, fig3, [48]) and the n-well (5, fig3, [51]) is disposed between the drain region (D, fig3, [48]) and the p-well (13, fig3, [51]).
Re claim 36, Jeon modified above teaches the method of claim 34, wherein the second vertical PN junction (5/13, fig3, [51]) is deeper than the first vertical PN junction (15/1, fig3).
Re claim 37, Jeon modified above teaches the method of claim 34, wherein the second vertical PN junction lowers a breakdown voltage of the transistor ([54]).
Re claim 38, Jeon modified above teaches the method of claim 34, wherein the p-well (13, fig3, [51]) is electrically coupled to a body contact region (P+ 31, fig3, [49]) with p-type doping through portions of the semiconductor substrate that have p-type doping (25, 7 and 1, fig3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-21, 23 and 25-33 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2015/0243780 in view of Wang et al. US 2019/0371939.
Re claim 19, Lin teaches a method of forming an integrated circuit device (fig3(c)), the method comprising:
doping a semiconductor substrate (p-type 102, fig3(c), [25]) to form a drift region (n-type 104, fig3(c), [25]) and a channel region (region between 106 and 104 under gate 116, fig3(c), [23, 33]) that have a junction (junction between 102 and 104, fig3(c), [23]) adjacent a surface of the semiconductor substrate (top surface of 102, fig3(c));
forming a gate stack (116 and 118, fig3(c), [33]) on the semiconductor substrate;
patterning the gate stack to form a gate (116, fig3(c), [33]) that is over the junction;
implanting a deep p-well (P+ 132, fig3(c), [27]);
implanting a deep n-well (n+ 130, fig3(c), [27]) above the deep p-well (p+ 132, fig3(c), [27]), wherein the deep p-well and the deep n-well have higher dopant concentrations than the drift region (n-type 104, fig3(c), [27]); and
implanting dopants to form a drain region (112, fig3(c), [34]) above the deep p-well (p+ 132, fig3(c), [27]) and the deep n- well (n+ 130, fig3(c), [27]).
Lin does not explicitly show forming a spacer abutting the gate;
Wang teaches forming a spacer (441, fig2A, [41]) abutting the gate (431, fig2A, [41]) used as hard mask to form ion implantation regions around the gate ([41]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin and Wang to add gate spacers abutting the gate used as hard mask to form ion implantation regions around the gate (Wang, [41]).
Re claim 20, Lin modified above teaches the method of claim 19, wherein the deep p-well and the deep n-well are aligned to the spacer (Lin, 130/132 aligned under right side of gate 116 with spacer of Wang added, fig3(c)).
Re claim 21, Lin modified above teaches a method of forming an integrated circuit device (fig3(c) or fig3(d)), the method comprising:
receiving a semiconductor substrate having a surface (top surface of p-type 102, fig2(a), [25]);
doping an upper portion of the semiconductor substrate (implant n-type 104, fig2(a), [25]) to provide a surface adjacent p-well (top part of p-type 102, fig2(a), [25]) and a surface adjacent n-well (n-type 104, fig2(a), [25]);
forming a gate stack (116 and 118, fig3(c) or 3(d), [33]) on the semiconductor substrate, wherein the gate stack comprises a gate dielectric layer (118, fig3(c) or 3(d), [33]) and an electrode layer (116, fig3(c) or 3(d), [33]);
patterning the gate stack to form a gate (116 and 118, fig3(c) or 3(d), [33]) having a drain side (side of 116 facing 112, fig3(c) or 3(d), [34]) and a source side (side of 116 facing 120, fig3(c) or 3(d), [34]), wherein the drain side is over the surface adjacent n-well (n-type 104, fig3(c) or 3(d), [25]) and the source side is over the surface adjacent p-well (top part of p-type 102, fig3(c) or 3(d));
Lin does not explicitly show forming a spacer around the gate;
Wang teaches forming a spacer (441, fig2A, [41]) abutting the gate (431, fig2A, [41]) used as hard mask to form ion implantation regions around the gate ([41]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin and Wang to add gate spacers abutting the gate used as hard mask to form ion implantation regions around the gate ([41]).
Lin modified above teaches while masking (152, fig2(e), [25]) the surface adjacent p-well on the source side, doping on the drain side to form a deep p-well (P+ 132, fig2(e), [22]) and a deep n-well (n+ 130, fig2(e), [22]), wherein the deep n-well (n+ 130, fig2(e), [22]) extends from the surface adjacent n-well to the deep p-well (P+ 132, fig2(e), [22]), the deep p-well (P+ 132, fig2(e), [22]) is below the deep n-well (n+ 130, fig2(e), [22]), and the deep p-well (P+ 132, fig2(e), [22]) extends from the deep n-well (n+ 130, fig2(e), [22]) to a p-doped portion of the semiconductor substrate (p-type 102 under 130/132, fig2(e), [25]) that is that is more lightly p-doped than the deep p-well (P+ 132, fig2(e), [22]);
doping to form a drain region (112, fig3(c) or 3(d), [34]) for the gate within the surface adjacent n-well (n-type 104, fig3(c) or 3(d), [25]) directly over the deep n-well (n+ 130, fig3(c) or 3(d), [22]) and the deep p-well (P+ 132, fig3(c) or (3d), [22]); and
doping on the source side to form a source region (108 and 110, fig3(c) or 3(d), [34]) for the gate within the surface adjacent p-well (top part of p-type 102, fig3(c) or 3(d), [25]).
Re claim 23, Lin modified above teaches the method of claim 21, wherein the p-doped portion (p-type 102 under 130/132, fig2(e), [25]) of the semiconductor substrate that is that is more lightly p-doped than the deep p-well (P+ 132, fig2(e), [22]) extends to the surface adjacent p-well (top part of p-type 102, fig2(a), [25]).
Re claim 25, Lin modified above teaches the method of claim 21, wherein a portion of the surface adjacent n-well (n-type 104, fig2(a), [25]) that is more lightly doped than the drain region (112, fig3(c), [25, 34]) and the deep n-well (n+ 130, fig3(c), [22]) is disposed between the drain region (112, fig3(c), [34]) and the the deep p-well (132, fig3(c)).
Re claim 26, Lin modified above teaches the method of claim 21, wherein the drain region (112, fig3(d), [25, 34]) is narrower than the deep n-well (n+ 130, fig3(d), [22]).
Re claim 27, Lin modified above teaches the method of claim 21, wherein doping on the drain side to form a deep p-well (P+ 132, fig2(e), [22]) and a deep n-well (n+ 130, fig3(d), [22]) comprises doping in alignment with the spacer (Lin, 130/132 aligned under right side of gate 116 with spacer of Wang added, fig3(c)).
Re claim 28, Lin modified above teaches the method of claim 21, further comprising prior to formation of the gate stack (116 and 118, fig2(g) and 3(c), [33]), forming an oxide structure (114, fig2(g), [32]) at the surface of the semiconductor substrate, wherein the gate forms with the drain side over the oxide structure.
Re claim 29, Lin modified above teaches the method of claim 28, wherein doping on the drain side to form a deep p-well and a deep n-well comprises doping in alignment with the oxide structure (130/132 aligned under 114, fig3(c)).
Re claim 30, Lin modified above teaches the method of claim 29, wherein forming the oxide structure comprises oxidizing the semiconductor substrate to form a field oxide structure (114 by oxidation, fig2(g), [32]).
Re claim 31, Lin modified above teaches the method of claim 29, wherein forming the oxide structure comprises etching and deposition to form a shallow trench isolation structure (114 by deposition, fig2(g), [32]).
Re claim 32, Lin modified above teaches the method of claim 21, wherein the deep n-well (n+ 130, fig3(c), [22]) extends from the drain region (112, fig3(c), [25, 34]) to the deep p-well (P+ 132, fig3(c), [22]).
Re claim 33, Lin modified above teaches the method of claim 21, wherein forming the gate stack (116 and 118, fig2(g) and 3(c), [33]) comprises a supplemental oxide deposition (114, fig3(c), [32]), wherein the supplemental oxide deposition makes the gate dielectric layer (dielectric layer under 116 with thickness of 118 and 114, fig3(c)) thicker on the drain side of the gate than on the source side of the gate (thickness of 118, fig3(c)).
Claim(s) 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2015/0243780 in view of Wang et al. US 2019/0371939 and Bode et al. US 2014/0001546.
Re claim 22, Lin modified above teaches the method of claim 21, the p-doped portion (p-type 102 under 130/132, fig3(c), [25]) of the semiconductor substrate that is more lightly p-doped than the deep p-well (P+ 132, fig3(c), [22]).
Lin does not explicitly show wherein the semiconductor substrate comprises a buried-n layer below the p-doped portion of the semiconductor substrate that is that is more lightly p-doped than the deep p-well.
Bode teaches a buried-n layer (NBL 220, fig2, [40]) below the p-doped portion of the semiconductor substrate (216, fig2, [40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin, Wang and Bode to add a NBL layer under Lin 102 in fig3(c) to avoid disruption of adjacent circuit blocks (Bode, [41]).
Claim(s) 21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Bode et al. US 2014/0001546 and Lin et al. US 2015/0243780.
Re claim 21, Bode teaches method of forming an integrated circuit device (fig2), the method comprising:
receiving a semiconductor substrate (210, fig2, [35]) having a surface (212, fig2, [35]);
doping an upper portion of the semiconductor substrate to provide a surface adjacent p-well (p-type 234, fig2, [36]) and a surface adjacent n-well (n-type 232, fig2, [36]);
forming a gate stack (242, fig2, [36]) on the semiconductor substrate, wherein the gate stack comprises a gate dielectric layer ([36]) and an electrode layer (242, fig2, [36]);
patterning the gate stack to form a gate (242, fig2, [36]) having a drain side (side of 242 facing 236, fig2) and a source side (side of 242 facing 238, fig2, [36]), wherein the drain side is over the surface adjacent n-well (n-type 232, fig2, [36]) and the source side is over the surface adjacent p-well (p-type 234, fig2, [36]);
forming a spacer around the gate (gate spacer around 242, fig2).
Bode does not explicitly show while masking the surface adjacent p-well on the source side, doping on the drain side to form a deep p-well and a deep n-well, wherein the deep n-well extends from the surface adjacent n-well to the deep p-well, the deep p-well is below the deep n-well, and the deep p-well extends from the deep n-well to a p-doped portion of the semiconductor substrate that is that is more lightly p-doped than the deep p-well; doping to form a drain region for the gate within the surface adjacent n-well directly over the deep n-well and the deep p-well; and doping on the source side to form a source region for the gate within the surface adjacent p-well.
Lin teaches while masking (152, fig2(e), [25]) the surface adjacent p-well on the source side, doping on the drain side to form a deep p-well (P+ 132, fig2(e), [22]) and a deep n-well (n+ 130, fig2(e), [22]), wherein the deep n-well (n+ 130, fig2(e), [22]) extends from the surface adjacent n-well to the deep p-well (P+ 132, fig2(e), [22]), the deep p-well (P+ 132, fig2(e), [22]) is below the deep n-well (n+ 130, fig2(e), [22]), and the deep p-well (P+ 132, fig2(e), [22]) extends from the deep n-well (n+ 130, fig2(e), [22]) to a p-doped portion of the semiconductor substrate (p-type 102 under 130/132, fig2(e), [25]) that is that is more lightly p-doped than the deep p-well (P+ 132, fig2(e), [22]);
doping to form a drain region (112, fig3(c), [34]) for the gate within the surface adjacent n-well (n-type 104, fig3(c), [25]) directly over the deep n-well (n+ 130, fig3(c), [22]) and the deep p-well (P+ 132, fig3(c), [22]); and
doping on the source side to form a source region (108 and 110, fig3(c), [34]) for the gate within the surface adjacent p-well (top part of p-type 102, fig2(a) and 3(c), [25]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin and Bode to add in the deep p-well and deep n-well 130/132 to 232 of Bode in fig2 to increase the breakdown voltage and reduce the on -resistance (Lin, [24])
Re claim 24, Bode in view of Lin teaches the method of claim 21, wherein the gate is one of two gates (Bode, 242, fig2, [36]) that share the drain region (Bode, n-type 236, fig2, [36]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812