DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks and Amendments, filed 31 December 2025, with respect to the rejection(s) of the claim(s) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further search and consideration, a new ground(s) of rejection is made in view of newly discovered reference US 20170221786 A1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 12, 14, 16, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Shigeru Konishi et al. (US 20170221786 A1; hereinafter Konishi) in view of Vladimir Odnoblyudov et al. (US 2018/0204941 A1; hereinafter Odnoblyudov) and Wen-Qing Xu et al. (US 20240017524 A1; hereinafter Xu).
Regarding Claim 9, Konishi teaches a method (Fig. 1A-1F), comprising:
forming a supporting layer of amorphous silicon material, sputtered aluminum nitride material, or sputtered silicon material (layer 2 of amorphous silicon material; ¶0042, ¶0030) over a first substrate that comprises an aluminum nitride ceramic material (ceramic AlN substrate 1; ¶0042, ¶0023);
forming a silicon seed layer (single-crystal silicon semiconductor layer 4a formed to be separated by ion implantation and used for forming semiconductor devices; ¶0018, ¶0022, ¶0042) over a second substrate (single crystal semiconductor substrate 4b; ¶0042);
directly bonding the silicon seed second layer (4a) to the supporting layer (2) (as shown in Fig. 1E; ¶0042);
removing the second substrate (4b) (as shown in Fig. 1F; ¶0042),
wherein directly bonding the silicon seed layer (4a) to the supporting layer (2) comprises performing surface activated bonding (“applying surface-activation treatment by plasma treatment or the like to at least one or both of the surface of the amorphous film on a support substrate and the surface of a single-crystal semiconductor substrate” ¶0041-¶0042) using a plasma (7) on a surface of the supporting layer (2; as shown in Fig. 1C).
Konishi is silent about further forming a gallium nitride-based electronic structure over the silicon seed layer (4a).
However, forming electronic devices on a device layer of a manufactured substrate is well known in the art. In the same field of endeavor, Odnoblyudov teaches (Fig. 1) forming a GaN-based HEMT (¶0004, ¶0031, ¶0121) on a single crystal silicon layer (120; ¶0042, ¶0048, ¶0055) of a manufactured AlN ceramic substrate (110; which is a ceramic material chosen to match a CTE of one or more subsequent GaN epitaxial layers shown in Fig. 1; wherein growing GaN utilizes a core material of ceramic AlN as described in view of ¶0081).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the GaN-based HEMT of Odnoblyudov utilizing the substrate of Konishi in order to provide a functioning transistor with reduced defects due to the CTE matching of the substrate and epitaxial layers (Odnoblyudov; ¶0002-¶0006, ¶0026-¶0033).
Although Konishi is silent about the surface activated bonding using the plasma (7) creates dangling bonds on the supporting layer (2), this is well known. Xu teaches performing a surface activation process by exposing a top most layer (108) of amorphous silicon (¶0025) to a plasma to create dangling bonds (¶0028) in order to bond two substrates at low temperatures (¶0004). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the surface activation of Konishi utilizing the plasma creates dangling bonds in the amorphous silicon layer (as described in view of Xu), and/or it would have been obvious to create dangling bonds by the plasma in order to enable wafer bonding at low temperatures (Xu; ¶0004).
Regarding Claim 12, modified Konishi teaches the method of claim 9, but is silent about further comprising: forming a layer of silicon oxide surrounding a portion of the first substrate (Konishi; 1); forming a layer of polycrystalline silicon surrounding the layer of silicon oxide; and removing a portion of the layer of polycrystalline silicon such that a remaining portion of the layer of polycrystalline silicon is below the first substrate (Knishi; 1).
In the same field of endeavor, Odnoblyudov teaches forming a layer of silicon oxide (Odnoblyudov; Fig. 12; first adhesion layer 1212; wherein the adhesion layers are silicon oxide; ¶0082-¶0083) surrounding a portion of the first substrate (AlN substrate 1210, which is equivalent to AlN substrate 1 of Konishi or AlN substrate 110 of Odnoblyudov Fig. 1; wherein the substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945)); forming a layer of polycrystalline silicon (Odnoblyudov; Fig. 12; 1214; ¶0085) surrounding the layer of silicon oxide (1212) (as shown in Odnoblyudov Fig. 12); and removing a portion of the layer of polycrystalline silicon such that a remaining portion of the layer of polycrystalline silicon is below the first substrate (1210) (as described in Odnoblyudov ¶0085, wherein a remaining portion of the polysilicon layer is below 1210).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the steps of Odnoblyudov in the method of Konishi in order to provide the polysilicon layer below the ceramic substrate to allow electrostatic chucking of the ceramic substrate for use in conventional silicon semiconductor processing tools (Odnoblyudov ¶0087).
Regarding Claim 14, modified Konishi teaches the method of claim 12, further comprising: depositing additional silicon oxide (Odnoblyudov Fig. 12; second adhesion layer 1216 which is silicon oxide; ¶0083, ¶0088) to grow the layer of silicon oxide (Odnoblyudov; 1212, which would be grown by the deposition of 1216 after the removal of the top portion of polysilicon 1214 as done in ¶0085, thereby forming 1212+1216); and forming a layer of silicon nitride (Odnoblyudov; Fig. 12; silicon nitride layer 1218; ¶0090) surrounding the layer of silicon oxide (1212+1216) (as shown in Odnoblyudov Fig. 12).
Regarding Claim 16, modified Konishi teaches the method of claim 9, further comprising: performing a chemical mechanical polishing (Konishi; CMP performed on 2; ¶0030) on the supporting layer (Konishi; 2) before directly bonding the silicon seed layer (Konishi; 4a) to the supporting layer (Konishi; 2).
Regarding Claim 22, modified Konishi teaches the method of claim 9, but does not expressly disclose wherein the silicon seed layer (Konishi; 4a) has a (111) lattice structure. Even though the crystal orientation of the seed layer is not expressly disclosed, Odnoblyudov teaches a (111) orientation single crystal silicon layer that is suitable for GaN epitaxy (Odnoblyudov ¶0077). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the seed layer of Konishi be a (111) orientation (as in Odnoblyudov) in order to provide a good and suitable surface for GaN epitaxy.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shigeru Konishi et al. (US 20170221786 A1; hereinafter Konishi) in view of Vladimir Odnoblyudov et al. (US 2018/0204941 A1; hereinafter Odnoblyudov), Wen-Qing Xu et al. (US 20240017524 A1; hereinafter Xu), and Min-Ying Tsai et al. (US 2017/0194194 A1; hereinafter Tsai).
Regarding Claim 11, modified Konishi teaches the method of claim 9, but is silent regarding wherein removing the second substrate comprises: performing wafer grinding on the second substrate to reduce a height of the second substrate; and performing a wet etching process to remove the second substrate.
However, this is a standard process known in the art. In the same field of endeavor, Tsai teaches a method of bonding two substrates (Tsai; Fig. 4 and Fig. 5; substrates 10 and 40; ¶0026) and subsequently removing one of the bonded substrates (10) by grinding away 80-90% of the substrate material (which reduces the height of the substrate 10), followed by performing a wet etching process (as described in Tsai; ¶0028-¶0032).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the substrate removal steps of Tsai in the method of Konishi in order to improve the throughput of the method (Tsai; ¶0032).
Claims 15, 23-25, and 27-28, and 31-33 are rejected under 35 U.S.C. 103 as being unpatentable over Shigeru Konishi et al. (US 20170221786 A1; hereinafter Konishi) in view of Vladimir Odnoblyudov et al. (US 2018/0204941 A1; hereinafter Odnoblyudov), Wen-Qing Xu et al. (US 20240017524 A1; hereinafter Xu), and Hubert Moriceau et al. (US 2019/0206678 A1; hereinafter Moriceau).
Regarding Claim 15, modified Konishi teaches the method of claim 14, but is silent about further comprising: removing a portion of the layer of silicon nitride (Odnoblyudov; 1218) formed over the silicon seed layer (Konishi; 4a); and removing a portion of the layer of silicon oxide (Odnoblyudov; 1212+1216) formed over the silicon seed layer (Konishi, 4a).
In the same field of endeavor, Moriceau teaches a method (Fig. 2) of bonding two wafers (1 and 2; ¶0076-0080) and forming a silicon oxide layer (6; ¶0111) and a silicon nitride layer (3; ¶0111) in order to protect the wafer (¶0104), and then removing the silicon oxide and silicon nitride layers from a top surface of the wafer (2) in order to expose the surface and prepare for GaN epitaxy (layer 4; ¶0107-¶0112).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the steps of removing the protective silicon oxide and silicon nitride layers (of Moriceau) in the method of modified Konishi, thereby exposing the silicon seed layer (Konishi, 4a), in order to protect the wafer while allowing exposure of the seed layer for further GaN epitaxy.
Regarding Claim 23, Konishi teaches a method (Fig. 1A-1F), comprising:
forming a supporting layer (layer 2 of amorphous silicon material; ¶0042, ¶0030) on a first substrate (ceramic AlN substrate 1; ¶0042, ¶0023);
forming a silicon seed layer (single-crystal silicon semiconductor layer 4a formed to be separated by ion implantation and used for forming semiconductor devices; ¶0018, ¶0022, ¶0042) on a second substrate (single crystal semiconductor substrate 4b; ¶0042);
bonding the silicon seed layer (4a) to the supporting layer (2) (Fig. 1E);
removing the second substrate (4b) (Fig. 1F).
Konishi is silent about forming an oxide layer around the silicon seed layer (4a), the supporting layer (2), and the first substrate (1); forming a nitride layer around the oxide layer, and forming a gallium nitride-based electronic structure on the surface of the silicon seed layer.
In the same field of endeavor, Odnoblyudov teaches forming a layer of silicon oxide (Odnoblyudov; Fig. 12; first adhesion layer 1212; wherein the adhesion layers are silicon oxide; ¶0082-¶0083, 0088) surrounding a portion of the first substrate (AlN substrate 1210, which is equivalent to AlN substrate 1 of Konishi or AlN substrate 110 of Odnoblyudov Fig. 1; wherein the substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945));
forming a layer of polycrystalline silicon (Odnoblyudov; Fig. 12; 1214; ¶0085) surrounding the layer of silicon oxide (1212) (as shown in Odnoblyudov Fig. 12) and forming an additional portion of the oxide layer (1216; ¶0080) surrounding the polycrystalline silicon layer (1214);
and removing a portion of the layer of polycrystalline silicon such that a remaining portion of the layer of polycrystalline silicon is below the first substrate (1210) (as described in Odnoblyudov ¶0085, wherein a remaining portion of the polysilicon layer is below 1210), and
forming a layer of silicon nitride (Odnoblyudov; Fig. 12; silicon nitride layer 1218; ¶0090) surrounding the layer of silicon oxide (now 1212+1216) (as shown in Odnoblyudov Fig. 12).
Odnoblyudov also teaches (Fig. 1) forming a GaN-based HEMT (¶0004, ¶0031, ¶0121) on a single crystal silicon layer (120; ¶0042, ¶0048, ¶0055) of a manufactured AlN ceramic substrate (110; which is a ceramic material chosen to match a CTE of one or more subsequent GaN epitaxial layers shown in Fig. 1; wherein growing GaN utilizes a core material of ceramic AlN as described in view of ¶0081)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the oxide/polysilicon/nitride layers (of Odnoblyudov) formed around the AlN substrate/seed layer of Konishi in order to protect the substrate/seed layer and allow electrostatic chucking of the ceramic substrate for use in conventional silicon semiconductor processing tools (Odnoblyudov ¶0087), and to form the GaN-based HEMT of Odnoblyudov utilizing the substrate of Konishi in order to provide a functioning transistor with reduced defects due to the CTE matching of the substrate and epitaxial layers (Odnoblyudov; ¶0002-¶0006, ¶0026-¶0033).
Konishi modified by Odnoblyudov does not expressly disclose removing a portion of the oxide layer (Odnoblyudov; 1212) and a portion of the nitride layer (Odnoblyudov; 1218) to expose a surface of the silicon seed layer (Konishi; 4a) to then form the GaN-based HEMT.
In the same field of endeavor, Moriceau teaches a method (Fig. 2) of bonding two wafers (1 and 2; ¶0076-0080) and forming a silicon oxide layer (6; ¶0111) and a silicon nitride layer (3; ¶0111) in order to protect the wafer (¶0104), and then removing the silicon oxide and silicon nitride layers from a top surface of the wafer (2) in order to expose the surface to prepare for GaN epitaxy (layer 4; ¶0107-¶0112).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the steps of removing the protective silicon oxide and silicon nitride layers (of Moriceau) in the method of modified Konishi, thereby exposing the silicon seed layer (Konishi, 4a), in order to protect the wafer while allowing exposure of the seed layer for further GaN epitaxy for the HEMT of Odnoblyudov.
Although Konishi is silent about the surface activated bonding using the plasma (7) creates dangling bonds on the supporting layer (2), this is well known. Xu teaches performing a surface activation process by exposing a top most layer (108) of amorphous silicon (¶0025) to a plasma to create dangling bonds (¶0028) in order to bond two substrates at low temperatures (¶0004). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the surface activation of Konishi utilizing the plasma creates dangling bonds in the amorphous silicon layer (as described in view of Xu), and/or it would have been obvious to create dangling bonds by the plasma in order to enable wafer bonding at low temperatures (Xu; ¶0004).
Regarding Claim 24, modified Konishi teaches the method of claim 23, wherein the first substrate (Konishi; 1) comprises aluminum nitride (Konishi; ; ¶0042, ¶0023).
Regarding Claim 25, modified Konishi teaches the method of claim 23, wherein removing the portion of the oxide layer (Moriceau; 6) comprises performing a wet etch process using hydrofluoric acid (HF) (hydrofluoric acid; Moriceau ¶0114).
Regarding Claim 27, modified Konishi teaches the method of claim 23, wherein a polycrystalline silicon layer (Odnoblyudov; Fig. 12; 1214; ¶0085) is disposed between a bottom surface of the first substrate (Konishi; 1, equivalent to Odnoblyudov 1210) and a remaining portion of the oxide layer (Odnoblyudov; Fig. 12; 1212; wherein polysilicon 1214 is removed from a top surface of 1210, and 1214 is between 1210+1216; ¶0085).
Regarding Claim 28, Konishi teaches a method (Fig. 1A-1F), comprising:
forming a supporting layer (layer 2 of amorphous silicon material; ¶0042, ¶0030) on a substrate (ceramic AlN substrate 1; ¶0042, ¶0023);
performing a surface activated process which uses a plasma (7; ¶0042) to bond a silicon seed layer (single-crystal silicon semiconductor layer 4a formed to be separated by ion implantation and used for forming semiconductor devices; ¶0018, ¶0022, ¶0042) to the supporting layer (2) (as shown in Fig. 1E; ¶0042).
Konishi is silent about depositing a first oxide layer around the silicon seed layer (4a), the supporting layer (2), and the substrate (1); forming a polycrystalline silicon layer around the first oxide layer; removing a portion of the polycrystalline silicon layer; depositing a second oxide layer around the first oxide layer and a remaining portion of the polycrystalline silicon layer; and forming a nitride layer around the second oxide layer.
In the same field of endeavor, Odnoblyudov teaches (Fig. 12) depositing a first oxide layer (1212; ¶0082) around an equivalent AlN substrate (1210; ¶0081); forming a polycrystalline silicon layer (1214; ¶0085) around the first oxide layer (1212); removing a portion of the polycrystalline silicon layer (a portion of 1214 is removed from one side of the substrate structure; ¶0085); depositing a second oxide layer (1216; ¶0088) around the first oxide layer (1212) and a remaining portion of the polycrystalline silicon layer (remaining lower portion of 1214); forming a nitride layer (1218; ¶0089) around the second oxide layer (1216) (as shown in Fig. 12).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the features/steps of Odnoblyudov in the device/method of Konishi in order to provide a polysilicon layer below the ceramic substrate to allow electrostatic chucking of the ceramic substrate for use in conventional silicon semiconductor processing tools (Odnoblyudov ¶0087), while providing protection for the structure during further fabrication steps.
Konishi modified by Odnoblyudov does not expressly disclose removing portions of the first oxide layer and the second oxide layer, and removing a portion of the nitride layer to expose a surface of the silicon seed layer (Konishi; 4a).
In the same field of endeavor, Moriceau teaches a method (Fig. 2) of bonding two wafers (1 and 2; ¶0076-0080) and forming a silicon oxide layer (6; ¶0111) and a silicon nitride layer (3; ¶0111) in order to protect the wafer (¶0104), and then removing the silicon oxide and silicon nitride layers from a top surface of the wafer (2) in order to expose the surface and prepare for GaN epitaxy (layer 4; ¶0107-¶0112).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the steps of removing the protective silicon oxide and silicon nitride layers (of Moriceau) in the method of modified Konishi, thereby exposing the silicon seed layer (Konishi, 4a), in order to protect the wafer while allowing exposure of the seed layer for further GaN epitaxy/device formation.
Modified Konishi is silent regarding forming a transistor structure on the surface of the silicon seed layer (Konishi; 4a). In the same field of endeavor; Odnoblyudov teaches (Fig. 1) forming a HEMT transistor structure (¶0031) on the surface of a silicon layer (Fig. 1; 120; ¶0027) on a ceramic substrate (110; ¶0027).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the GaN-based HEMT of Odnoblyudov utilizing the substrate of Konishi in order to provide a functioning transistor with reduced defects due to the CTE matching of the substrate and epitaxial layers (Odnoblyudov; ¶0002-¶0006, ¶0026-¶0033)
Although Konishi is silent about the surface activated bonding using the plasma (7) creates dangling bonds on the supporting layer (2), this is well known. Xu teaches performing a surface activation process by exposing a top most layer (108) of amorphous silicon (¶0025) to a plasma to create dangling bonds (¶0028) in order to bond two substrates at low temperatures (¶0004). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the surface activation of Konishi utilizing the plasma creates dangling bonds in the amorphous silicon layer (as described in view of Xu), and/or it would have been obvious to create dangling bonds by the plasma in order to enable wafer bonding at low temperatures (Xu; ¶0004).
Regarding Claim 30, modified Konishi teaches the method of claim 29, wherein the surface activated process is performed in a heated environment (as described in Konishi; ¶0041).
Konishi is silent regarding wherein the surface activated process is performed in a vacuum environment. However, Xu discloses performing the activation and bonding under vacuum (¶0032). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the activation under vacuum environment to prevent introduction of impurities from the atmosphere.
Regarding Claim 31, modified Konishi teaches the method of claim 28, wherein forming the transistor structure on the surface of the silicon seed layer (Konishi; 4a: equivalent to Odnoblyudov Fig. 1; 120) comprises: forming an aluminum nitride seed layer (Odnoblyudov; Fig. 1; wherein 130 is epitaxially formed on 120 and comprises an AlN layer that acts as a seed layer for further epitaxial growth; ¶0028) on the surface of the silicon seed layer (Odnoblyudov 120); forming a buffer layer (Odnoblyudov; Fig. 1; buffer layer 130 further comprises AlGaN buffer; ¶0028) on the aluminum nitride seed layer; and forming a heterojunction structure (Odnoblyudov; Fig. 1; heterojunction including the AlGaN/GaN interface forming 2DEG channel 150 for the HEMT; ¶0031) on the buffer layer (AlGaN of 130).
Regarding Claim 32, modified Konishi teaches the method of claim 27, wherein the polycrystalline silicon layer (Odnoblyudov; 1214) is further disposed over a remaining portion of the nitride layer (Odnoblyudov; 1218) (as modified by Moriceau wherein the nitride layer is removed from the top, leaving the portion of the nitride layer below the substrate and therefore leaving the polycrystalline silicon layer over the nitride layer).
Regarding Claim 33, modified Konishi teaches the method of claim 32, wherein the remaining portion of the oxide layer (as modified by Moriceau, Odnoblyudov Fig. 12; portion of 1212+1216 not removed from the top) surrounds the polycrystalline silicon layer (1214).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Shigeru Konishi et al. (US 20170221786 A1; hereinafter Konishi) in view of Vladimir Odnoblyudov et al. (US 2018/0204941 A1; hereinafter Odnoblyudov), Wen-Qing Xu et al. (US 20240017524 A1; hereinafter Xu), and Ya-Yu Yang et al. (US 10290730 B1; hereinafter Yang).
Regarding Claim 17, modified Konishi teaches the method of claim 9, wherein forming the gallium nitride-based electronic structure comprises: performing gallium nitride epitaxial growth (Odnoblyudov; Fig. 1; 140; ¶0029-¶0031); and performing a high-electron-mobility transistor (HEMT) process (to form a HEMT; Odnoblyudov; ¶0031).
Konishi/Odnoblyudov are silent regarding forming a source, a drain, and a gate in the HEMT process.
In the same field of endeavor, Yang teaches a similar device/method, including forming a GaN based HEMT (Yang; Fig. 1; C1:L13-L62) on an engineered substrate comprising AlN (Yang; Fig. 1; substrate 20 with AlN core 5; C6:L54-L56), the HEMT comprising a source (Yang; Fig. 1; 74), a drain (Yang; Fig. 1; 72), and a gate (Yang; Fig. 1; gate 80; C10:L33-L35).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the source, drain, and gate of Yang in the device/method of modified Konishi in order to provide a functional device with source/drain/gate terminals for external connection.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Shigeru Konishi et al. (US 20170221786 A1; hereinafter Konishi) in view of Vladimir Odnoblyudov et al. (US 2018/0204941 A1; hereinafter Odnoblyudov), Wen-Qing Xu et al. (US 20240017524 A1; hereinafter Xu), and and Davide Patti (US 2020/0243518 A1; hereinafter Patti).
Regarding Claim 21, modified Konishi teaches the method of claim 9, but is silent about the silicon seed layer (Konishi; 4a) comprises p-silicon.
Although Konishi is silent about the doping type of the silicon seed layer, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try one of the 3 finite n-type, p-type, or undoped silicon seed layer types, with a reasonable chance of success for obtaining the desired doping type desired for the device without undue experimentation. MPEP 2143 I (E).
Nevertheless, in the same field of endeavor, Patti teaches a similar HEMT with p-type Si layer with (111) crystal orientation for forming a GaN based HEMT (Patti; ¶0025). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have those features of Patti in modified Konishi because of the art-recognized suitability of p-type 111 Si for the intended purpose of forming a GaN-based HEMT.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Shigeru Konishi et al. (US 20170221786 A1; hereinafter Konishi) in view of Vladimir Odnoblyudov et al. (US 2018/0204941 A1; hereinafter Odnoblyudov), Wen-Qing Xu et al. (US 20240017524 A1; hereinafter Xu), Hubert Moriceau et al. (US 2019/0206678 A1; hereinafter Moriceau), and Zilan Li (US 2023/0031161 A1; hereinafter Li).
Regarding Claim 26, modified Konishi teaches the method of claim 23, but does not expressly disclose wherein removing the portion of the nitride layer (Moriceau; 3) comprises performing a wet etch process using phosphoric acid (H3P04).
However, the selection of a known etchant to remove a known material is an obvious selection to one of ordinary skill in the art. In the same field of endeavor, Li teaches (¶0173) selectively removing silicon nitride by wet etching with phosphoric acid. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use phosphoric acid to selectively etch the SiN of modified Konishi while leaving the silicon oxide (as in Li), due to the etching selectivity of phosphoric acid between the two materials (Li; ¶0173).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898