DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on 05/14/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made in the reply filed on 05/14/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 10-14 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kneissl et al. (US20030116767A1).
Regarding claim 1, Fig.2 of Kneissl teaches a semiconductor structure, comprising:
a silicon carbide substrate 202 (para.0032) having a first thickness T1 (para.0032, wherein the sapphire substrate 202 typically has a thickness of 200 micron to 1000 micron);
a nucleation layer 204 (para.0033) located on the silicon carbide substrate 202 and having a second thickness T2 (para.0033, wherein the nucleation layer 204 has a thickness in the range between 10 nm and 30 nm),
wherein the nucleation layer 204 is composed of aluminum gallium nitride (AlGaN), and the second thickness T2 is in a thickness range of T1*0.001% to T1*0.01% ((the upper thickness range of 202) *0.001% gives 10nm while (the lower thickness range of 202) *0.01% gives 20nm); and
a gallium nitride layer 206 (para.0034, wherein layer 206 is an n-type GaN) located on the nucleation layer 204 and spaced apart from the silicon carbide substrate 202.
Regarding claim 2, Kneissl further teaches the semiconductor structure according to claim 1, wherein the second thickness T2 is in a thickness range of T1*0.002% to T1*0.007% (wherein the (upper thickness 1000micron which is equivalent to 1,000,000nm) *0.002% gives 20nm which within the thickness range of the nucleation layer 204).
Regarding claim 3, Kneissl further teaches the semiconductor structure according to claim 2, wherein the second thickness T2 is in a thickness range of T1*0.003% to T1*0.005% (wherein the (upper thickness 1000micron which is equivalent to 1000,000nm) *0.003% gives 30nm which within the thickness range of the nucleation layer 204).
Regarding claim 10, Kneissl further teaches the semiconductor structure according to claim 1, wherein the gallium nitride layer 206 (para.0034, wherein layer 206 is an n-type GaN) has a third thickness T3, and the third thickness T3 is in a thickness range of T1*0.02% to T1*1% (para.0034, wherein layer 206 typically has a thickness of from about 1 .mu.m to about 20 .mu.m; which falls within a thickness range of T1*0.02% to T1*1%; wherein (upper thickness 1000 micron which is equivalent to 1000,000nm) *1% gives 2000nm ).
Regarding claim 11, Kneissl further teaches the semiconductor structure according to claim 10, wherein the gallium nitride layer has the third thickness T3, and the third thickness T3 is in a thickness range of T1*0.04% to T1*0.5% % (para.0034, wherein layer 206 typically has a thickness of from about 1 .mu.m to about 20 .mu.m; which falls within a thickness range of T1*0.04% to T1*0.5%; wherein (upper thickness 1000 micron which is equivalent to 1000,000nm) *0.5% gives 5000nm).
Regarding claim 12, Kneissl further teaches the semiconductor structure according to claim 11, wherein the gallium nitride layer has the third thickness T3, and the third thickness T3 is in a thickness range of T1*0.1% to T1*0.3% (para.0034, wherein layer 206 typically has a thickness of from about 1 .mu.m to about 20 .mu.m; which falls within a thickness range of T1*0.1% to T1*0.3%; wherein (upper thickness 1000 micron which is equivalent to 1000,000nm) *0.3% gives 3000nm ).
Regarding claim 13, Kneissl further teaches the semiconductor structure according to claim 1, wherein the first thickness T1 is 500μm (para.0032, wherein the sapphire substrate 202 typically has a thickness of 200 micron to 1000 micron).
Regarding claim 14, Kneissl further teaches the semiconductor structure according to claim 1, wherein the second thickness T2 is 20nm (para.0033, wherein the nucleation layer 204 has a thickness in the range between 10 nm and 30 nm).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kneissl et al. (US20030116767A1) in view of Sugawara et al. (US20140061660A1).
Regarding claim 4, Kneissl does not teach wherein the AlGaN is represented by the following formula (1):
AlxGa(100%-x) N formula (1)
wherein in formula (1), an aluminum content X is in a range of 20% to 60%.
Fig.1A of Sugawara teaches a semiconductor light emitting device that includes a supporting substrate, a light emitting layer including a nitride semiconductor, and a nitride multilayer film; wherein the material of the buffer AlN layer 11a and the AlN layer 11c is preferably Al.sub.xGa.sub.1-xN (wherein x = 0.5, and 0.5 is equal to 50% which is within range 20% to 60%) (para.0052).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Al.sub.xGa.sub.1-xN (wherein x = 0.5), as taught by Sugawara, in the teachings of Kneissl in order to prevent the diffusion of silicon (Si) in the silicon wafer 10 and to make the nitride multilayer film 11 to function as an antireflection film (Sugawara, [para.0052]).
Regarding claim 6, Kneissl does not teach wherein the AlGaN is represented by the following formula (1):
AlxGa(100%-x) N formula (1)
wherein in formula (1), an aluminum content X is in a range of 30% to 50%.
Fig.1A of Sugawara teaches a semiconductor light emitting device that includes a supporting substrate, a light emitting layer including a nitride semiconductor, and a nitride multilayer film; wherein the material of the buffer AlN layer 11a and the AlN layer 11c is preferably Al.sub.xGa.sub.1-xN (wherein x = 0.5, and wherein 0.5 is equal to 50%) (para.0052).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Al.sub.xGa.sub.1-xN (wherein x = 0.5), as taught by Sugawara, in the teachings of Kneissl in order to prevent the diffusion of silicon (Si) in the silicon wafer 10 and to make the nitride multilayer film 11 to function as an antireflection film (Sugawara, [para.0052]).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kneissl et al. (US20030116767A1) in view of Sugawara et al. (US20140061660A1) and in further view of Ayari et al. (US20220231188A1).
Regarding claim 5, the combination of Kneissl and Sugawara does not teach wherein the silicon carbide substrate is a 4-inch silicon carbide wafer substrate.
Figs. 2A and 2B of Ayari teach wherein growth substrate 102 can have a diameter of approximately two inches and approximately six inches and the growth substrate 102 can be silicon or silicon carbide (para.0075).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a silicon carbide substrate with the dimensions of Ayari in order to provide a sufficient size to enable subdividing the growth substrate into a plurality of delimited areas (Ayari, [para.0007]).
Regarding claim 7, the combination of Kneissl and Sugawara does not teach wherein the silicon carbide substrate is a 6-inch silicon carbide wafer substrate.
Fig.s 2A and 2B of Ayari teach wherein growth substrate 102 can have a diameter of approximately two inches and approximately six inches and the growth substrate 102 can be silicon or silicon carbide (para.0075).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a silicon carbide substrate with the dimensions of Ayari in order to provide a sufficient size to enable subdividing the growth substrate into a plurality of delimited areas (Ayari, [para.0007]).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kneissl et al. (US20030116767A1) in view of Park et al. (US11387355B2).
Regarding claim 8, Kneissl does not teach wherein the semiconductor structure has a bow in a range of -25μm to +25μm.
Fig.2 Park teaches wherein wafer bow is reduced or eliminated by controlling the epitaxial deposition time, and hence the thickness, of the third type III-V semiconductor lattice transition layer 124; and wherein for an epitaxial growth time of 268 seconds (which corresponds to a thickness of about 100 nm for the second type III-V lattice transition layer 122), an average wafer bow of −3 μm (concave) was observed for six samples. This trend extrapolates to a change in wafer bow of about 1.7 μm per second of epitaxial growth time for the third type III-V semiconductor lattice transition layer 124 with the specific device measured. Thus, the parameter of epitaxial growth time for the third type III-V semiconductor lattice transition layer 124 was isolated as an independent process parameter that can be used to shift the wafer bow of the type III-V semiconductor device 100 in a desired direction, and can be used to eliminate or mitigate wafer bow (col.8, lines 49-52 and col.9, lines 4-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the wafer bow reduction, as taught by Park, in the teachings of Kneissl because bigger wafer bows can cause cracks to propagate in the device and can harm the device performance and therefore reducing the wafer bow can reduce cracks and thus improve the device performance (Park, [col.2, lines 2-4]).
Regarding claim 9, Kneissl does not teach wherein the semiconductor structure has a bow in a range of -5μm to +5μm.
Fig.2 Park teaches wherein wafer bow is reduced or eliminated by controlling the epitaxial deposition time, and hence the thickness, of the third type III-V semiconductor lattice transition layer 124; and wherein for an epitaxial growth time of 268 seconds (which corresponds to a thickness of about 100 nm for the second type III-V lattice transition layer 122), an average wafer bow of −3 μm (concave) was observed for six samples. This trend extrapolates to a change in wafer bow of about 1.7 μm per second of epitaxial growth time for the third type III-V semiconductor lattice transition layer 124 with the specific device measured. Thus, the parameter of epitaxial growth time for the third type III-V semiconductor lattice transition layer 124 was isolated as an independent process parameter that can be used to shift the wafer bow of the type III-V semiconductor device 100 in a desired direction, and can be used to eliminate or mitigate wafer bow (col.8, lines 49-52 and col.9, lines 4-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the wafer bow reduction, as taught by Park, in the teachings of Kneissl because bigger wafer bows can cause cracks to propagate in the device and can harm the device performance and therefore reducing the wafer bow can reduce cracks and thus improve the device performance (Park, [col.2, lines 2-4]).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kneissl et al. (US20030116767A1) in view of Nakata et al. (US20120025205A1).
Regarding claim 15, Kneissl teaches the semiconductor structure according to claim 1, wherein the nucleation layer 204 (para.0033) includes an AlGaN layer, the AlGaN layer includes a first side and a second side opposite to the first side, the first side is in contact with the silicon carbide substrate 202 (para.0032), and the second side is in contact with the gallium nitride layer 206 (para.0034).
Kneissl does not teach wherein an aluminum content in the AlGaN layer decreases from the first side to the second side.
Fig.5 of Nakata teaches a semiconductor device includes an AlGaN layer that is provided on a SiC substrate and a GaN layer that is provided on the AlGaN layer; and wherein the AlGaN buffer layer 18 configured so that the Al composition ratio decreases from the SiC substrate 10 towards the GaN channel layer 14 and that the Al composition ratio of the AlGaN buffer layer 18 is 10% on the side close to the SiC substrate 10 and is 5% on the other side close to the GaN channel layer 14 (para.0140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Nakata’s AlGaN buffer layer 18, which is configured so that the Al composition ratio decreases from the SiC substrate 10 towards the GaN channel layer 14, in the teachings of Kneissl in order to raise Ec (conduction band edge) and improve the pinch-off characteristic (Nakata, [para.0141]).
Regarding claim 16, Nakata further teaches the semiconductor structure according to claim 15, wherein the aluminum content in the AlGaN layer decreases in a linear manner (para.0124, wherein Al composition ratio: gradually decreasing from 10% to 5% from the seed layer 12 to the GaN channel layer 14 (that is, the Al composition ratio closest to the seed layer 12 is 10% and that closest to the GaN channel layer 14 is 5%)).
Regarding claim 17, Nakata further teaches the semiconductor structure according to claim 15, wherein the aluminum content in the AlGaN layer decreases in a non-linear manner (para.0142, wherein the continuous change of the Al composition ratio of the AlGaN buffer layer 18 may have a stepwise change).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891
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