DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/15/2025 has been entered.
Response to Amendment
Applicant’s amendment filed on 10/15/2025 is acknowledged. Claims 1, 8, 12 and 15 have been amended.
Response to Arguments
Applicant’s arguments with respect to claims 1-11, 15-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “wherein the second connector is a single continuous conductive material” in the 3rd line from the bottom up. It is unclear whether this single continuous conductive material is the same or different than the “single continuous conductive material” in the definition of the post-passivation interconnect in lines 14-15 of the claim. For the purpose of examination, they are interpreted to be different conductive materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2013/0147034 A1) in view of Su et al. (US 7622309 B2) and Paek et al. (US 8362612 B1).
Regarding claim 1, Chen teaches a structure (650 in Fig. 6A-6C of Chen), comprising:
an integrated circuit die (650 in Fig. 6A);
an interconnect structure (38-44 in Figs. 6A-6C), wherein the integrated circuit die is attached to a first side (top side) of the interconnect structure, the interconnect structure comprising:
a conductive layer (22/22’) having a first contact pad (22’) and a second contact pad (22);
a first dielectric layer (30-32 in Fig. 6C) disposed on the conductive layer; and
a post-passivation interconnect (PPI) (38 in Figs. 2A & 6B), wherein the PPI is a single continuous conductive material (as shown in Fig. 2A) directly on the first dielectric layer, the PPI being in a non-corner region (as shown in Fig. 6B) of the integrated circuit die in the plan view, the corner region being under a higher stress than the non-corner region of the interconnect structure (as described in [0033] of Chen), the PPI comprising a PPI pad (portion of 38 in contact with bump 44 in Fig. 2A) and a conductive segment (portion of 38 not in contact with bump 44), the conductive segment extending through the first dielectric layer to contact the second contact pad (as shown in Fig. 2A), a second recess (the portion of 38 that is in the via hole) being disposed in the conductive segment in a plan view, the second recess overlapping the second contact pad in a cross-sectional view (as shown in Fig. 2A), the PPI pad having a flat top surface (as shown in Fig. 2A);
a first solder bump (44’ in Fig. 6C); and
a second solder bump (44 in Fig. 2A & 6B) physically contacting the flat top surface of the PPI pad, the second solder bump being laterally offset from the second recess (as shown in Fig. 2A).
But Chen does not teach that the interconnect structure comprising: a ground-up underbump metallization (UBM) pad extending through the first dielectric layer to contact the first contact pad, the ground-up UBM pad contacting an upper surface of the first dielectric layer, the ground-up UBM pad being in a corner region of the integrated circuit die in a plan view, a top surface of the ground-up UBM pad having a first recess; and the conductive segment being connected to the PPI pad by a transition element that changes in width from a width of the conductive segment to a width of the conductive pad in a plan view, the first solder bump is on the ground-up UBM pad, the first solder bump contacting sidewalls of the first recess of the ground-up UBM pad; and wherein an entire bottom surface of the second solder bump is coplanar with the flat top surface of the PPI pad in a cross-sectional view.
Su teaches a robust bump structure for corner bump (Figs. 3 and 5 of Su). The bump structure comprises: a contact pad (103 in Fig. 3); a first dielectric layer (301) on the contact pad; a first ground-up underbump metallization (UBM) pad (105) on the first dielectric layer, the first ground-up UBM pad being in a first region of the interconnect structure proximate a first corner region of the first integrated circuit die in a plan view (as shown in Fig. 5, this bump structure is designed for corner bump), a first portion (portion of 105 within the hole in dielectric layer 301) of the first ground-up UBM pad extending through the first dielectric layer to contact the first contact pad, the first portion of the first ground-up UBM pad having a recessed surface (recessed top surface of 105); and a connector (25) on the first ground-up UBM pad of the interconnect structure, the first connector contacting sidewalls and the recessed surface of the first ground-up UBM pad, and wherein the connector is a single continuous conductive material (as described in column 8 lines 54-56 of Su, the layer 200 is optional so the bump 25 is made of a single continuous solder ball material 504).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have added the UBM pad 105 of Su into the bump structure 100’ in Fig. 6C of Chen in order to strengthen the bump structure.
As incorporated, the dielectric layer 104, 301, 302 of Su are analogous to the first dielectric layer 30, 32 of Chen, respectively. So the UBM pad 105 of Su would be disposed on top of the layer 32 but under layer 40 in Fig. 6C of Chen.
But Chen in view of Su does not teach that the conductive segment being connected to the PPI pad by a transition element that changes in width from a width of the conductive segment to a width of the conductive pad in a plan view; and wherein an entire bottom surface of the second solder bump is coplanar with the flat top surface of the PPI pad in a cross-sectional view.
Paek teaches an interconnect structure (Figs. 4 & 5 of Paek). The structure comprises: a single continuous conductive material (430-440) directly on a passivation layer (114), a pad (430 in Fig. 5) and a conductive segment (430a), the conductive segment extending through the first dielectric layer to contact a second contact pad (113), a second recess (the portion of 430a in the via hole) being disposed in the conductive segment in a plan view, the second recess overlapping the second contact pad in a cross-sectional view (as shown in Fig. 4), the pad of the interconnect structure has a flat top surface (as shown in Fig. 4), and the conductive segment being connected to the pad by a transition element (portion connecting 430a to 430b) that changes in width from a width (W in Fig. 5 of Paek) of the conductive segment to a width (D in Fig. 5 of Paek) of the conductive pad in a plan view.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the second solder bump of Chen as disclosed by Paek in order to have reduced the manufacturing cost (see Abstract of Paek).
As incorporated, layer 460 of Paek is analogous to layer 40 of Chen, and solder bump (450) of Paek is analogous to 44 of Chen. So the entire bottom surface of the second solder bump would be coplanar with the flat top surface of the PPI pad (38 of Chen) in a cross-sectional view.
Regarding claim 2, Chen-Su-Paek teaches all limitations of the structure of claim 1, and further comprising: a second dielectric layer (40 of Chen or 302 of Su) on the first dielectric layer, the second dielectric layer extending along sidewalls of the UBM pad (see Fig. 3 of Su).
Regarding claim 3, Chen-Su-Paek teaches all limitations of the structure of claim 2, and also teaches wherein the second dielectric layer extends along sidewalls of the PPI (as shown in Fig. 6B of Chen).
Regarding claim 4, Chen-Su-Paek teaches all limitations of the structure of claim 2, and also teaches wherein the second dielectric layer contacts a sidewall of the first solder bump (as shown in Fig. 6B of Chen, the layer 40 contacts the sidewall of the lower/thinner part of the bump 44).
Regarding claim 5, Chen-Su-Paek teaches all limitations of the structure of claim 1, and also teaches wherein the interconnect structure is between the first solder bump and the integrated circuit die (as shown in Figs. 6A-6C of Chen).
Regarding claim 6, Chen-Su-Paek teaches all limitations of the structure of claim 1, and also teaches wherein the ground-up UBM pad comprises a first distance (R3 in Fig. 7 of Chen) to a neutral point (DNP) (C in Fig. 7 of Chen), wherein the PPI pad comprises a second DNP (R1 or R2 in Fig. 7), and wherein the first DNP is greater than the second DNP (as shown in Fig. 7 of Chen).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Su and Paek, and further in view of Lin et al. (US 2013/0062761 A1).
Regarding claim 7, Chen-Su-Paek teaches all limitations of the structure of claim 1, but does not teach the structure further comprising: an encapsulant on the interconnect structure and along sidewalls of the integrated circuit die; and a through via on the interconnect structure, wherein the through via is electrically coupled to the ground-up UBM pad.
Lin teaches a structure (Fig. 15 of Lin) that comprises: a molding material (124a in Fig. 15) on the interconnect structure (112 and 120); and a plurality of through-vias (134) on the interconnect structure, the molding material extending along sidewalls of the through vias (as shown in Fig. 15 of Lin).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the molding material and through-vias as disclosed by Lin in order to add more dies onto the package.
Claims 8, 10-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Su, Chen (US 2015/0021759 A1) (hereinafter referred to as Chen2025) and Liang et al. (US 8581400 B2).
Regarding claim 8, Chen teaches a structure (650 in Fig. 6A-6C of Chen with details of the bump structures shown in Figs. 2A-2B and 3), comprising:
a first integrated circuit die (650 in Fig. 6A);
an interconnect structure (the bump structures shown in Fig. 2A-2B, 3 and 6B-6C) coupled to the first integrated circuit die, the interconnect structure comprising:
a first contact pad (22’ in Fig. 3 and 6C) and a second contact pad (22 in Fig. 2A and 6B);
a first dielectric layer (30-32) on the first contact pad and the second contact pad; and
a post-passivation interconnect (PPI) (38 in Fig. 6B), wherein the PPI is a single continuous conductive material (as shown in Fig. 2A and 6B) on the first dielectric layer, the PPI being in a region (non-corner region in Fig. 6A) of the interconnect structure distal the first corner region of the first integrated circuit die in the plan view, the PPI comprising a PPI pad (portion of 38 in contact with bump 44) and a conductive segment (the rest of 38), a first portion (portion of conductive segment 38 in the hole in layer 30-32) of the conductive segment extending through the first dielectric layer to contact the second contact pad, the PPI pad having a flat top surface (see Fig. 2A & 6B);
a first connector (44’ in Fig. 6C); and
a second connector (44 in Fig. 6B) physically contacting the flat top surface of the PPI pad (as shown in Fig. 2A), wherein the second connector is laterally spaced apart from the first portion of the conductive segment (as shown in Fig. 2A).
But Chen does not each that the interconnect structure comprising: a first ground-up underbump metallization (UBM) pad on the first dielectric layer, the first ground-up UBM pad being in a first region of the interconnect structure proximate a first corner region of the first integrated circuit die in a plan view, a first portion of the first ground-up UBM pad extending through the first dielectric layer to contact the first contact pad, the first portion of the first ground-up UBM pad having a recessed surface, a lateral edge of the first contact pad extends beyond a lateral edge of the first ground-up UBM pad in a cross- sectional view; and that the first connector is on the first ground-up UBM pad of the interconnect structure, the first connector contacting sidewalls and the recessed surface of the first ground-up UBM pad; and wherein the second connector is a single continuous conductive material; and the second connector overlaps the second contact pad in a cross-sectional view.
Su teaches a robust bump structure for corner bump (Figs. 3 and 5 of Su). The bump structure comprises: a contact pad (103 in Fig. 3); a first dielectric layer (301) on the contact pad; a first ground-up underbump metallization (UBM) pad (105) on the first dielectric layer, the first ground-up UBM pad being in a first region of the interconnect structure proximate a first corner region of the first integrated circuit die in a plan view (as shown in Fig. 5, this bump structure is designed for corner bump), a first portion (portion of 105 within the hole in dielectric layer 301) of the first ground-up UBM pad extending through the first dielectric layer to contact the first contact pad, the first portion of the first ground-up UBM pad having a recessed surface (recessed top surface of 105); and a connector (25) on the first ground-up UBM pad of the interconnect structure, the first connector contacting sidewalls and the recessed surface of the first ground-up UBM pad, and wherein the connector is a single continuous conductive material (as described in column 8 lines 54-56 of Su, the layer 200 is optional so the bump 25 is made of a single continuous solder ball material 504).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have added the UBM pad 105 of Su into the bump structure 100’ in Fig. 6C of Chen in order to strengthen the bump structure, and to have made the bump from single continuous conductive material in order to simplify and to reduce cost of the manufacturing method.
As incorporated, the dielectric layer 104-301 of Su are analogous to the first dielectric layer 30-32 of Chen. So the UBM pad 105 of Su would be disposed on top of the layer 32 but under layer 40 in Fig. 6C of Chen. Layer 302 of Su is analogous to 40 of Chen.
But Chen in view of Su does not each that a lateral edge of the first contact pad extends beyond a lateral edge of the first ground-up UBM pad in a cross-sectional view; and the second connector overlaps the second contact pad in a cross-sectional view.
Chen2015 teaches an interconnect structure (see Fig. 3A-3D of Chen2015) comprising a ground-up UBM structure (bump structure on the right in Fig. 3D) in the corner region of the interconnect structure. The contact pad (104b in Fig. 3D) is larger than the width of its UBM pad (108b).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first contact pad larger than the ground-up UBM pad, as disclosed by Chen2015, in order to withstand more stress/strain.
But Chen-Su-Chen2015 does not each that the second connector overlaps the second contact pad in a cross-sectional view.
Liang teaches a post-passivation interconnect (PPI) structure (Fig. 11 of Liang) that comprises: a contact pad (22); a PPI structure (28I) connecting to the contact pad; a solder bump (34-36) disposed on the flat top surface of the PPI structure, wherein the second connector overlaps the second contact pad in a cross-sectional view (see Fig. 11 of Liang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the length of the PPI short enough so that the second connector overlaps with the second contact pad in order to simplify the arrangement. As the layout of the solder array of Chen is a fan-out, the bumps at the center region of the array do not need to be displaced too much laterally from the contact pad. Such situation gives rise to the need for short PPI pad, as shown in Liang.
Regarding claim 10, Chen-Su-Chen2015-Liang teaches all limitations of the structure of claim 8, and also teaches wherein the interconnect structure further comprises:
a third contact pad (lower right corner of the die 650 in Fig. 6A of Chen also has the structure in Fig. 6C, so there is a pad 22’ there too); and
a second ground-up UBM pad (42’ of the bump structure 100’ at the lower right corner) on the first dielectric layer, the second ground-up UBM pad being in a corner region (as defined) of the interconnect structure in the plan view, a first portion (portion of 42’ inside the via hole) of the second ground-up UBM pad extending through the first dielectric layer to contact the third contact pad, the first portion of the second ground-up UBM pad having a recessed surface (as shown in Fig. 6C of Chen).
Regarding claim 11, Chen-Su-Chen2015-Liang teaches all limitations of the structure of claim 10, and also teaches wherein the second connector is not in a corner region (as taught in claim 8 above) of the first integrated circuit die or in a corner region of the interconnect structure in the plan view.
Regarding claim 14, Chen-Su-Chen2015-Liang teaches all limitations of the structure of claim 10, and further comprising: a second dielectric layer (40 in Figs. 6B-C of Chen) contacting a surface and a sidewall of each of the first ground-up UBM pad and the PPI (as shown in Fig. 6B of Chen and Fig. 3 of Su).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Su, Chen2015, and Liang, and further in view of Lin.
Regarding claim 9, Chen-Su-Liang teaches all limitations of the structure of claim 8, but does not teach the structure further comprising: a molding material on the interconnect structure; and a plurality of through-vias on the interconnect structure, the molding material extending along sidewalls of the plurality of through vias.
Lin teaches a structure (Fig. 15 of Lin) that comprises: a molding material (124a in Fig. 15) on the interconnect structure (112 and 120); and a plurality of through-vias (134) on the interconnect structure, the molding material extending along sidewalls of the through vias (as shown in Fig. 15 of Lin).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the molding material and through-vias as disclosed by Lin in order to add more dies onto the package.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Su, Lu, Hanaoka (US 7462937 B2) and Lin.
Regarding claim 15, Chen teaches a structure (650 in Fig. 6A-6C of Chen with details of the bump structures shown in Figs. 2A-2B and 3) comprising:
a die (650 in Fig. 6A) on a first side (top side) of an interconnect (the bump structures shown in Fig. 2A-2B, 3 and 6B-6C);
a second plurality of connectors (38 in Figs. 2A and 6B) on a second side (bottom side of the bumps) of the interconnect, the second plurality of connectors being first post-passivation interconnect (PPI) pads (see Fig. 2A, 3 and 6B), the second plurality of connectors located in second regions (non-corner regions) of the second side of the interconnect, the second regions being proximate center regions of the dies in the plan view (see Fig. 7 of Chen);
first solder bumps (44’ in Fig. 6C); and
second solder bumps (44 in Fig. 6B) having bottom surfaces that physically contact flat top surfaces of the first PPI pads, the second solder bumps being single continuous conductive materials (as shown in Fig. 2A), the first solder bumps being located closer to the dies than the second solder bumps (as shown in Figs. 6B-6C of Chen).
But Chen does not teach that there are a plurality of dies on the first side of the interconnect, and the structure comprising: a molding compound around the dies; a first plurality of connectors on a second side of the interconnect, the first plurality of connectors being ground-up underbump metallization (UBM) pads, the first plurality of connectors located in first regions of the second side of the interconnect, the first regions being proximate corner regions of the dies in a plan view; and that the first solder bumps are on the first plurality of connectors, the first solder bumps contacting sidewalls of respective ground-up UBM pads; wherein an entire bottom surface of each of the second solder bumps contacts a respective top surface of the first PPI pads in a cross-sectional view, the first PPI pads are connected to conductive segments by respective transition elements in a plan view, wherein the conductive segments are laterally offset from the second solder bumps, and wide sides of the transition elements contacting the PPI pads respectively and narrow sides of the transition elements contacting the conductive segments respectively in the plan view.
Su teaches a robust bump structure for corner bump (Figs. 3 and 5 of Su). The bump structure comprises: a contact pad (103 in Fig. 3); a first dielectric layer (301) on the contact pad; a first ground-up underbump metallization (UBM) pad (105) on the first dielectric layer, the first ground-up UBM pad being in a first region of the interconnect structure proximate a first corner region of the first integrated circuit die in a plan view (as shown in Fig. 5, this bump structure is designed for corner bump), a first portion (portion of 105 within the hole in dielectric layer 301) of the first ground-up UBM pad extending through the first dielectric layer to contact the first contact pad, the first portion of the first ground-up UBM pad having a recessed surface (recessed top surface of 105); and a connector (25) on the first ground-up UBM pad of the interconnect structure, the first connector contacting sidewalls and the recessed surface of the first ground-up UBM pad, and wherein the connector is a single continuous conductive material (as described in column 8 lines 54-56 of Su, the layer 200 is optional so the bump 25 is made of a single continuous solder ball material 504).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have added the UBM pad 105 of Su into the bump structure 100’ in Fig. 6C of Chen in order to strengthen the bump structure, and to have made the bump from single continuous conductive material in order to simplify and to reduce cost of the manufacturing method.
As incorporated, the dielectric layer 104-301 of Su are analogous to the first dielectric layer 30-32 of Chen. So the UBM pad 105 of Su would be disposed on top of the layer 32 but under layer 40 in Fig. 6C of Chen. Layer 302 of Su is analogous to 40 of Chen.
But Chen in view of Su does not teach that there are a plurality of dies on the first side of the interconnect, and the structure comprising: a molding compound around the dies; wherein an entire bottom surface of each of the second solder bumps contacts a respective top surface of the first PPI pads in a cross-sectional view, the first PPI pads are connected to conductive segments by respective transition elements in a plan view, wherein the conductive segments are laterally offset from the second solder bumps, and wide sides of the transition elements contacting the PPI pads respectively and narrow sides of the transition elements contacting the conductive segments respectively in the plan view.
Lu teaches a PPI structure (100 in Fig. 2 of Lu) comprising: a solder bump (182 in Fig. 2 of Lu); a PPI pad (portion of 120-132 contacting the solder bump 182) and a conductive segment (remaining portion of 120-132); the conductive segment extending through a first dielectric layer (114) to contact the second contact pad (116), the conductive segment having a recess (the portion of 120-132 in the via hole) over the second contact pad, the PPI pad having a flat top surface (see Fig. 2 of Lu); and wherein an entire bottom surface of the second solder bump is coplanar with the flat top surface of the PPI pad in a cross-sectional view (see Fig. 2 of Lu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the second solder bump of Chen as disclosed by Lu in order to have stronger hold of the second solder bump.
As incorporated, molding compound 134 of Lu is analogous to layer 40 of Chen, and solder bump 182 of Lu is analogous to 44 of Chen. So the entire bottom surface of the second solder bump would be coplanar with the flat top surface of the PPI pad (38 of Chen) in a cross-sectional view.
But Chen-Su-Lu does not teach that there are a plurality of dies on the first side of the interconnect, and the structure comprising: a molding compound around the dies; wherein the first PPI pads are connected to conductive segments by respective transition elements in a plan view, wherein the conductive segments are laterally offset from the second solder bumps, and wide sides of the transition elements contacting the PPI pads respectively and narrow sides of the transition elements contacting the conductive segments respectively in the plan view.
Hanaoka teaches a structure on a surface of a substrate (Figs. 5A-C to 7 of Hanaoka). The structure comprises: a contact pad (14 in Fig. 1B) on top surface of a substrate (10); a passivation layer (16) on the top surface; a PPI structure (30 in Fig. 5A-5C of Hanaoka) disposed on the passivation layer and contacting the contact pad, wherein the PPI structure including a PPI pad (34 in Fig. 5A-5C) and a conductive segment (the uniform width portion of 32); a solder bump (50 in Fig. 7) on the PPI pad; wherein the PPI pad is connected to conductive segment by respective transition element (the tapering portion of interconnect 30 that is connecting the circular PPI pad 34 to the uniform width portion of 32 as shown in Fig. 5C) in a plan view, wherein the conductive segments are laterally offset from the second solder bumps (as shown in Fig. 5C), and wide sides of the transition elements contacting the PPI pads respectively and narrow sides of the transition elements contacting the conductive segments respectively in the plan view (as shown in Fig. 5C).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the shape of the PPI of Chen-Su-Lu as disclosed by Hanaoka in order to strengthen the PPI structure (smooth corners reduces stress on the interconnect).
But Chen-Su-Lu-Hanaoka does not teach that there are a plurality of dies on the first side of the interconnect, and the structure comprising: a molding compound around the dies.
Lin teaches a structure (Fig. 55 of Lin) that comprises: a plurality of dies (216a-216b) on the interconnect structure (212 and 218a); a molding material (224a in Fig. 55) on the dies and interconnect structure; and a plurality of through-vias (292 in Fig. 54) on the interconnect structure, the molding material extending along sidewalls of the through vias (as shown in Fig. 55 of Lin).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the plurality of dies and the molding material in order to increase functionality of the package and to have protected the dies.
Regarding claim 16, Chen-Su-Lu-Hanaoka-Lin teaches all limitations of the structure of claim 15, and further comprising: a third plurality of connectors (236 and 220c in Fig. 55 of Lin) on the second side of the interconnect, the third plurality of connectors being PPI pads (as incorporated, each die of 216a-216d have both PPI pads and UBM pads as shown in Fig. 6A of Chen. Thus, the PPI pads are identified as the third plurality of connectors), wherein the plurality of dies comprises a first die (116b of Su) and a second die (116c of Su), wherein a first one of the first plurality of connectors is in a first corner (upper right corner in Fig. 6A of Chen) of the first die in the plan view, wherein a first one of the third plurality of connectors is in a second corner (lower right corner of Fig. 6A) of the first die in the plan view.
Regarding claim 17, Chen-Su-Lu- Hanaoka-Lin teaches all limitations of the structure of claim 16, and also teaches wherein the second corner of the first die is adjacent the second die (as combined in claim 15).
Regarding claim 18, Chen-Su-Lu- Hanaoka-Lin teaches all limitations of the structure of claim 17, and also teaches wherein the first corner of the first die is a closest corner of the plurality of dies to a corner of the interconnect in the plan view (the choice of first die determines this property. For example, the first die can be identified as 216b in Fig. 55 of Lin and so its top right corner would be closest to the top right corner of the package).
Regarding claim 19, Chen-Su-Lu- Hanaoka-Lin teaches all limitations of the structure of claim 15, and also teaches wherein the first regions being under a higher stress than the second regions (as described in [0033] of Chen).
Regarding claim 20, Chen-Su-Lu- Hanaoka-Lin teaches all limitations of the structure of claim 15, and further comprising a dielectric layer (40 in Fig. 6B of Chen) partially covering the first plurality of connectors and partially covering the second plurality of connectors, wherein the dielectric layer only partially covers a sidewall (sidewall of the lower/thinner part of the bumps in Fig. 6B-6C of Chen) of the first solder bumps and the second solder bumps.
Allowable Subject Matter
Claims 12-13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12, the prior art of record does not disclose or fairly teaches all limitations of the structure of claim 10 and also including the limitation “wherein the second connector is in a second corner region of the first integrated circuit die in the plan view, wherein the second corner region is disposed at a location where a first sidewall of the first integrated circuit die adjoins a second sidewall of the first integrated circuit die in a plan view, and wherein the second connector is adjacent to the first sidewall and the second sidewall”.
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898