DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (FIGS. 1A–1V) in the reply filed on 10 Feb 2026 is acknowledged.
Applicant stated, “Claims 1-3, 9-12 and 16-20 are directed to the elected Species 1”, and the amended claims of 10 Feb 2026 have claims 4–8 and 13–15 marked as Withdrawn.
Additionally, since claim 16 depends on withdrawn/nonelected claim 13, the examiner also considers claim 16 to be withdrawn/nonelected.
Thus, claims 4–8 and 13–16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10 Feb 2026.
The claims to be examined in this office action are claims 1–3, 9–12, and 17–20.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10 Apr 2023 has been considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because in FIGS. 1G–1V and FIG. 3 (17 drawings) reference characters 114 and 116 have both been used to point to “the conductive layer 114” ¶[0031]. The specification states: “As shown in Fig. 1G, the seed layer 112 and the conductive layer 114 are partially removed, in accordance with some embodiments. As a result, the remaining portions of the seed layer 112 and the conductive layer 114 together form multiple conductive structures 116. The conductive structures 116 may function as through insulator vias (TIVs)” ¶[0032]. As such, the drawings should indicate in some way that the conductive layer 116 refers to the combination of the seed layer 112 and the conductive layer 114. This could be accomplished using a ’}’ as a grouping symbol, for example. Some ideas for possible edits are shown below:
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Also, in FIGS. 6E and 6F reference characters 140A and 602c have both been used to point to “the insulating layer 602c” ¶[0089]; and reference characters 140B and 602b have both been used to point to “the insulating layer 602b” ¶[0087]. The specification states: “first remaining portion of the insulating layer 602a, a first remaining portion of the second insulating layer 602b, and the remaining portion of the insulating layer 602c together form a dielectric structure 140A. A second remaining portion of the insulating layer 602a and a second remaining portion of the insulating layer 602b together form a dielectric structure 140B. A third remaining portion of the insulating layer 602a forms a dielectric structure 140C” ¶[0091]. As such, the drawings should indicate in some way that the dielectric structure 140A refers to the combination of first portions of the insulating layers 602a, 602b, and 602c; and that the dielectric structure 140B refers to the combination of second portions of the insulating layers 602a and 602b. This could be accomplished using a ’{’ as a grouping symbol, for example. Some ideas for possible edits are shown below.
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 19, the examiner finds the adjective “grounding” in “grounding bump” to be indefinite because it conflicts with the specification and the drawings. The specification does not include the term “grounding bump” but it does include the term “grounding layer”, as discussed below.
Claim 19 describes a “grounding bump”, which based on its description in the claim, the examiner understands to be referring to the conductive bump 152B in FIG. 1V or FIG. 3. For explanation, the examiner recites claim 19 and adds references to FIG. 1V based on the examiner’s understanding and interpretation of the claim:
“19. (Original) The package structure [FIG. 1V] as claimed in claim 18, further comprising:
a grounding bump [152B] formed on the redistribution structure [144a-c, 142A-C, 146, 148], wherein the grounding bump [152B] is electrically connected to the second conductive feature [142A] of the capacitor element [106, 140A, 142A] and the fourth conductive feature [142B] of the second capacitor element [106, 140B, 142B].”
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The term “grounding bump” is not used in the specification. The specification states: “The conductive bump 152C is electrically connected to the conductive structure 116 that is further electrically connected to the conductive feature 104 that functions as a grounding layer” ¶[0062]. Thus, the examiner understands from ¶[0062] and from inspecting FIG. 1V that the bottom electrodes 106 (see ¶[0053]) of the three capacitors having dielectric structures 140A, 140B, and 140C, respectively, are to be connected to ground through the conductive feature 104, the conductive pillar 116, the redistribution structure (146, 148), a UBM structure 150, and the conductive bump 152C. The examiner understands the claimed “grounding bump” to refer to conductive bump 152B because that is the bump that is shown in FIG. 1V as being electrically connected to the top electrode 142A of the capacitor that has the dielectric structure 140A, as required by the claim. Thus, the claim implies by using the name “grounding bump” that the top electrodes 142A and 142B of two of the capacitors having dielectric structures 140A and 140B, respectively, are to be connected to ground, which contradicts ¶[0062] of the specification, where it is implied that the bottom electrodes 106 of the capacitors are to be connected to ground.
In summary, based on FIG. 1V and ¶[0062], the examiner believes that the conductive bump 152C could be properly referred to as “a grounding bump”, but the conductive bump 152B, which is claimed as “a grounding bump” (based on the examiner’s interpretation of the claim in view of FIG. 1V), should be given a different name in claim 19 other than “a grounding bump”. A possible replacement term in claim 19 would be a “charging bump” or “charging/discharging bump” since it stands to reason that if the bottom electrodes 106 function as “grounding electrodes” of the capacitors (connected to the grounding layer 104 and the “grounding bump” 152C), then the top electrodes 142A–C function as “charging electrodes” for charging the capacitors by connecting a voltage different from ground to the bump 152B, and also function as “discharging electrodes” for discharging the capacitors by connecting the bump 152B to ground.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1–2, 9, and 11–12 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2016/0133686 A1 by Liao and Jou (“Liao-2016” hereinafter).
Regarding claim 1, Liao-2016 teaches:
A method (FIG. 21–26) for forming a package structure 200 (FIG. 20, “integrated Fan-Out (InFO) package 200” ¶[0059]), comprising:
surrounding (FIG. 22) a semiconductor chip 208 (“device die 208” ¶[0060]) with a protective layer 209 (“the molding compound MC is applied in the molding layer 209 to surround the device die 208” ¶[0027]), wherein the protective layer 209 has a first dielectric constant (“the molding compound MC includes material with relatively low dielectric constant, including, for example, an epoxy resin, a molding underfill, or the like” ¶[0064], “the molding compound MC has a low-k value, e.g., less than about 3.9, and even less than about 2.5 in other embodiments” ¶[0076]);
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partially removing (FIG. 23) the protective layer 209 to form an opening (i.e., the leftmost of the three openings in FIG. 23 between the four vertical conductive structures 124 and 144 [labeled in FIG. 20] where the protective layer 209 from FIG. 22 has been removed, “in operation S393 [FIG. 21], an etching process is performed to remove the exposed portions of the molding compound MC between the vertical conductive structures 124 and the vertical conductive structures 144, as illustrated in FIG. 23” ¶[0066]);
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forming (FIG. 25) a dielectric structure 160 (“dielectric material 160” ¶[0068]) at least partially filling the opening (“in operation S397 [FIG. 21], the dielectric material 160 is formed between the vertical conductive structures 124 and the vertical conductive structures 144 and overlying the molding layer 209, as illustrated in FIG. 25” ¶[0068]), wherein the dielectric structure 160 has a second dielectric constant (“the dielectric material 160 includes room-temperature (e.g., 25° C.) liquid-phase high-K polymer … of which the dielectric constant is greater than or equal to approximately 4” ¶[0061]), and the second dielectric constant (of 4 or greater) is higher than the first dielectric constant (of 3.9 or lower or even 2.5 or lower, see above) (“the dielectric constant (or permittivity) value of the dielectric material 160 is greater than that of the molding compound MC” ¶[0076]); and
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forming (see FIG. 20, and compare to steps shown in FIGS. 14–19) a redistribution structure 212+214 (“redistribution layers (RDLs) 212 and 214” ¶[0023]) over the semiconductor chip 208, the protective layer 209, and the dielectric structure 160.
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Regarding claim 2, Liao-2016 teaches:
The method for forming a package structure 200 (FIG. 20) as claimed in claim 1, further comprising:
partially removing (FIG. 23) the protective layer 209 to form a second opening (i.e., the rightmost of the three openings in FIG. 23 between the four vertical conductive structures 124 and 144 [labeled in FIG. 20] where the protective layer 209 from FIG. 22 has been removed);
forming (FIG. 25) an insulating layer 160 overfilling the opening (leftmost of the three openings) and the second opening (rightmost of the three openings) (“The dielectric material 160 is filled between the vertical conductive structures 124 and the vertical conductive structures 144 in the semiconductor structure 100 to form an insulating structure” ¶[0060]); and
planarizing (FIG. 26) the insulating layer 160 such that a first remaining portion of the insulating layer 160 in the opening (leftmost of the three openings) forms the dielectric structure 160 (leftmost of the three dielectric structures 160), and a second remaining portion of the insulating layer in the second opening (rightmost of the three openings) forms a second dielectric structure 160 (rightmost of the three dielectric structures 160).
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Regarding claim 9, Liao-2016 teaches:
The method for forming a package structure 200 (FIG. 20) as claimed in claim 1, further comprising:
forming (FIG. 5) a second redistribution structure 204 (“InFO backside redistribution layer (RDL) 204” ¶[0023]) over a carrier substrate 201 (“carrier 201” ¶[0033]), wherein the second redistribution structure 204 has a first conductive feature (“the backside RDL 204 includes conductive features, including, for example, conductive lines and/or vias, formed in one or more polymer layers” ¶[0034]);
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disposing (FIG. 11) the semiconductor chip 208 over the second redistribution structure 204;
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forming (FIG. 12) the protective layer 209 over the second redistribution structure 204 such that the protective layer surrounds the semiconductor chip 208; and
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forming (see FIGS. 14–19 and compare to FIG. 20) a second conductive feature 210 (FIG. 20, “conductive layer 210” ¶[0023]) on the dielectric structure 160 (leftmost of the three dielectric structures 160), wherein the dielectric structure 160 is between the second conductive feature 210 and the first conductive feature 204.
That is, since FIG. 20 shows that the left of the two second conductive features 210 extends horizontally beyond the right sidewall of the vertical conductive feature 144 to vertically overlap a portion of the leftmost of the three dielectric structures 160, and the left of the two first conductive features 204 extends horizontally beyond the left sidewall of the vertical conductive feature 124 to vertically overlap a portion of the leftmost of the three dielectric structures 160, it is a true statement that the leftmost of the three dielectric structures 160 is between a portion of the second conductive feature 210 and a portion of the first conductive feature 204. A nearly vertical line segment could be drawn from the overhanging portion of the second conductive feature 210 to the extended portion of the first conductive feature 204 with the line segment only passing through the leftmost of the three dielectric structures 160, identified as “the dielectric structure” of this claim.
Regarding claim 11, Liao-2016 teaches:
A package structure 200 (FIG. 20, “integrated Fan-Out (InFO) package 200” ¶[0059]), comprising:
a semiconductor chip 208 (“device die 208” ¶[0060]);
a dielectric structure 160 (“dielectric material 160” ¶[0068]) laterally spaced apart from the semiconductor chip 208, wherein the dielectric structure 160 has a first dielectric constant (“the dielectric material 160 includes room-temperature (e.g., 25° C.) liquid-phase high-K polymer … of which the dielectric constant is greater than or equal to approximately 4” ¶[0061]);
a protective layer 209 surrounding the semiconductor chip 208 and the dielectric structure 160 (“the molding compound MC is applied in the molding layer 209 to surround the device die 208” ¶[0027], and FIG. 20 shows the molding layer 209 surrounding the left and right sides of the vertical capacitor 100, thereby surrounding the left and right sides of the dielectric structure 160 of the vertical capacitor 100 without being in direct contact with the dielectric structure 160), wherein the protective layer 209 has a second dielectric constant (“the molding compound MC includes material with relatively low dielectric constant, including, for example, an epoxy resin, a molding underfill, or the like” ¶[0064], “the molding compound MC has a low-k value, e.g., less than about 3.9, and even less than about 2.5 in other embodiments” ¶[0076]), and the second dielectric constant (of 3.9 or lower or even 2.5 or lower) is lower than the first dielectric constant (of 4 or higher, see above) (“the dielectric constant (or permittivity) value of the dielectric material 160 is greater than that of the molding compound MC” ¶[0076]); and
a redistribution structure 212+214 (“redistribution layers (RDLs) 212 and 214” ¶[0023]) over the semiconductor chip 208, the dielectric structure 160, and the protective layer 209.
Regarding claim 12, Liao-2016 teaches:
The package structure 200 (FIG. 20) as claimed in claim 11, wherein the dielectric structure 160 is substantially as thick as the protective layer 209 (as shown in FIG. 20, the protective layer 209 and the dielectric structure 160 have the same thickness in the vertical direction).
Claims 17–20 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2020/0135840 A1 by Chen and Liao (“Chen” hereinafter).
Regarding claim 17, Chen teaches:
A package structure 100 (FIG. 22, “semiconductor arrangement 100” ¶[0012]), comprising:
a semiconductor chip 102 (“the active device 102 comprises a known good die (KGD) cut from a semiconductor wafer” ¶[0023]);
a capacitor element 202 (“first capacitor 202” ¶[0061]) laterally spaced apart from the semiconductor chip 102, wherein the capacitor element 202 has a first conductive feature 106, a dielectric structure 110, and a second conductive feature 104, and the dielectric structure 110 is between the first conductive feature 106 and the second conductive feature 104 (“The first capacitor 202 is defined by the vertical conductive structure 106, the vertical conductive structure 104, and the dielectric material 110 between 106 and 104” ¶[0062]);
a protective layer 118 (“molding layer 118” ¶[0027]) surrounding the semiconductor chip 102 and the dielectric structure 110 of the capacitor element 202 (i.e., the protective layer 118 surrounds the left and right sides of the semiconductor chip 102, and the protective layer 118 surrounds the left and right sides of the dielectric structure 110 of the capacitor element 202 without being in direct contact with the dielectric structure 110); and
a redistribution structure 954+958 (“the layer of conductive elements 954 are part of a redistribution layer” ¶[0049], “the deposited conductive material 958 defines a redistribution layer” ¶[0054]) over the semiconductor chip 102, the capacitor element 202, and the protective layer 118.
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Regarding claim 18, Chen teaches:
The package structure 100 as claimed in claim 17, further comprising:
a second capacitor element 206 (“third capacitor 206” ¶[0061]) laterally spaced apart from the capacitor element 202, wherein the second capacitor element 206 has a third conductive feature 107, a second dielectric structure 110, and a fourth conductive feature 111, and the second dielectric structure 110 is between the third conductive feature 107 and the fourth conductive feature 111 (“The third capacitor 206 is defined by the vertical conductive structures 107 and 109 and the dielectric material 110 between 107 and 109” ¶[0064]).
Regarding claim 19, Chen teaches:
The package structure 100 as claimed in claim 18, further comprising:
a grounding bump 974 (“conductive element 974” ¶[0067]) formed on the redistribution structure 954+958, wherein the grounding bump 974 is electrically connected to the second conductive feature 104 of the capacitor element 202 and the fourth conductive feature 109 of the second capacitor element 206 (“the voltage applied to at least one of the vertical conductive structures 104, 105, or 109 is ground or zero volts” ¶[0067]; “the voltage applied to the vertical conductive structure 109, such as through the conductive element 974, is also applied to at least one of the vertical conductive structures 104 or 105, such as through one or more electrical connections (not shown) through layers 962, 956, and 952, or such as through one or more electrical connections (not shown) in layer 116 that connect at least one of the vertical conductive structures 104, 105, or 109 to a different of the vertical conductive structures 104, 105, or 109” ¶[0067]).
Based on the underlined portions above, Chen teaches that the vertical conductive structures 104, 105, and 109 can be electrically connected to each other (through undrawn electrical connections), and thus the vertical conductive structures 104, 105, and 109 can be electrically connected through the bump 974 (since FIG. 22 shows that conductive structure 109 is electrically connected to the bump 974) to a common electric potential of zero volts, defined as ground. Thus the bump 974 may be called a grounding bump 974.
Regarding claim 20, Chen teaches:
The package structure 100 as claimed in claim 18, wherein the dielectric structure 110 (of the capacitor element 202) and the second dielectric structure 110 (of the second capacitor element 206) have the same dielectric constant (since they were formed from a single layer of dielectric material dielectric material 110 in FIG. 12 that was thinned/planarized in FIG. 13A to form the separate dielectric structures 110 of FIG. 22), and the dielectric structure 110 (of the capacitor element 202) is larger (in width, since the first distance 221 is wider than the second distance 224 in FIG. 22) than the second dielectric structure 110 (of the second capacitor element 206).
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Claims 17–20 are also rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2021/0028095 A1 by Kuo and Liao (“Kuo” hereinafter).
Regarding claim 17, Kuo teaches:
A package structure (FIG. 14, “an integrated fan-out (InFO) packaging structure”), comprising:
a semiconductor chip 800 (“die 800” ¶[0023]);
a capacitor element A laterally spaced apart from the semiconductor chip 800, wherein the capacitor element A has a first conductive feature 610 (i.e., the left of the three through interposer vias 610 [TIVs, see claim 1], each TIV 610 being a combination of a copper seed layer stack 500 and a copper layer 600, see ¶[0021]), a dielectric structure 1100 (i.e., the left of the three dielectric structures 1100), and a second conductive feature 1110 (i.e., the left of the three conductive features 1110), and the dielectric structure 1100 is between the first conductive feature 610 and the second conductive feature 1110 (see FIG. 11, “patterned dielectric layer 1100, patterned metal layer 1110, and TIVs 610 form MIM capacitors A, B, C” ¶[0031], “metal insulator metal (MIM) capacitors” ¶[0004]);
a protective layer 900+1210 (see FIG. 12, “molding compound (MC) 900” ¶[0024] and “polymer layer 1200” ¶[0036]) surrounding the semiconductor chip 800 and the dielectric structure 1100 (FIG. 11) of the capacitor element A (i.e., FIG. 12 shows that the molding compound 900 surrounds the lateral sides of the semiconductor chip 800, and the polymer layer 1200 surrounds the top side of the semiconductor chip 800 and the lateral sides of the dielectric structure 1100 of the capacitor element A); and
a redistribution structure 1300 (see FIG. 14, “second RDL 1300” ¶[0038]) over the semiconductor chip 800, the capacitor element A, and the protective layer 900+1210.
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Regarding claim 18, Kuo teaches:
The package structure (FIG. 14) as claimed in claim 17, further comprising:
a second capacitor element B laterally spaced apart from the capacitor element A, wherein the second capacitor element B has a third conductive feature 610 (i.e., the middle of the three TIVs 610), a second dielectric structure 1100 (i.e., the middle of the three dielectric structures 1100), and a fourth conductive feature 1110 (i.e., the middle of the three conductive features 1110), and the second dielectric structure 1100 is between the third conductive feature 610 and the fourth conductive feature 1110.
Regarding claim 19, Kuo teaches:
The package structure (FIG. 14) as claimed in claim 18, further comprising:
a grounding1 bump 1430 (“solder bump 1430” ¶[0040]) formed on the redistribution structure 1300, wherein the grounding bump 1430 is electrically connected to the second conductive feature 1110 of the capacitor element A and the fourth conductive feature 1110 of the second capacitor element B (“solder bump 1430—which is electrically connected to MIM capacitor A—can be electrically coupled to an external power supply through metal layer 1110 of MIM capacitor A”; “electrical connections to metal layer 1110 of MIM decoupling capacitors B and C can be formed at locations along the y-axis not visible in FIG. 15 (e.g., into the page)” ¶[0040]).
Regarding claim 20, Kuo teaches:
The package structure as claimed in claim 18, wherein the dielectric structure 1100 (of capacitor A) and the second dielectric structure 1100 (of the capacitor B) have the same dielectric constant (the separate patterns of the patterned dielectric layer 1100 of FIG. 11 corresponding to capacitors A and B, respectively, have the same dielectric constant because they were formed from patterning the single “high-k dielectric 1010” ¶[0026] of FIG. 10), and the dielectric structure 1100 (of capacitor A) is larger (in width, as shown in FIG. 11) than the second dielectric structure 1100 (of capacitor B).
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Claims 17 and 18 are also rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2020/0243453 A1 by Wang and Lin (“Wang” hereinafter).
Regarding claim 17, Wang teaches:
A package structure 100 (FIG. 1, “package structure 100” ¶[0016]), comprising:
a semiconductor chip 300 (“System on Chip unit 300” ¶[0016]);
a capacitor element 200 (“first capacitor 200” ¶[0016]) laterally spaced apart from the semiconductor chip 300, wherein the capacitor element 200 has a first conductive feature 210, a dielectric structure 230, and a second conductive feature 220 (“the first capacitor 200 includes a first conductive element 210, an dielectric element 230 and a second conductive element 220” ¶[0023]), and the dielectric structure 230 is between the first conductive feature 210 and the second conductive feature 220;
a protective layer 110 surrounding the semiconductor chip 300 and the dielectric structure 230 of the capacitor element 200 (“the first dielectric layer 110 is formed by a molding process through a first dielectric medium so as to bond the first capacitor 200 and the System on Chip unit 300” ¶[0018]); and
a redistribution structure 120+121 (“second dielectric layer 120” and “wiring layer 121” ¶[0018]) over the semiconductor chip 300, the capacitor element 200, and the protective layer 110.
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Regarding claim 18, Wang teaches:
The package structure 100 as claimed in claim 17, further comprising:
a second capacitor element C laterally spaced apart from the capacitor element 200 (as shown in FIG. 1, C is both laterally and vertically spaced apart from 200), wherein the second capacitor element C has a third conductive feature 121a, a second dielectric structure 120b, and a fourth conductive feature 121b (“the gap between one of the first metal units 121a and one of the second metal units 121b can form a second capacitor C. The second capacitor C is formed in the second dielectric layer 120” ¶[0036]), and the second dielectric structure 120b is between the third conductive feature 121a and the fourth conductive feature 121b (as shown in FIG. 5F).
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Claims 17 and 18 are also rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2022/0336336 A1 by Kim.
Regarding claim 17, Kim teaches:
A package structure (FIG. 1, “semiconductor package” ¶[0011]), comprising:
a semiconductor chip 300 (“semiconductor chip 300” ¶[0021]);
a capacitor element 430 (inside region “A” in FIG. 1, detail of region “A” shown in FIG. 2) laterally spaced apart from the semiconductor chip 300, wherein the capacitor element 430 has a first conductive feature 434, a dielectric structure 432, and a second conductive feature 434 (FIG. 2, “the first passive device 430 may be a multi-layer ceramic capacitor (MLCC) in which a pair of electrodes 434 are provided on opposite lateral surfaces of a ceramic main body 432. For example, the MLCC may include the electrodes 434 and the ceramic main body 432”), and the dielectric structure 432 is between the first conductive feature 434 (on the left side of 432) and the second conductive feature 434 (on the right side of 432);
a protective layer 500 (“molding layer 500” ¶[0056]) surrounding the semiconductor chip 300 and the dielectric structure 432 of the capacitor element 430; and
a redistribution structure 600 (“second redistribution substrate 600” ¶[0024]) over the semiconductor chip 300, the capacitor element 430, and the protective layer 500.
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Regarding claim 18, Kim teaches:
The package structure (FIG. 1) as claimed in claim 17, further comprising:
a second capacitor element 430 (i.e., the 430 on the right side of the semiconductor chip 300) laterally spaced apart from the capacitor element 430 (i.e., the 430 on the left side of the semiconductor chip 300 inside the region “A” in FIG. 1 that is shown in greater detail in FIG. 2), wherein the second capacitor element 430 (right side) has a third conductive feature 434, a second dielectric structure 432, and a fourth conductive feature 434, and the second dielectric structure 432 is between the third conductive feature 434 (on the left side of 432) and the fourth conductive feature (on the right side of 432).
Claims 17 and 18 are also rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2011/0233726 A1 by Huang et al. (“Huang” hereinafter).
Regarding claim 17, Huang teaches:
A package structure (FIG. 6, “semiconductor package” ¶[0068]), comprising:
a semiconductor chip 150 (“semiconductor die 150” ¶[0073]);
a capacitor element 142a+144+148 (“vertically oriented integrated MIM capacitor” ¶[0077]) laterally spaced apart from the semiconductor chip 150, wherein the capacitor element 142a+144+148 has a first conductive feature 142a (“conductive pillar 142a” ¶[0077]), a dielectric structure 144 (“dielectric layer 144” ¶[0077]), and a second conductive feature 148 (“conductive layer 148” ¶[0077]), and the dielectric structure 144 is between the first conductive feature 142a and the second conductive feature 148 (“conductive pillars 142a and 142d operates as a first metal electrode of first and second vertically oriented integrated MIM capacitors. Conductive layer 148 is the second metal electrode of the MIM capacitors. Dielectric layer 144 is the intermediate insulator between the first and second metal electrodes” ¶[0077]);
a protective layer 154 (“molding compound 154” ¶[0074]) surrounding the semiconductor chip 150 and the dielectric structure 144 of the capacitor element 142a+144+148 (i.e., the protective layer 154 surrounds the left and right sides of the dielectric structure 144 of the capacitor element 142a+144+148 without being in direct contact with the dielectric structure 144); and
a redistribution structure 165 (“interconnect structure 165” ¶[0086]) over the semiconductor chip 150, the capacitor element 142a+144+148, and the protective layer 154.
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Regarding claim 18, Huang teaches:
The package structure (FIG. 6) as claimed in claim 17, further comprising:
a second capacitor element 142d+144+148 (“vertically oriented integrated MIM capacitor” ¶[0077]) laterally spaced apart from the capacitor element 142a+144+148, wherein the second capacitor element 142d+144+148 has a third conductive feature 142d, a second dielectric structure 144, and a fourth conductive feature 148, and the second dielectric structure 144 is between the third conductive feature 142d and the fourth conductive feature 148 (“conductive pillars 142a and 142d operates as a first metal electrode of first and second vertically oriented integrated MIM capacitors. Conductive layer 148 is the second metal electrode of the MIM capacitors. Dielectric layer 144 is the intermediate insulator between the first and second metal electrodes” ¶[0077]).
Claim 17 is also rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2018/0337122 A1 by Liao and Jou (“Liao-2018” hereinafter).
Regarding claim 17, Liao-2018 teaches:
A package structure 200 (FIG. 1, “integrated Fan-Out (InFO) package 200” ¶[0009]), comprising:
a semiconductor chip 208 (“device die 208” ¶[0009]);
a capacitor element 220 (“metal-insulator-metal (MIM) capacitor 220” ¶[0009]) laterally spaced apart from the semiconductor chip 208, wherein the capacitor element 220 has a first conductive feature 207, a dielectric structure 218, and a second conductive feature 210 (“the MIM capacitor 220 includes the first electrode 207, the insulation layer 218 and the second electrode 210” ¶[0010]), and the dielectric structure 218 is between the first conductive feature 207 and the second conductive feature 210 (as shown in FIG. 1);
a protective layer 209 (“molding layer 209” ¶[0009]) surrounding the semiconductor chip 208 and the dielectric structure 218 of the capacitor element 220 (as shown in FIG. 1, the protective layer 209 surrounds the left and right sides of the semiconductor chip 208, and the protective layer 209 surrounds the left and right sides of the dielectric structure 218 without being in direct contact with the dielectric structure 218); and
a redistribution structure 212+214 (“front side redistribution layers (RDLs) 212 and 214” ¶[0009]) over the semiconductor chip 208, the capacitor element 220, and the protective layer 209.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liao-2016 (as applied to the rejection of claim 2 above) in view of Chen (cited above in the rejections of claims 17–20).
Regarding claim 3, Liao-2016 teaches the method for forming a package structure 200 (FIG. 20) as claimed in claim 2, as shown above.
However, Liao-2016 fails to teach that the opening (FIG. 23, leftmost of the three openings) is wider than the second opening (FIG. 23, rightmost of the three openings). That is, the three openings in FIG. 23 between the four vertical conductive structures 124 and 144 (labeled in FIG. 20) appear to have equal widths.
Chen shows in FIG. 22 (reproduced above in the rejection of claim 17) a package structure 100 sharing many features in common with Liao-2016’s package structure 200, including a semiconductor chip 102 surrounded by a protective layer 118, and capacitors 202, 204, 206, and 208 each comprising two adjacent vertical conductive structures with dielectric structures 110 located between the two adjacent vertical conductive structures. Additionally, Chen teaches a method of forming the package structure 100 in agreement with Liao-2016 (and in agreement with claims 1 and 2 of the present application), including:
partially removing (FIG. 11) the protective layer to form an opening 223 (having width 221) and a second opening 227 (having width 224 in FIG. 13A) (see ¶[0027]);
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forming (FIG. 12, reproduced in the rejection of claim 20 above) an insulating layer 110 overfilling the opening 223 and the second opening 227; and
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planarizing (FIG. 13A) the insulating layer 110 such that a first remaining portion of the insulating layer 110 in the opening 223 (FIG. 11) forms the dielectric structure 110 (having width 221 in FIG. 13A), and a second remaining portion of the insulating layer 110 in the second opening 227 (FIG. 11) forms a second dielectric structure (having width 224 in FIG. 13A).
FIG. 11 clearly shows that the width 221 of the opening 223 is wider than the width 224 of the second opening 227.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liao-2016’s vertical capacitor 100 of FIG. 20 to have varying horizontal spacings instead of uniform spacings between the adjacent vertical conductive structures 124 and 144, as demonstrated in Chen’s FIG. 11 by the varying horizontal widths 221, 222, 224, and 226 of the four openings. Chen’s purpose in using different horizontal widths for the openings was to have different widths for the dielectric structures 110 between the vertical conductors of the capacitors 202, 204, 206, and 208, thereby achieving different capacitance values for the different capacitors 202, 204, 206, and 208. See ¶[0010–0011] and ¶[0062–0067]. In particular: “The semiconductor arrangement 100 having the different capacitors with respective capacitances is implemented in a circuit in some embodiments” ¶[0067].
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, Liao-2016 teaches:
The method for forming a package structure 200 (FIG. 20) as claimed in claim 9, further comprising:
forming (FIG. 11) a conductive pillar 207 (“conductive through molding via (TMV) 207” ¶[0023]) over the second redistribution structure 204 before the protective layer 209 is formed (FIG. 12), wherein the conductive pillar 207 is electrically connected to the first conductive feature 204 (“the backside RDL 204 includes conductive features, including, for example, conductive lines and/or vias, formed in one or more polymer layers” ¶[0034]); and
forming (see FIG. 28)2 a first conductive bump 217a (“external connector 217a” ¶[0073]) and a second conductive bump 217b (“external connector 217b”) over the redistribution structure 212+214, wherein the first conductive bump 217a is electrically connected to the conductive pillar 207 (as shown in FIG. 28, “the conductive through molding via 207 is electrically coupled to the external connector 217a, through the RDLs 212 and 214” ¶[0073]).
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However, Liao-2016 fails to teach that the second conductive bump 217b is electrically connected to the second conductive feature 210. Rather, as shown in FIG. 28 and described in ¶[0073] of the specification, the second conductive bump 217b is electrically connected to the conductive pillar 2082 of the semiconductor chip 208, and the other conductive pillar 2081 of the semiconductor chip 208 is electrically connected to the second conductive feature 210. Thus, there is no direct electrical connection in FIG. 28 between the second conductive bump 217b and the second conductive feature 210.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Patent application publication US 2019/0157108 A1
See FIGS. 11 and 15
Relevant to claim 17
MIM capacitor 1120 laterally adjacent to die 800, surrounded by molding compound 900, and topped by redistribution layers 1210 and 1300
German patent application publication DE-102016100856-A1 (relying on attached machine translation) (drawings appear to be substantially the same as in Chen-2016 cited above)
See FIG. 28
Relevant to claim 17
vertical capacitor 100 laterally adjacent to device die 208, surrounded by molding layer 209, and topped by redistribution layers 212 and 214
Relevant to claims 1 and 11
“the value of the dielectric constant (or permittivity) of the dielectric material is greater than that of the molding compound MC”
“the molding compound MC in the molding layer is outside the semiconductor structure 100 applied to the die component 208 to surround, and the molding compound MC has a low dielectric constant, z. Less than about 3.9 and even less than about 2.5 in other embodiments”
“the dielectric material includes 160 a high-permittivity polymer … whose dielectric constant is greater than or equal to approximately 4”
“the dielectric constant of the dielectric material is 160 higher than that of the molding compound MC”
“the value of the dielectric constant (or permittivity) of the dielectric material is 160 larger than that of the molding compound MC”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.J.M./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
1 See rejection of claim 19 under 35 USC § 112(b) due to the indefiniteness of the adjective “grounding” in view of ¶[0062] of the specification and FIG. 1V of the drawings. For examination, the examiner will interpret the “grounding bump” to be any conductive bump that meets the connectivity requirements of claim 19.
2 FIG. 28 is similar to FIG. 20, but with the addition of a second external connector 217b; “the manufacturing process of the Integrated Fan-Out (InFO) package 200 illustrated in FIG. 28 is similar to the manufacturing process of the Integrated Fan-Out (InFO) package 200 illustrated in FIG. 20” ¶[0073].
Prosecution Insights