Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/30/26 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 02/26/26 have been fully considered but they are not persuasive.
Applicant argues, “In essence, the Examiner's withdrawal of claims 21-25 and claims 26-28 on the basis of a new restriction requirement fails to provide Applicant an opportunity to elect and/or traverse. While the MPEP allows an Examiner to withdraw claims through election by original presentation, this mechanism is only available after an office action on the merits. See MPEP 821.03. Accordingly, Applicant respectfully submits that the withdrawal of claims 21-25 and claims 26-28 is improper. Applicant requests that claims 21-25 and claims 26-28 be examined on the merits, or in the alternative, a proper restriction be issued to afford Applicant the opportunity to elect a subset of claims and/or traverse the restriction.
The Examiner has considered the Applicant’s arguments, but respectfully disagrees for the following reasons;
The Examiner takes the position that the response received on10/17/25 to the restriction requirement (issued on 08/21/25), elected to Group I of the original filed claims. The Examiner explained in the Non-Final action that the newly added claims, if present when the original claims were submitted, would have been restricted. The reasons for this decision was clear shown and will be repeated below.
Newly submitted claims #21-28 (hereinafter referred to as claims #21-25, Group II and claims #26-28, Group III) are directed to inventions that are independent or distinct from the invention originally claimed (claims #1-12; Group I) for the following reasons:
Inventions Group I and Group II are directed to related methods. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed by the method of Group II can be practice for it's intended purpose without requiring a plurality of semiconductor nanostructures; and a plurality of sacrificial layers, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly, which is required by the claimed method of Group I. Also, the invention as claimed in Group I can be practiced for it's intended purpose without requiring a method wherein replacing a dummy gate stack with a replacement gate stack, wherein the placement gate stack contacts the dielectric inner spacer, and wherein a portion of the replacement gate stack is between the first semiconductor layer and the second semiconductor layer, as required by the invention of the Group II claim language. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Inventions Group I and Group III are directed to related methods. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed by the method of Group III can be practice for it's intended purpose without requiring a plurality of semiconductor nanostructures; and a plurality of sacrificial layers, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly, which is required by the claimed method of Group I. Also, the invention as claimed in Group I can be practiced for it's intended purpose without requiring a method of forming a first portion contacting both of the gate stack and the semiconductor nanostructure; and forming a second portion separate from the gate stack and the semiconductor nanostructure by the first portion, as required by the invention of the Group III claim language. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
The Examiner takes the position that the constant adding of independent claims may be done, as long as the newly added claims are not directed to, nor create, a different claimed invention separate from the claimed invention of the originally filed claims. “The Examiner directs the Applicant to MPEP 35 U.S.C. 121 quoted in the preceding section states that the Director may require restriction if two or more "independent and distinct" inventions are claimed in one application. In 37 CFR 1.141, the statement is made that two or more "independent and distinct inventions" may not be claimed in one application.”
Furthermore, the Examiner takes the position that the Applicant cannot expect that every time the choice is made to add additional claims, that the process of examination will be started from the beginning. In theory, this type of expectation could result in a plethora of restriction action; thus, this would not embody compact prosecution.
For the above reasons, the Examiner takes the position that the requirement of the newly added claims to be restrict out was proper and maintained in the action as follows.
Applicant agues, ” Claim #1 recites "laterally recessing the plurality of sacrificial layers to form lateral recesses; depositing a first spacer layer extending into the lateral recesses, wherein the first spacer layer comprises a first dielectric material." Examiner asserted layer 220a as being the first spacer layer that comprises a first dielectric material SiP. Applicant respectfully disagrees.
The Examiner has considered the Applicant’s arguments and agrees. However, Examiner has shown below in the present action, using the presently relied on art of Chanemougame, wherein it is shown (paragraph 0057, 00769 and 0077) that the two materials within the recess sections are dielectrics of different make up, as required in the claim requirements of claim #1.
Claims #1-12 will be examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim #1-4, 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over CHENG (U.S. Pub. No, 2019/0348498), hereinafter referred to as "Cheng" and in view of Chanemougame et al., (U.S. Pub. No.2020/0083352), hereinafter referred to as "Chanemougame".
Cheng shows, with respect to claim #1, method comprising: forming a stack of layers (fig. #3a, item 206, 208) (paragraph 0027) comprising: a plurality of semiconductor nanostructures (fig. #6e, item 230) (paragraph 0025, 0034); and a plurality of sacrificial layers (fig. #9, item 212) (paragraph 0028), wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly (paragraph 0027); laterally recessing (fig. #Ex1, item LR1) the plurality of sacrificial layers to form lateral recesses (paragraph 0025); depositing a first spacer layer (fig. #10c, item 220a) extending into the lateral recesses (paragraph 0033).
[AltContent: textbox (Lateral Recess; LR1)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Ex1)]
PNG
media_image1.png
698
447
media_image1.png
Greyscale
Cheng substantially shows the claimed invention as shown in the rejection above.
Cheng fails to show, with respect to claim #1, a method comprising and trimming the first spacer layer and the second spacer layer to form inner spacers wherein the first spacer layer comprises a first dielectric material; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer comprises a second dielectric material different from the first dielectric material.
Chanemougame teaches, with respect to claim #1, a method comprising and trimming the first spacer layer (fig. #17a, item 135) and the second spacer layer (fig. #17a, item 118) to form inner spacers (paragraph 0057, 0076, 0077) wherein the first spacer layer (fig. #17a, item 118) comprises a first dielectric material (Silicon Nitride); depositing a second spacer layer (fig. #17a, item 135) on the first spacer layer (paragraph 0076), wherein the second spacer layer (fig. #17a, item 135) comprises a second dielectric material (titanium dioxide) different from the first dielectric material (fig. #17a, item 118; Silicon Nitride) (paragraph 0076).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #1, to modified the invention of Cheng as modified by the invention of Chanemougame, which teaches, a method comprising and trimming the first spacer layer and the second spacer layer to form inner spacers wherein the first spacer layer comprises a first dielectric material; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer comprises a second dielectric material different from the first dielectric material, to incorporate a structural condition wherein any of exposed portions of the dielectric is removed, as taught by Chanemougame.
Cheng shows, with respect to claim #2, a method wherein the second spacer layer (fig. #10c, item 242) comprises portions deposited into the lateral recesses (paragraph 0033, 0037).
Cheng shows, with respect to claim #3, a method wherein one of the inner spacers comprises a first portion (below; fig. #Ex2, item FP1) of the first spacer layer (fig. #10c, item 221a), and a second portion (below; fig. #Ex2, item SP1) of the second spacer layer (fig. #10c, item 220a) (paragraph 0032-0033, 0037).
[AltContent: textbox (Second Portion; SP1)][AltContent: textbox (First Portion; FP1)][AltContent: textbox (Ex2)]
PNG
media_image2.png
696
400
media_image2.png
Greyscale
Cheng substantially shows the claimed invention as shown in the rejection of claim #1 above.
Cheng fails to show, with respect to claim #4, a method wherein in the trimming, the first spacer layer has a higher etching rate than the second spacer layer.
Chanemougame teaches, with respect to claim #4, a method wherein in the trimming (paragraph 0057, 0076, 0077), the first spacer layer (fig. #17a, item 118; Silicon Nitride) has a higher etching rate than the second spacer layer (fig. #17a, item 135; titanium dioxide) (paragraph 0076).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #4, to modified the invention of Cheng as modified by the invention of Chanemougame, which teaches, a method wherein in the trimming, the first spacer layer has a higher etching rate than the second spacer layer, to incorporate a structural condition wherein any of exposed portions of the dielectric is removed, as taught by Chanemougame.
Cheng shows, with respect to claim #7, method comprising wherein each of the first spacer layer and the second spacer layer is deposited as a conformal layer (paragraph 0033, 0037).
Cheng shows, with respect to claim #8, method comprising further comprising removing the plurality of sacrificial layers through an etching process using an etching chemical, wherein inner sidewalls of the inner spacers are exposed to the etching chemical (paragraph 0031-0033).
Cheng shows, with respect to claim #9, a method wherein the first spacer layer (fig. #9c, item 211a; SiN, SiO, SiC, SiOC, SiOCN) comprises a hard shell and an outer portion formed of a material having a lower k value than the hard shell (paragraph 0032).
Cheng as modified by Chanemougame substantially shows the claimed invention as shown in the rejection of claim #8 above.
Cheng fails to show, with respect to claim #9, a method wherein in the removing the plurality of sacrificial layers, the hard shell is exposed to the etching chemical, and has a lower etching rate than the outer portion.
Chanemougame teaches, with respect to claim #9, a method wherein in the removing the plurality of sacrificial layers, the hard shell is exposed to the etching chemical, and has a lower etching rate than the outer portion (fig. #17a, item 118; SiN; K=7-7.5) (fig. #17a, item 135; titanium dioxide; K=30-100) (paragraph 0076-0077).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #9, to modified the invention of Cheng as modified by the invention of Chanemougame, which teaches, a method wherein in the removing the plurality of sacrificial layers, the hard shell is exposed to the etching chemical, and has a lower etching rate than the outer portion, to incorporate a structural condition wherein any of exposed portions of the dielectric is removed, as taught by Chanemougame.
Cheng as modified by Chanemougame substantially shows the claimed invention as shown in the rejection of claim #1 above.
Cheng fails to show, with respect to claim #10, a method wherein the first spacer layer has a first dielectric constant, and the second spacer layer has a second dielectric constant higher than the first dielectric constant.
Chanemougame teaches, with respect to claim #10, a method wherein the first spacer layer (fig. #17a, item 118; SiN; K=7-7.5) has a first dielectric constant, and the second spacer layer (fig. #17a, item 135; titanium dioxide, K=30-100) has a second dielectric constant higher than the first dielectric constant (paragraph 0076-0077).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #10, to modified the invention of Cheng as modified by the invention of Chanemougame, which teaches, a method wherein the first spacer layer has a first dielectric constant, and the second spacer layer has a second dielectric constant higher than the first dielectric constant, to incorporate a structural condition that can store more electrical energy in an electric field, which allows for smaller and more efficient electronic components, as taught by Chanemougame.
//
Claim #5, 6 are rejected under 35 U.S.C. 103 as being unpatentable over CHENG (U.S. Pub. No, 2019/0348498), hereinafter referred to as "Cheng" as modified by Chanemougame et al., (U.S. Pub. No.2020/0083352), hereinafter referred to as "Chanemougame" as shown in the rejection of claim #1 above and in further view of Ando et al., (U.S. Pub. No. 2019/0157414), hereinafter referred to as "Ando".
Cheng as modified by Chanemougame substantially shows the claimed invention as shown in the rejection of claim #1 above.
Cheng fails to show, with respect to claim #5, a method wherein the trimming comprises: a first stage performed using a first etching chemical, wherein the first stage has a first etching selectivity, and the first etching selectivity is equal to a ratio of an etching rate of the second spacer layer to an etching rate of the first spacer layer; and a second stage after the first stage, wherein the second stage is performed using a second chemical different from the first etching chemical
Chanemougame teaches, with respect to claim #5 a method wherein the trimming comprises: a first stage performed using a first etching chemical, and a second stage after the first stage, wherein the second stage is performed using a second chemical different from the first etching chemical (paragraph 0077).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #5, to modified the invention of Cheng as modified by the invention of Chanemougame, which teaches, a method wherein the trimming comprises: a first stage performed using a first etching chemical, and a second stage after the first stage, wherein the second stage is performed using a second chemical different from the first etching chemical to incorporate a structural condition wherein any of exposed portions of the dielectric is removed, as taught by Chanemougame.
Cheng as modified by Chanemougame substantially shows the claimed invention as shown in the rejection of claim #5 above.
Cheng as modified by Chanemougame fail to show, with respect to claim #5, a method wherein the first stage has a first etching selectivity, and the first etching selectivity is equal to a ratio of an etching rate of the second spacer layer to an etching rate of the first spacer layer.
Ando teaches, with respect to claim #5, a method wherein the first stage has a first etching selectivity, and the first etching selectivity is equal to a ratio of an etching rate of the second spacer layer to an etching rate of the first spacer layer (paragraph 0022, 0024-0025).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #5, to modified the invention of Cheng as modified by Chanemougame, with the modification by the invention of Ando, which teaches, a method wherein the first stage has a first etching selectivity, and the first etching selectivity is equal to a ratio of an etching rate of the second spacer layer to an etching rate of the first spacer layer, to incorporate a structural condition that has a clean and complete etching performance, as taught by Ando.
Cheng as modified by Chanemougame fail to show, with respect to claim #6, a method wherein the second stage has a second etching selectivity lower than the first etching selectivity.
Ando teaches, with respect to claim #6, a method wherein the second stage has a second etching selectivity lower than the first etching selectivity (paragraph 0022, 0024-0025).
The Examiner notes Ando discloses the claimed invention except for explicitly stating wherein the second stage has a second etching selectivity lower than the first etching selectivity. However, the Examiner notes that Ando shows (as can be seen from the sited areas above and throughout Ando’s invention) wherein various materials may be used for gap filing; therefore, providing opportunities for varying selectivity’s. Furthermore, the Examiner notes that the neither the present specification nor present claim language provides any detailed description (amount, ranges or preferred value) of the claimed selectivity as shown in claim #6. It would have been obvious to one having ordinary skill in the art at the time the invention was made to produce a selectivity stage wherein the second stage has a second etching selectivity lower than the first etching selectivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re A11er, 105 USPQ 233. Thus, it would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #6, to modified the invention of Cheng as modified by Chanemougame, with the modification by the invention of Ando, which teaches, a method wherein the second stage has a second etching selectivity lower than the first etching selectivity, to incorporate a structural condition that has a clean and complete etching performance, as taught by Ando.
Allowable Subject Matter
Claims #11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. While the prior art teaches a method comprising: forming a stack of layers comprising: a plurality of semiconductor nanostructures; and a plurality of sacrificial layers, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly; laterally recessing the plurality of sacrificial layers to form lateral recesses; depositing a first spacer layer extending into the lateral recesses, wherein the first spacer layer comprises a first dielectric material; depositing a second spacer layer on the first spacer layer, wherein the second spacer layer comprises a second dielectric material different from the first dielectric material, (CHENG, 2019/0348498; Chanemougame et al., 2020/0083352; Ando et al., 2019/0157414), it fails to teach either collectively or alone, with respect to claim #11, a method further comprising: depositing a third spacer layer on the second spacer layer, wherein the third spacer layer has a third dielectric constant higher than the second dielectric constant.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
04/13/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights