DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 2/25/2026 is acknowledged.
Applicant amended claims 1 and 21; and cancelled claim 7.
Applicant added claim 25.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2021/0126113) (hereafter Lin), in view of Lim et al. (US 2021/0036121) (hereafter Lim).
Regarding claim 21, Lin discloses a method of fabricating a semiconductor device, comprising:
forming a fin-shaped base 105 (Fig. 8B, paragraph 0021) protruding from a substrate 201 (Fig. 8B, paragraph 0024);
depositing an isolation structure 209 (Fig. 8B, paragraph 0030) on sidewalls of the fin-shaped base 105 (Fig. 8B);
forming a plurality of nanostructures 701 (Fig. 8B, paragraph 0081) vertically stacked over the fin-shaped base 105 (Fig. 8B);
forming a gate structure 107 (Figs. 1 and 8A, paragraph 0081) extending lengthwise in a first direction (vertical direction in Fig. 1) and wrapping around at least one of the nanostructures 701 (Fig. 8A);
depositing gate spacers 403 (Fig. 8A, paragraph 0047) on sidewalls of the gate structure 107 (Fig. 8A);
forming a first trench 901 (Fig. 9B, paragraph 0090) dividing the gate structure 107 (Fig. 9B) into segments, wherein the first trench 901 (Fig. 9B) extends lengthwise (see region where 109 is formed in Fig. 1) in a second direction (horizontal direction in Fig. 1) different from the first direction (vertical direction in Fig. 1);
depositing a first isolation feature 109 (Fig. 10B, paragraph 0090) in the first trench 901 (Fig. 9B);
after the depositing of the first isolation feature 109 (Fig. 10B), etching (see Figs. 11A and 12A) the gate structure 107 (Fig. 10A) and the nanostructures 701 (Fig. 10A) to form a second trench 1003 (Fig. 12A, paragraph 0097) disposed between the gate spacers 403 (Fig. 12A), wherein the second trench 1003 (Fig. 12A) extends lengthwise (see region where 111 is formed in Fig. 1) in the first direction (vertical direction in Fig. 1); and
depositing a second isolation feature 111 (Fig. 13A, paragraph 0099) in the second trench 1003 (Fig. 12A), wherein the second isolation feature 111 (Fig. 1) intersects the first isolation feature 109 (Fig. 1) when viewed from top.
Lin does not disclose a bottom portion of the second isolation feature is below a bottom surface of the isolation structure.
Lim discloses a bottom portion of the second isolation feature 200a (Fig. 24, paragraph 0036) is below a bottom surface of the isolation structure 110 (Fig. 24, paragraph 0039).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form a bottom portion of the second isolation feature is below a bottom surface of the isolation structure, as taught by Lim, since the lower end of the isolation structure 200a (Lim, Fig. 24, paragraph 0057) may be disposed to be lower than the lower end of the active region 105 (Lim, Fig. 24, paragraph 0057) by a predetermined depth such that the isolation structure 200a (Lim, Fig. 24, paragraph 0061) may be disposed between adjacent source/drain regions 150 (Lim, Fig. 24, paragraph 0061) to prevent diffusion of impurities included in the adjacent source/drain regions 150 (Lim, Fig. 24, paragraph 0061).
Regarding claim 22, Lin further discloses the method of claim 21, wherein the second isolation feature 111 (Fig. 13B) covers a top surface (see Fig. 13B, wherein 111 covers the lower top surface of 109) of the first isolation feature 109 (Fig. 13B).
Regarding claim 23, Lin further discloses the method of claim 21, wherein a width of the second isolation feature 111 (Fig. 1) is greater (see Fig. 1, wherein 111 has larger length in vertical direction than 109) than a width of the first isolation feature 109 (Fig. 1), and a depth of the second isolation feature 111 (Fig. 13B) is greater than a depth of the first isolation feature 109 (Fig. 13B).
Regarding claim 24, Lin discloses the method of claim 21, however Lin does not disclose the second isolation feature has a necking profile in a cross-section of the semiconductor device.
Lim discloses the second isolation feature 200e (Fig. 5B, paragraph 0074) has a necking profile in a cross-section of the semiconductor device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form the second isolation feature has a necking profile in a cross-section of the semiconductor device, as taught by Lim, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a convex shape from the shapes listed in paragraph 0056 of Lin (e.g. flat surface, a convex, or a sharp shape); if this leads to the anticipated success, in the instant case providing an isolation structure to separate the plurality of transistors from each other, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Allowable Subject Matter
Claims 1-6 and 8-16 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Lin et al. (US 2021/0126113), discloses inner spacers 403 (Fig. 4A, paragraph 0077) disposed between adjacent ones of the plurality of channel layers 207 (Fig. 4A); and depositing a second isolation feature 111 (Fig. 13A, paragraph 0099) in the second trench 1003 (Fig. 12A), wherein the second isolation feature 111 (Fig. 1) intersects the first isolation feature 109 (Fig. 1) in a top view of the semiconductor device but fails to disclose a bottom portion of the second isolation feature is directly under a bottommost one of the inner spacers. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method of fabricating a semiconductor device, comprising: a bottom portion of the second isolation feature is directly under a bottommost one of the inner spacers in combination with other elements of claim 1.
In addition, a closest prior art, Lin et al. (US 2021/0126113), discloses forming first (first 107 from the left corner of Fig. 1, paragraph 0021), second (second 107 from the left corner of Fig. 1, paragraph 0021), and third gate structures (third 107 from the left corner of Fig. 1, paragraph 0021) across the fin element 105 (Fig. 1), each of the first (first 107 from the left corner of Fig. 1), second (second 107 from the left corner of Fig. 1), and third gate structures (third 107 from the left corner of Fig. 1) extending lengthwise along a second direction (vertical direction in Fig. 1) perpendicular to the first direction (horizontal direction in Fig. 1); and forming first (left 901 in Fig. 9B, paragraph 0090) and second trenches (right 901 in Fig. 9B, paragraph 0090) sandwiching the fin element 105 (Fig. 9B) and extending lengthwise (see regions where top 109 and bottom 109 are formed in Fig. 1) in the first direction (horizontal direction in Fig. 1) but fails to disclose each of the first and second trenches intersecting the first, second, and the third gate structures; and replacing the first and third gate structures with third and fourth isolation features, respectively. Additionally, the prior art does not teach or suggest a method, comprising: each of the first and second trenches intersecting the first, second, and the third gate structures; and replacing the first and third gate structures with third and fourth isolation features, respectively in combination with other elements of claim 11.
A closest prior art, Lin et al. (US 2021/0126113), discloses a method of fabricating a semiconductor device, comprising: providing a dummy structure (203 and 301 in Fig. 4A, paragraphs 0029 and 0035) including a plurality of channel layers 207 (Fig. 4A, paragraph 0077) disposed over a substrate 201 (Fig. 4A, paragraph 0024), inner spacers 403 (Fig. 4A, paragraph 0077) disposed between adjacent ones of the plurality of channel layers 207 (Fig. 4A), and a gate structure 107 (Fig. 8A, paragraph 0081) interposing the plurality of channel layers 701 (Fig. 8A, paragraph 0081) and extending lengthwise (see 107 in Fig. 1) in a first direction (vertical direction in Fig. 1); forming a first trench 901 (Fig. 9B, paragraph 0090) dividing the gate structure 107 (Fig. 9B) into segments, wherein the first trench 901 (Fig. 9B) extends lengthwise (see region where 109 is formed in Fig. 1) in a second direction (horizontal direction in Fig. 1) perpendicular to the first direction (vertical direction in Fig. 1); depositing a first isolation feature 109 (Fig. 10B, paragraph 0090) in the first trench 901 (Fig. 9B); etching (see Figs. 11A and 12A) the gate structure 107 (Fig. 10A) and the plurality of channel layers 701 (Fig. 10A) to form a second trench 1003 (Fig. 12A, paragraph 0097), wherein the second trench 1003 (Fig. 12A) extends lengthwise (see region where 111 is formed in Fig. 1) in the first direction (vertical direction in Fig. 1) and exposes the inner spacers 403 (Fig. 12A); and depositing a second isolation feature 111 (Fig. 13A, paragraph 0099) in the second trench 1003 (Fig. 12A), wherein the second isolation feature 111 (Fig. 1) intersects the first isolation feature 109 (Fig. 1) in a top view of the semiconductor device but fails to teach a bottom portion of the second isolation feature is directly under a bottommost one of the inner spacers as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-6 and 8-10 depend on claim 1.
In addition, a closest prior art, Lin et al. (US 2021/0126113), discloses a method, comprising: forming a fin element 105 (Figs. 1 and 8A, paragraph 0030) over a substrate 201 (Fig. 8A, paragraph 0030) and extending lengthwise along a first direction (horizontal direction in Fig. 1); forming first (first 107 from the left corner of Fig. 1, paragraph 0021), second (second 107 from the left corner of Fig. 1, paragraph 0021), and third gate structures (third 107 from the left corner of Fig. 1, paragraph 0021) across the fin element 105 (Fig. 1), each of the first (first 107 from the left corner of Fig. 1), second (second 107 from the left corner of Fig. 1), and third gate structures (third 107 from the left corner of Fig. 1) extending lengthwise along a second direction (vertical direction in Fig. 1) perpendicular to the first direction (horizontal direction in Fig. 1); forming first (left 901 in Fig. 9B, paragraph 0090) and second trenches (right 901 in Fig. 9B, paragraph 0090) sandwiching the fin element 105 (Fig. 9B) and extending lengthwise (see regions where top 109 and bottom 109 are formed in Fig. 1) in the first direction (horizontal direction in Fig. 1); and forming first (left 109 in Fig. 9B, paragraph 0090) and second isolation features (right 109 in Fig. 9B, paragraph 0090) in the first (left 901 in Fig. 9B) and second trenches (right 901 in Fig. 9B), respectively but fails to teach each of the first and second trenches intersecting the first, second, and the third gate structures; and replacing the first and third gate structures with third and fourth isolation features, respectively as the context of claim 11. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 12-16 depend on claim 11.
3. Claim 25 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
4. Claim 25 would be allowable because a closest prior art, Lin et al. (US 2021/0126113), discloses depositing an isolation structure 209 (Fig. 8B, paragraph 0030) on sidewalls of the fin-shaped base 105 (Fig. 8B); and depositing a second isolation feature 111 (Fig. 13A, paragraph 0099) in the second trench 1003 (Fig. 12A) but fails to disclose the bottom portion of the second isolation feature is directly under the bottom surface of the isolation structure. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method of fabricating a semiconductor device, comprising: the bottom portion of the second isolation feature is directly under the bottom surface of the isolation structure in combination with other elements of the base claim 1.
Response to Arguments
1. Applicant's arguments filed 2/25/2026 have been fully considered.
Applicant's arguments with respect to claims 21-24 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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