Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-17 in the reply filed on 11/3/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/1/2023 and 7/18/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. US 2018/0315821.
Re claim 12, Xie teaches a method of forming a semiconductor structure (100, fig4A-4L, [70]), comprising:
providing a semiconductor substrate (102, fig4A, [28]) having a source/drain feature (124, fig4A, [34]) and a gate structure (GL 110, fig4A, [32]) formed thereon;
forming an interlayer dielectric layer (114, fig4A, [33]) on the semiconductor substrate;
patterning the interlayer dielectric layer (114, fig4A, [33]) to form a trench (114X, fig4A, [62]) to expose the source/drain feature (124, fig4A, [34]) within the trench;
forming a silicide layer (metal silicide formed after pre-clean process, fig4B, [63]) on the source/drain feature;
filling a metal layer (116, fig4B, [63]) on the silicide layer within the trench;
forming a patterned mask (150, 121, fig4C, [65]) with an opening, wherein a first portion of the metal layer is exposed within the opening (exposed part of 116 between 150 and 114, fig4C) and a second portion of the metal layer is covered by the patterned mask (part of 116 under 150, fig4C), and wherein the second portion is extending to the second portion in the trench (fig4D); and
etching the metal layer (fig4D) through the opening of the patterned mask such that the first portion (exposed part of 116 between 121 and 114, fig4C-4D) of the metal layer is recessed, and the second portion of the metal layer remains (part of 116 under 150, fig4C-4D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-11, 13-15, 17 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. US 2018/0315821 in view of Jiang et al. US 2020/0328154.
Re claim 1, Xie teaches a method of forming a semiconductor structure (100, fig4A-4L, [70]), comprising:
providing a semiconductor substrate (102, fig4A, [28]) having a source/drain feature (124, fig4A, [34]) and a gate structure (GL 110, fig4A, [32]) formed thereon;
forming an interlayer dielectric layer (114, fig4A, [33]) on the semiconductor substrate;
patterning the interlayer dielectric layer (114, fig4A, [33]) to form a trench (114X, fig4A, [62]) to expose the source/drain feature (124, fig4A, [34]) within the trench;
filling a metal layer (116, fig4B, [63]) in the trench;
recessing a portion of the metal layer in the trench (fig4D), thereby forming a recess (153, fig4D, [65]) in the metal layer; and
refilling a dielectric material layer (145, fig4E, [66]) in the recess.
Xie does not explicitly show forming a dielectric liner on sidewalls of the trench.
Jiang teaches forming a dielectric liner (160, fig13, [36]) on sidewalls of the trench with exposed S/D feature (102S/D, [36]); filling a metal layer (170, fig13, [37]) in the trench;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie and Jiang to add a dielectric liner under the metal contact. The motivation to do so is to improve bonding of the contact metal and suppress diffusion of the contact metal (Jiang, [36]).
Re claim 2, Xie modified above teaches the method of claim 1, wherein the recessing (153, fig4D, [65]) the portion of the metal layer includes etching the portion of the metal layer thereby forming a contact (lower part of 116 in contact with both sides of 114, fig4E, [63]) and a via (top part of 116 in contact with 121, fig4E) self-aligned with the contact.
Re claim 3, Xie modified above teaches the method of claim 2, wherein the dielectric material layer (145 as SiOCN, fig4E, [66]) is different from the dielectric liner (Jiang berried/adhesive layer as SiON added directly under Xie 116, fig4E) and the interlayer dielectric layer (114 as SiO2, fig4A, [33]) in composition.
Re claim 4, Xie modified above teaches the method of claim 3, wherein the dielectric material layer includes silicon nitride (145 as SiOCN, fig4E, [66]; SiOCN comprising Silicon oxide , silicon carbide and silicon nitride, see teaching reference Tomczak et al. US 2023/0059464 [36]); the dielectric liner includes at least one of silicon oxide and silicon oxynitride (Jiang berried/adhesive layer as SiON added directly under Xie 116, fig4E); and the interlayer dielectric layer includes a low-k dielectric material (114 as SiO2, fig4A, [33]).
Re claim 6, Xie modified above teaches the method of claim 1, wherein the forming the interlayer dielectric layer (114, fig4A, [33]) further includes forming an etch stop layer (112, fig4A, [32]) underlying the interlayer dielectric layer.
Re claim 7, Xie modified above teaches the method of claim 6, the recessing the portion of the metal layer (fig4D) in the trench includes forming a patterned dielectric layer (121, fig4D, [64]) by a lithography process and an etching process (150, fig4C, [65]); and recessing the metal layer (116, fig4D, [63]) using the interlayer dielectric layer (114, fig4D, [33]) and the patterned dielectric layer (121, fig4D, [64]) as a collective etch mask.
Re claim 8, Xie modified above teaches the method of claim 7, the recessing the portion of the metal layer (116, fig4D, [63]) in the trench includes recessing the portion of the metal layer such that a top surface of the recessed portion (116R, fig4D, [65]) of the metal layer is below a bottom surface of the etch stop layer (112, fig4D, [32]).
Re claim 9, Xie modified above teaches the method of claim 1, wherein the refilling of the dielectric material layer (145, fig4E, [66]) in the recess includes depositing the dielectric material layer in the recess; and performing a chemical mechanical polishing process to the dielectric material layer (fig4G, [67]).
Re claim 10, Xie modified above teaches the method of claim 1, wherein the dielectric liner (Jiang berried/adhesive layer as SiON added directly under Xie 116 around 114, fig4G) is enclosing the dielectric material layer (145, fig4G, [66]) and the metal layer (116, fig4G, [63]) in a top view.
Re claim 11, Xie modified above teaches the method of claim 2, wherein the contact (lower part of 116 in contact with both sides of 114 , fig4G, [63]) is overlapped with the dielectric material layer (145, fig4G, [66]) and the via (tip part of 116 under 121, fig4D) in a top view.
Re claim 13, Xie teaches the method of claim 12, refilling a dielectric material layer (145, fig4E, [66]) in the recess after the etching the metal layer.
Xie does not explicitly show further comprising forming a dielectric liner on sidewalls of the trench prior to the filling the metal layer in the trench.
Jiang teaches forming a dielectric liner (160, fig13, [36]) on sidewalls of the trench with exposed S/D feature (102S/D, [36]); filling a metal layer (170, fig13, [37]) in the trench;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie and Jiang to add a dielectric liner under the metal contact. The motivation to do so is to improve bonding of the contact metal and suppress diffusion of the contact metal (Jiang, [36]).
Re claim 14, Xie modified above teaches the method of claim 13, wherein the dielectric liner (Jiang berried/adhesive layer as SiON added directly under Xie 116 around 114, fig4G) is enclosing the dielectric material layer (145, fig4G, [66]) and the metal layer (116, fig4G, [63]) in a top view; and the contact (part of 116 with top surface 116R, fig4G) is completely overlapped with the dielectric material layer (145, fig4G, [66]) and the via in a top view.
Re claim 15, Xie modified above teaches the method of claim 13, wherein the dielectric material layer (145 as SiOCN, fig4G, [66]) is different from the dielectric liner (Jiang berried/adhesive layer as SiON added directly under Xie 116, fig4E) and the interlayer dielectric layer (114 as SiO2, fig4A, [33]) in composition; and the dielectric liner is continuously extending from a sidewall of the second portion of the metal layer from top to bottom (barrier formed between 114 and 116, fig4E).
Re claim 17, Xie modified above teaches the method of claim 12, further comprising forming an etch stop layer (112, fig4A, [62]) underlying the interlayer dielectric layer (114, fig4A, [33]), wherein the etching the metal layer includes recessing the first portion of the metal layer such that a top surface of the recessed first portion of the metal layer (116R, fig4D, [65]) is below a top surface of the etch stop layer (112, fig4A, [62]).
Re claim 21, Xie teaches a method of forming a semiconductor structure (100, fig4A-4L, [70]), comprising:
providing a semiconductor substrate (102, fig4A, [28]) having a source/drain feature (124, fig4A, [34]) and a gate structure (GL 110, fig4A, [32]) formed thereon;
forming an interlayer dielectric layer (114, fig4A, [33]) on the semiconductor substrate;
patterning the interlayer dielectric layer to form a trench (114X, fig4A, [62]) to expose the source/drain feature within the trench;
forming a silicide layer (metal silicide formed after pre-clean process, fig4B, [63]) on the source/drain feature;
filling a metal layer (116, fig4B, [63]) on the silicide layer within the trench;
forming a patterned mask (150, 121, fig4C, [65]) with an opening, wherein a first portion (exposed part of 116 between 121 and 114, fig4C) of the metal layer is exposed within the opening and a second portion (part of 116 under 150, fig4C) of the metal layer is covered by the patterned mask, and
wherein the second portion is extending to the second portion in the trench (fig4D); and
etching the metal layer through the opening of the patterned mask such that the first portion of the metal layer is recessed to form a recess (153, fig4D, [65]), and
the second portion of the metal layer remains (part of 116 under 150, fig4C-4D), thereby forming a contact (lower part of 116 in contact with both sides of 114 , fig4E, [63]) and a via (top part of 116 in contact with 121, fig4E) self-aligned with the contact; and
refilling a dielectric material (145, fig4E, [66]) layer in the recess.
Xie does not explicitly show forming a dielectric liner on sidewalls of the trench.
Jiang teaches forming a dielectric liner (160, fig13, [36]) on sidewalls of the trench with exposed S/D feature (102S/D, [36]); filling a metal layer (170, fig13, [37]) in the trench;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie and Jiang to add a dielectric liner under the metal contact. The motivation to do so is to improve bonding of the contact metal and suppress diffusion of the contact metal (Jiang, [36]).
Re claim 22, Xie modified above teaches the method of claim 21, wherein the contact (lower part of 116 in contact with both sides of 114 , fig4E, [63]) is overlapped with the dielectric material layer (145, fig4E, [66]) and the via (top part of 116 in contact with 121, fig4E) in a top view; the dielectric material layer includes silicon nitride (145 as SiOCN, fig4E, [66]; SiOCN comprising silicon oxide , silicon carbide and silicon nitride, see teaching reference Tomczak et al. US 2023/0059464 [36]); the dielectric liner includes at least one of silicon oxide and silicon oxynitride (Jiang berried/adhesive layer as SiON added directly under Xie 116 around 114, fig4G); and the interlayer dielectric layer includes a low-k dielectric material (114 as SiO2, fig4A, [33]).
Claim(s) 5, 16 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. US 2018/0315821 in view of Jiang et al. US 2020/0328154 and Lin et al. US 2022/0051940.
Re claim 5, Xie does not explicitly show the method of claim 1, wherein the forming the dielectric liner includes depositing a dielectric film on surfaces of the trench and applying an anisotropic etch to the dielectric film.
Lin teaches forming the dielectric liner (224, fig5, [22]) includes depositing a dielectric film (224, fig4, [21]) on surfaces of the trench and applying an anisotropic etch (fig5, [22]) to the dielectric film.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie modified above and Lin to open the bottom part of the dielectric liner. The motivation to do so is to reduce contact resistance (Lin, [12]).
Re claim 16, Xie does not explicitly show the method of claim 15, wherein the forming the dielectric liner includes depositing a dielectric film on surfaces of the trench and applying an anisotropic etch to the dielectric film.
Lin teaches forming the dielectric liner (224, fig5, [22]) includes depositing a dielectric film (224, fig4, [21]) on surfaces of the trench and applying an anisotropic etch (fig5, [22]) to the dielectric film.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie modified above and Lin to open the bottom part of the dielectric liner. The motivation to do so is to reduce contact resistance (Lin, [12]).
Re claim 23, Xie modified above teaches the method of claim 21, wherein the forming the dielectric liner (Jiang berried/adhesive layer as SiON added directly under Xie 116 around 114, fig4G) includes depositing a dielectric film on surfaces of the trench; the forming the interlayer dielectric layer (114, fig4A, [33]) further includes forming an etch stop layer (112, fig4A, [62]) underlying the interlayer dielectric layer; and the etching of the metal layer includes recessing the first portion of the metal layer such that a top surface of the recessed portion of the metal layer (116R, fig4D, [65]) is below a bottom surface of the etch stop layer (112, fig4D, [62]).
Xie does not explicitly show applying an anisotropic etch to the dielectric film.
Lin teaches forming the dielectric liner (224, fig5, [22]) includes depositing a dielectric film (224, fig4, [21]) on surfaces of the trench and applying an anisotropic etch (fig5, [22]) to the dielectric film.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Xie modified above and Lin to open the bottom part of the dielectric liner. The motivation to do so is to reduce contact resistance (Lin, [12]).
Conclusion
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/XIAOMING LIU/ Examiner, Art Unit 2812