Prosecution Insights
Last updated: April 19, 2026
Application No. 18/298,819

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Apr 11, 2023
Examiner
PHAM, LONG
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co. Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1493 granted / 1633 resolved
+23.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
38 currently pending
Career history
1671
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
39.9%
-0.1% vs TC avg
§102
41.8%
+1.8% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1633 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of claims 1-3 and 5-10 in the reply filed on 12/29/25 is acknowledged. The traversal is on the ground(s) that see the election of 12/29/25. This is not found persuasive because the consideration and searches of patentable distinct species are not co-extensive. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5, 6, 7, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US pat 11948891). With respect to claim 1, Park et al. teach an electronic package, comprising (see figs. 1-26, particularly fig. 5 and associated text): an electronic module including a carrier 140, an electronic component 124, a plurality of conductive structures 115 and a plurality of conductive components 112 disposed on the carrier, wherein the electronic component, the plurality of conductive structures and the plurality of conductive components are electrically connected to the carrier; an encapsulation layer 140” formed on the carrier and encapsulating the electronic component, the plurality of conductive structures and the plurality of conductive components; a shielding layer 150 (top part and side part down to about 140”) formed on the encapsulation layer and covering the electronic component, wherein the shielding layer is electrically connected to the plurality of conductive structures and free from being electrically connected to the plurality of conductive components; and a shielding structure (the end portion of 150 on side) covering the electronic module. With respect to claim 5, Park et al. teach each of the plurality of conductive structures is in a form of a metal pillar, a wire, or a combination of bumps. See fig. 5 and associated text. With respect to claim 6, Park et al. teach each of the plurality of conductive components is in a form of a solder ball or a combination of bumps. See fig. 5 and associated text. With respect to claim 7, Park et al. teach the carrier has a first side (top) and a second side (bottom) opposing the first side, wherein the encapsulation layer, the electronic component, the plurality of conductive structures and the plurality of conductive components are formed on the second side of the carrier. See fig. 5 and associated text. With respect to claim 8, Park et al. teach another electronic component 121 disposed on the first side of the carrier. See fig. 5 and associated text. With respect to claim 9, Park et al. teach the electronic module further comprises a packaging layer 160 encapsulating the another electronic component. See fig. 5 and associated text. Allowable Subject Matter Claims 2-3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having and encapsulated structure having a component, conductive structures, and connectors over and electrically connected to a carrier, a shielding layer covering the component and electrically connected to conductive structures and not electrically connected to the connectors, a shielding structure covering the structure as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Apr 11, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604733
PACKAGE STRUCTURES WITH COLLAPSE CONTROL FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604754
PACKAGE STRUCTURES WITH NON-UNIFORM INTERCONNECT FEATURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604766
SEMICONDUCTOR PACKAGE STRUCTURE
2y 5m to grant Granted Apr 14, 2026
Patent 12604739
Semiconductor Device and Method of Forming a 3-D Stacked Semiconductor Package Structure
2y 5m to grant Granted Apr 14, 2026
Patent 12599033
QUASI-MONOLITHIC INTEGRATED PACKAGING ARCHITECTURE WITH MID-DIE SERIALIZER/DESERIALIZER
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+5.6%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1633 resolved cases by this examiner. Grant probability derived from career allow rate.

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