Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 12/08/2025.
Claims 16-35 are currently pending.
Claims 16, 18, and 20 have been amended.
Claims 1-15 have been canceled.
Claims 16-35 have been examined.
Election/Restriction
Applicant's election without traverse of claims 16-20 and new claims 21-35 of Group II., in the reply filed on 12/08/2025, is acknowledged. Currently there are no pending claims to Group I.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/12/2023, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE ALL AROUND SEMICONDUCTOR STRUCTURE WITH DIELECTRIC STRUCTURES OF DIFFERENT WIDTHS AND METHODS OF FORMING THE SAME
Claim Objections
Claims 31-35 are objected to because of the following informalities:
Claim 31 introduces a second dielectric structure before introducing a first dielectric structure which in dependent claims 33-35 are rectified by the introduction of a first dielectric structure. Claim 32 never introduces a first dielectric structure. While the claim tree related to independent claim 31 is logically consistent internally, an average reader would naturally search for a first material before looking for a second material. Applicant is advised amend claims 31-35 renaming the first and second dielectrics as appropriate avoid possible confusion.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-35 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chiang et al. US 20240258415 A1 (hereinafter Chiang).
The applied reference has common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Annotated Fig. 3 will be used in discussion below.
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Regarding claim 16, Chiang discloses: A method for forming a semiconductor structure, (Figs. 2-26D include the method of semiconductor device.) comprising:
forming a first fin structure and a second fin structure over a substrate, (annotated Fig. 3, first fin structure F1 and second fin structure F2 over a substrate 50.) wherein the first fin structure comprises first semiconductor material layers (Fig. 3 and [0027] and [0055], second nanostructure 54 and third semiconductor layer 57A and fifth semiconductor layer 57B which can be made of silicon.) and second semiconductor material layers alternately stacked (Fig. 3 and [0027] and [0055], first nanostructure 52 and fourth nanostructure 56 made of silicon-germanium.), and the second fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked; (Fig. 3, the first fin structure F1 and second fin structure F2 have the same layers in an alternating stack.)
forming a dummy gate structure (Fig. 5A, dummy gate structure includes dummy dielectric layer 71, dummy gate 76, and mask 78.) over and between the first fin structure and the second fin structure; (See Fig. 5A.)
removing a topmost first semiconductor layer and a topmost second semiconductor layer to form a recess; (Fig. 7A, second recesses 87 are formed by removing third semiconductor layer 57B and fourth semiconductor layer 56.)
forming a protective layer in the recess, wherein the protective layer is formed over the first fin structure and the second fin structure; (Fig. 8A, hard mask structure 84 is formed in the recess 87 over first fin structure F1 and second fin structure F2.)
removing a portion of the dummy gate structure to expose a trench between the first fin structure and the second fin structure; (Fig. 9C, dummy gate structure is removed between the first fin structure F1 and second find structure F2.)
forming an oxide layer (Fig. 14B, liner 102.) and a first dielectric structure (isolation walls 104.) in the trench, wherein the first dielectric structure is between the first fin structure and the second fin structure, and the first dielectric structure is through the protective layer; (See Fig. 14B, liner 102 and isolation walls 104 is formed through hard mask structure 84.)
removing the first semiconductor material layers to expose the second semiconductor material layers; and (Fig. 19B, exposing the second nanostructures 54.)
forming a gate structure to surround the second semiconductor material layers. (Fig. 21B, gate electrode 108 formed around second nanostructures 54.)
Regarding Claim 17, Chiang further discloses:
forming a third fin structure adjacent to the second fin structure, (annotated Fig. 3, third fin structure F3) wherein the third fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked; (Fig. 3, the third fin structure F3 has the same layers in an alternating stack as the first and second fin structures F1 and F2.)
forming the dummy gate structure over the third fin structure; (Fig. 5A, dummy gate structure includes dummy dielectric layer 71, dummy gate 76, and mask 78 over the third fin structure F3.)
forming the protective layer over the third fin structure; (Fig. 8A, hard mask structure 84 is formed in the recess 87 over third fin structure F3.)
removing the second semiconductor material layers of the third fin structure to expose the first semiconductor material layers of the third fin structure; (Fig. 21B, first nanostructure 52 are removed from the third fin structure F3.)
forming the gate structure to surround the first semiconductor material layers of the third fin structure; and (Fig. 21B, gate electrode 108 formed around second nanostructures 54.)
forming a conductor layer between the first semiconductor material layers of the second fin structure and the first semiconductor material layers of the third fin structure. (Fig. 21B, gate electrode 108 forms a layer that is between that between the second nanostructure layers 54 of the second fin structure F2 and the third fin structure F3.)
Regarding Claim 18, Chiang further discloses:
removing a portion of the oxide layer to expose a sidewall surface of the first dielectric structure; and (Fig. 19B, removing liner 102 to expose side walls of first isolation walls 104.)
forming a gate dielectric layer on the sidewall surface of the first dielectric structure. (Fig. 20B, gate dielectric 106 is deposited on the side walls of the first isolation walls 104.)
Regarding Claim 19, Chiang further discloses:
removing a portion of the first fin structure and a portion of the second fin structure, (Fig. 17B, removes a portion of the first and second fin structures F1 and F2.)
wherein a sidewall surface of the protective layer extends beyond a sidewall surface of the first fin structure. (See Fig. 17B, hard mask 84 has an overhang of the underlying first fin structure F1.)
Regarding Claim 20, Chiang further discloses:
wherein the first dielectric structure has an extending portion which is directly above the gate structure. (annotated Fig. 21B, 104_ep is directly above the gate electrode 108.)
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Regarding Claim 21, Chiang further discloses:
removing a portion of the gate structure to form a trench; and (Fig. 23B, portion of gate electrode 108 is removed to form third recesses 105.)
forming a second dielectric structure in the trench, (Fig. 26B, second isolation wall 110 and second ILD 116 and the second isolation wall is formed in third recess 105.) wherein a top surface of the second dielectric structure is higher than a top surface of the protective layer. (See Fig. 26B, the top surface of the second ILD 116 is higher than the top surface of the hard mask 84.)
Regarding Claim 22, Chiang further discloses:
removing the second semiconductor material layers to form a plurality of nanostructures, wherein a top surface of the first dielectric structure is higher than a topmost surface of the nanostructures. (Fig. 18B, removing first nanostructure 52 is removed leaving a plurality of nanostructures 54 and the top surface of the first isolation walls 104 is higher than the top surface of the nanostructures 54.)
Regarding Claim 23, Chiang further discloses:
forming an isolation structure over the substrate, (Fig. 4B, isolation regions 68 over substrate 50.) wherein the first dielectric structure is on the isolation structure. (Fig. 14B, first isolation wall 104 is on the isolation regions 68.)
Regarding Claim 24, Chiang further discloses:
forming a gate contact structure on the gate structure, wherein the gate contact structure is through the protective layer. (Fig. 26B, gate contact 114 is formed through hard mask 84)
Regarding Claim 25, Chiang further discloses:
removing a portion of the first fin structure to form a notch; and (Fig. 19B, second nanostructures 54 has portions removed to create notch.)
forming an inner spacer layer in the notch, (Fig. 20B, interfacial layer 106′ is formed within the notch created by the trimming of the nanostructure 54.) wherein the protective layer (hard mask 84) is higher than a topmost surface of the inner spacer layer. (Fig. 20B, hard mask 84 is higher than the interfacial layer 106’.)
Regarding Claim 26, Chiang discloses:
A method for forming a semiconductor structure, Figs. 2-26D include the method of semiconductor device.) comprising:
forming a first fin structure and a second fin structure over a substrate, (annotated Fig. 3, first fin structure F1 and second fin structure F2 over a substrate 50.) wherein the first fin structure comprises first semiconductor material layers (Fig. 3 and [0027] and [0055], second nanostructure 54 and third semiconductor layer 57A and 57B which can be made of silicon.) and second semiconductor material layers alternately stacked, (Fig. 3 and [0027] and [0055], first nanostructure 52 and fourth nanostructure 56 made of silicon-germanium.), and the second fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked; (Fig. 3, the first fin structure F1 and second fin structure F2 have the same layers in an alternating stack.)
removing a topmost first semiconductor layer and a topmost second semiconductor layer to form a recess; (Fig. 7A, second recesses 87 are formed by removing third semiconductor layer 57B and fourth semiconductor layer 56.)
forming a protective layer in the recess; (Fig. 8A, hard mask structure 84 is formed in the recess 87.)
forming a dummy gate structure (Fig. 5A, dummy gate structure includes dummy dielectric layer 71, dummy gate 76, and mask 78.) on the first fin structure and the second fin structure; (See Fig. 5A.)
removing a portion of the dummy gate structure and a portion of the protective layer to form a T-shaped trench; (Fig. 13B, dummy gate 76 and mask 78 and hard mask 84 are removed and recess 101 is formed which is a T-shaped trench.)
forming a first dielectric structure in the T-shaped trench; and (Fig. 14B, first isolation walls 104 are formed with in the T-shaped trench.)
replacing the dummy gate structure with a gate structure. (Fig. 15A-21B removes the dummy gate structure and replaces with gate stack which includes gate dielectric layer 106 and gate electrodes 108.)
Regarding Claim 27, Chiang discloses:
forming a liner layer (Fig. 14B, liner layer 102) in the T-shaped trench (recess 101) before forming the first dielectric structure. (first isolation wall 104) ([0070], liner 102 is formed before deposited before the first isolation wall 104.)
Regarding Claim 28, Chiang discloses:
removing a portion of the liner layer before forming the gate structure. (See Fig. 16B, linear 102 is removed before the gate stack, [0016] gate stack includes gate dielectric layer 106 and gate electrode 108, in Figs. 20B and 21B.)
Regarding Claim 29, Chiang discloses:
wherein the gate structure comprises a first portion and a second portion, and the first portion is separated from the second portion by the first dielectric structure. (See annotated Fig. 21B below, 108_p1 and 108_p2 are separated by first isolation wall 104.)
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Regarding Claim 30, Chiang discloses:
forming a gate contact structure on the gate structure, wherein the gate contact structure is through the protective layer. (Fig. 26B, gate contact 114 is formed through hard mask 84)
Regarding Claim 31, Chiang discloses:
A method for forming a semiconductor structure, (Figs. 2-26D include the method of semiconductor device.) comprising:
forming a first fin structure, (Fig. 3, first fin structure F1.) a second fin structure (Second fin structure F2) and a third fin structure (Third fin structure F3.) on a substrate, (Substrate 50.) wherein the first fin structure, the second fin structure and the third fin structure, respectively, comprise first semiconductor material layers (Fig. 3 and [0027] and [0055], the first fin structure F1, second fin structure F2, and third fin structure F3 comprise second nanostructure 54 and third semiconductor layer 57A and 57B which can be made of silicon.) and second semiconductor material layers alternately stacked; (Fig. 3 and [0027] and [0055], the first fin structure F1, second fin structure F2, and third fin structure F3 comprise first nanostructure 52 and fourth nanostructure 56 made of silicon-germanium.)
forming a dummy gate structure over the first fin structure, the second fin structure and the third fin structure; (Fig. 5A, dummy gate structure includes dummy dielectric layer 71, dummy gate 76, and mask 78.)
removing a portion of the dummy gate structure to form a first dielectric structure between the second fin structure and the third fin structure; (Fig. 9C, dummy gate 76 is removed between the second fin structure F2 and third fin structure F3.)
removing another portion of the dummy gate structure to form a trench; (Fig. 9C, first recesses 86.)
removing the second semiconductor material layers to form a plurality of nanostructures; (Fig. 21B, first nanostructure 52 are removed from the fin structures.)
forming a gate structure in the trench, wherein the nanostructures are surrounded by the gate structure; and (Fig. 21B, gate electrodes 108 is formed in the recesses 105.)
removing a portion of the gate structure to form a second dielectric structure, wherein the second dielectric structure is between the first fin structure and the second fin structure. (Fig. 26B, isolation walls 110 which is between the first fin structure F1 and second fin structure F2.)
Regarding claim 32, Chiang further discloses:
forming a conductive layer on a portion of the gate structure. (Fig. 26B, gate contact 114.)
Regarding Claim 33, Chiang further discloses:
forming an isolation structure over the substrate, (Fig. 4B, isolation regions 68 over substrate 50.) wherein the first dielectric structure (Fig. 14B, first isolation wall 104.) and the second dielectric structure (Fig. 25B, isolation walls 110) are on the isolation structure. (See Fig. 25B.)
Regarding Claim 34, Chiang further discloses:
forming a liner layer (Fig. 14B, liner layer 102) before forming the first dielectric structure (first isolation wall 104); and ([0070], liner 102 is formed before deposited before the first isolation wall 104.)
removing a portion of the liner layer before forming the gate structure. (See Fig. 16B, linear 102 is removed before the gate stack, [0016] gate stack includes gate dielectric layer 106 and gate electrode 108, in Figs. 20B and 21B.)
Regarding Claim 35, Chiang further discloses:
removing a topmost first semiconductor layer and a topmost second semiconductor layer to form a recess; and (Fig. 7B, recess 87 is formed by removing layer fifth semiconductor layer 57B and fourth semiconductor layer 56.)
forming a protective layer in the recess; and (Fig. 8B, hard mask 84 is deposited in recess 87.)
removing a portion of the protective layer before forming the first dielectric structure. (Fig. 13B, second recesses 101 is formed and etches a portion of the hard mask 84. Then Fig. 14B, shows that the first isolation wall 104 is formed in recesses 101.)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
You et al. US 12107006 B2 – Fig. 2A- 2W show the method of making a semiconductor structure with GAA where the isolation structure has a T-shaped isolation structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812