DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As of March 30, 2026, no information disclosure statement has been made of record.
Drawing Objections
Examiner withdraws the drawing objection based upon Applicant’s replacement sheet and amendment to claim 31.
Specification Objections
Examiner withdraws the specification objections based upon Applicant’s amendments to the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16, 20-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hodo et al. (US 2017/0125450 A1) (“Hodo”), in view of Ishii et al. (US 7,385,224 B2) (“Ishii”), in view of Morosawa et al. (US 2011/0180802 A1) (“Morosawa”).
Regarding claim 16, Hodo teaches at least in figures 18:
forming a gate electrode (62a-b) in a first dielectric layer (67) over a substrate (50);
forming a gate dielectric layer (at least one of 63-65) over the gate electrode (62a-b) and the first dielectric layer (67);
forming a semiconducting material layer (66a-c) over the gate dielectric layer (at least one of 63-65),
wherein the semiconducting material layer (66a-c) comprises a first metal-oxide material (¶ 0230, where 66b can be formed of at least one of In, Ga, or Zn and O);
forming contact terminals (31a-b over 66a-c) within the contact openings (area occupied by 31a-b).
Hodo does not teach:
forming a blocking dielectric layer over the semiconducting material layer;
forming a second dielectric layer over the blocking dielectric layer;
performing a hybrid etching process etching through the second dielectric layer and the blocking dielectric layer to expose a top surface of the semiconducting material layer without recessing the semiconducting material layer and to form contact openings; and
wherein the contact terminals are in direct contact with the exposed top surface of the semiconducting material layer.
Ishii teaches at least in figures 1B, 6B, and 7B:
forming a blocking dielectric layer (9) over the semiconducting material layer (8);
forming a second dielectric layer (12) over the blocking dielectric layer (9);
performing a hybrid etching process (the process is defined below)
etching through the second dielectric layer and the blocking dielectric layer to expose a top surface of the semiconducting material layer without recessing the semiconducting material layer and to form contact openings (figure 6B shows that layers 9 and 12 are etched to form opening); and
wherein the contact terminals (23-24) are in direct contact with the exposed top surface of the semiconducting material layer (8).
It would have been obvious to one of ordinary skill in the art to remove 68a from Hodo and use the process of Ishii instead as the contact terminals of 23-24 as the layer 68a of Hodo (Hodo ¶ 0269) can be formed of the same material as Ishii 23 (Ishii col. 7-8 at lines 65-2). Thus, Ishii can be considered to form an integral contact from Hodo’s separable contact as both contacts use the same material to perform the same function. MPEP 2144.04(V)(B).
Ishii and Hodo do not teach:
Wherein the blocking dielectric layer comprises a second metal-oxide material different from the first metal-oxide material.
This is because Hodo teaches:
The blocking dielectric layer comprises SiN.
Morosawa teaches:
That one of ordinary skill in the art would want to use a second metal-oxide material as the blocking dielectric layer such as oxide, nitride, or oxynitride containing one or more of aluminum (Al), titanium (Ti), and tantalum (Ta) in order to prevent a reduction of oxygen due to hydrogen as a contaminate from interfering with the oxide semiconductor, thus it serves as a better protection, or blocking, dielectric layer for oxide semiconductor devices. ¶ 0102-104.
Regarding claim 20, Ishii teaches at least in figures 1B, 6B, and 7B:
wherein the blocking dielectric layer (9) is formed directly on the semiconducting material layer (8) by an in-situ deposition process (in-situ means in the original place. The blocking dielectric layer 9 is formed in the original place where it is formed. Therefore, 9 is formed in-situ and directly on the semiconducting material layer. The claim does not state that both the blocking dielectric layer and the semiconducting layer are formed in the same machine).
Regarding claim 21, Ishii teaches at least in figures 1B, 6B, and 7B:
wherein the blocking dielectric layer (9) is formed of a material of a density higher than that of a material of the semiconducting material layer (Ishii 8; Hodo 66a-c).
This is obvious as the blocking dielectric layer and the semiconducting material layer can be formed of the same material disclosed by Applicant. Therefore, it would have been obvious that the blocking dielectric layer would have a higher density than the semiconducting material as this is a characteristic of the material.
Regarding claim 22, Ishii teaches at least in figures 1B, 6B, and 7B:
forming a capping dielectric layer over the second dielectric layer; and forming a third dielectric layer over the capping dielectric layer, before performing the hybrid etching process.
The above limitation is directed to Applicant’s figure 8-13. The capping dielectric layer and third dielectric layer are considered a duplication of the blocking dielectric layer and second dielectric layer. What Applicant is doing is stacking more dielectric layers. This is considered a duplication of parts under MPEP 2144.04(VI)(B). As such, the limitations here would have been obvious to one of ordinary skill in the art.
Regarding claim 23, Ishii teaches at least in figures 1B, 6B, and 7B:
performing a second dry etching process to etch through the third dielectric layer to expose the capping dielectric layer; and performing a second wet etching process to remove the exposed capping dielectric layer, after forming the capping dielectric layer and the third dielectric layer and before performing the hybrid etching process.
The above limitation is an obvious duplication of process. Similar to claim 22 above, where Applicant has duplicated the parts. It would have been obvious to one of ordinary skill in the art that if they duplicated the parts they could also, based upon the opinion, duplicated the process. This is because it appears that the critical aspect to the invention is to make sure that one does not dry etch all the way down to the semiconductor layer (see claim 17). Adding more layers and/or more etch steps appear to be an obvious duplication of layers and process, as neither adding more layers or more etch steps is critical to the disclosed invention. Thus, this limitation like the limitations in claim 22 would have been obvious to one of ordinary skill in the art.
Regarding claim 24-25,
Claim 24-25 are directed to the material of the capping dielectric layer and the blocking dielectric layer, and whether they are the same or different. The choice of what material to use a dielectric layer, whether it be labeled as capping or blocking, or insulating, etc., is a routine decision one of ordinary skill in the art makes when designing and creating a device. The is a routine decision to those of ordinary skill in the art and does not provide a patentable distinction from the prior art as it is a routine decision made by those of ordinary skill in the art. As such the choice of material for the capping dielectric layer and blocking dielectric layer would have been obvious.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hodo, in view of Ishii, in view of Morosawa, in view of Kang et al. (US 2005/0260804 A1) (“Kang”).
Regarding claim 17, Hodo does not teach
wherein performing the hybrid etching process comprising:
performing a dry etching process to remove and etch through the second dielectric layer; and
performing a wet etching process to etch through the blocking dielectric layer without damaging the semiconducting material layer.
Kang teaches at least in figure 3A-3D:
wherein performing the hybrid etching process comprising (detailed below):
performing a dry etching process to remove and etch through the second dielectric layer (figure 3C; ¶ 0046); and
performing a wet etching process to etch through the blocking dielectric layer without damaging the semiconducting material layer (figure 3D; ¶ 0049).
It would have been obvious to one of ordinary skill in the art to use the two step etching process of Kang versus the one step etching process of the prior art as Kang teaches that using a single dry etch process may require additional steps to remove a polymer layer created by etching the dielectric layer. In addition, the single step dry etch process may create a non-uniform layer which can create a non-uniform contact resistance to the active region. ¶¶ 0009, and 53.
Regarding claim 18, Kang teaches at least in figure 3A-3D:
wherein the dry etching process is performed to etch through the second dielectric layer (106) and over-etch upper portions of the blocking dielectric layer (104).
Regarding claim 19, Kang does not explicitly teach:
wherein the wet etching process has an etching selectivity larger than 5 toward the blocking dielectric layer to the semiconducting material layer.
However, it would have been obvious to one of ordinary skill in the art to choose a wet etchant with the required selectivity. This is because as shown in Kang one wants to etch the polymer created by dry etching and the remaining dielectric 104 without etching the semiconductor layer 103. Therefore, one of ordinary skill in the art would use routine skill in the art and select a wet etchant with the required selectivity.
Claim(s) 26-27, 29-33, and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hodo, in view of Ishii, in view of Kim et al. (US 2013/0280859 A1) (“Kim”).
Regarding claim 26,
Claim 26 is a combination of claim 16 and claim 20, but is narrower than claim 20 as it requires the forming the gate dielectric, the semiconducting layer, and the second dielectric layer in the same chamber.
Hodo and Ishii teach all the limitations of claim 26 except for the requirement of the same chamber.
Kim teaches:
That when forming oxide semiconductor, IGZO, transistors one would want to form the oxide semiconductor and the dielectric films in the same chamber. ¶ 0072, where “it is possible to perform deposition of the gate dielectric, deposition of the active layer, and deposition and annealing of the passivation layer in-situ while maintaining the process apparatus in a vacuum state”. ¶ 0006, where TFTs can be, and have been, manufactured in the same chamber. Therefor,e it is obvious for one to keep the device under vacuum while performing this processing. This would have been obvious to one of ordinary skill in the art because by performing all these steps in the same machine under a single vacuum it would decrease processing time of the layers. This is because one would not need to wait for the time it takes to pull a vacuum for each layer before processing it. One could pull a single vacuum, thereby increasing throughput of the device.
Regarding claim 27,
Claim 27 is rejected for the same reasons as claim 21 above.
Regarding claim 29,
Claim 29 is rejected for the same reasons as claim 22 above.
Regarding claim 30,
Claim 30 is rejected for the same reasons as claim 23 above.
Regarding claim 31,
Claim 31 appears to be claim 26 with the additional limitation:
Forming a first dielectric layer over a contact line;
Forming a gate electrode in the first dielectric layer and in contact with the contact line.
Hodo teaches at least in figure 18:
Forming a first dielectric layer (67) over a contact line (¶ 0249, where the gate 62a-b may be connected to wiring);
Forming a gate electrode (62a-b) in the first dielectric layer (67) and in contact with the contact line (¶ 0249).
Based upon this claim 31 is rejected for the reasons given directly above and the reasons given in claim 26.
Regarding claim 32,
Claim 32 is rejected for the same reasons as claim 21 above.
Regarding claim 33,
Based upon Applicant’s ¶ 0033, the limitation of claim 33 happens because the semiconductor layer and the blocking dielectric layer are formed in-situ in the same chamber under a single vacuum. This is taught by Kim in claim 26 above. Therefore, claim 33 is obvious for the reasons given in claim 33.
Regarding claim 35,
Claim 35 is rejected for the same reasons as claim 22 above.
Claim(s) 28, and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hodo, in view of Ishii, in view of Kim, in view of Kang.
Regarding claim 28,
Claim 28 is rejected for the same reasons as claim 17 above.
Regarding claim 34,
Claim 34 is rejected for the same reasons as claim 17 above.
Response to Arguments
Regarding claim 16,
Applicant’s arguments, March 17, 2026, with respect to the rejection(s) of claim(s) 16 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in light of the new reference Morosawa.
Regarding claims 26, and 31,
Applicant's arguments filed March 17, 2026, have been fully considered but they are not persuasive.
Applicant asserts Kim does not teach the steps are performed in the same chamber. Examiner has cited to a difference portion of the Kim reference to elaborate upon that which has been cited previously. In this case Examiner is also citing to ¶ 0006 which states that it is known in the art to perform all the steps in the same chamber. This is not considered new grounds of rejection as stated in MPEP 2107.03(a)(II)(1), where Citing a different portion of a reference to elaborate upon that which has been cited previously is not considered new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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