DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed November 4, 2025. Claims 1, 11 and 21 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-17, and 21-23 are pending.
Applicant’s Amendments to the drawings overcome the drawing objections outlined in the previous Office Action. The drawing objections have been withdrawn.
Applicant’s Amendment to the specification overcome the specification objection outlined in the previous Office Action. The specification objection has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 9-10, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Fujita (US 20200344433 A1) in view of Chien et al. (US 20150189207 A1) herein after “Chien”.
Regarding claim 1, Figs. 13-17 of Fujita disclose a method for manufacturing an image sensor structure (Figs. 13-17, method of manufacturing an image sensor, ¶ [0093]), comprising:
forming an isolation structure (Fig. 14, isolation dopant layer 101, ¶ [0067]) in a substrate (Fig. 14, semiconductor substrate 100, ¶ [0048]) to divide the substrate (100) into a first region (Fig. 9, pixel regions PR, ¶ [0049]) and a second region (PR) (“The isolation dopant layer 101 may be formed by ion-implanting dopants”, ¶ [0098]);
forming a first light sensing region (Fig. 14, first region 110a, ¶ [0063]) in the first region (PR) and a second light sensing region (110a) in the second region (PR) (“The second dopant layers 110a may be formed by ion-implanting dopants”, ¶ [0099]);
forming a first gate structure (Fig. 15, gate electrodes 130a, ¶ [0052]) over the first light sensing region (110a) and a second gate structure (130a) over the second light sensing region (110a), wherein the first gate structure (130a) and the second gate structure (130a) are positioned at a frontside surface (100a) of the substrate (100) (“the formation of the transfer gate electrodes 130a to 130d may include patterning the first surface 100a of the semiconductor substrate 100”, ¶ [0103]);
forming gate spacers (spacers shown in Fig. 15, SPC) on sidewalls of the first and second gate structures (130a);
depositing a blocking layer (Fig. 16, lower interlayer insulating layer 150, ¶ [0071]) on sidewalls of the gate spacers (SPC) (“interlayer insulating layers 150 may be formed on the first surface 100a of the semiconductor substrate 100”, ¶ [0106]), the blocking layer (150) having an opening (hole for contact plug 141) positioned between the first and second gate structures (130a);
forming a source/drain structure (Fig. 16, floating diffusion region 120, ¶ [0051]) directly under the opening (hole for contact plug 141) in the blocking layer (150);
and forming an interlayer dielectric layer (Fig. 16, upper interlayer insulating layer 150, ¶ [0071]) over the first and second gate structures (130a) and the blocking layer (150).
Fujita fails to disclose after the depositing of the blocking layer, forming a source/drain structure directly under the opening in the blocking layer.
In the similar field of endeavor of image sensor devices, Figs. 7A-7C of Chien disclose after the depositing of the blocking layer (Fig. 7B, photoresist 713, ¶ [0042]), forming a source/drain structure (Fig. 7B, sources/drains 705, ¶ [0042]) directly under the opening (Fig. 7B, openings 715, ¶ [0042]) in the blocking layer (713).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include forming the source/drain structure after the blocking layer as disclosed by Chien, to achieve a desired dopant profile (see Chien, ¶ [0044]) and/or because selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (MPEP 2144.04IV.C).
Regarding claim 3, Fujita and Chien together disclose the method of claim 1 as applied above, and Fig. 16 of Fujita further discloses wherein the opening (hole for contact plug 141) is directly above the isolation structure (101).
Regarding claim 4, Fujita and Chien together disclose the method of claim 1 as applied above, and Figs. 14 and 16 of Fujita further disclose wherein the forming of the isolation structure (101) includes implanting a first type dopant into a top portion of the substrate (100) (“The isolation dopant layer 101 may be formed by ion-implanting dopants of the first conductivity type”, ¶ [0098]), the forming of the source/drain structure (120) includes implanting a second type dopant into a top portion of the isolation structure (101) (“The floating diffusion region 120 may be formed by ion-implanting dopants of the second conductivity type”, ¶ [0104]), and the first type dopant and the second type dopant have opposite conductivities (“a second conductivity type that is different than the first conductivity type”, ¶ [0007]).
Regarding claim 5, Figs. 14 and 16 of Fujita disclose the method of claim 4 as applied above, and Fujita further discloses wherein the first type dopant is a p-type dopant (“The isolation dopant layer 101 may be formed by ion-implanting dopants of the first conductivity type (e.g., the P-type)”, ¶ [0098]), and the second type dopant is an n-type dopant (“The floating diffusion region 120 may be formed by ion-implanting dopants of a second conductivity type (e.g., an N-type)”, ¶ [0051]).
Regarding claim 9, Fujita and Chien together disclose the method of claim 1 as applied above, and Fujita further discloses wherein the forming of the first and second gate structures (130a) includes:
etching the frontside surface (100a) of the substrate (100) to form a first recess and a second recess (120), wherein the first recess exposes the first light sensing region (110a), and the second recess exposes the second light sensing region (110a) (“the formation of the transfer gate electrodes 130a to 130d may include patterning the first surface 100a of the semiconductor substrate 100 to form gate recess regions”, ¶ [0103]);
depositing a gate dielectric layer and a gate electrode layer in the first recess and the second recess (“forming a gate insulating layer conformally covering inner surfaces of the gate recess regions, forming a gate conductive layer filling the gate recess regions”, ¶ [0103]); and
patterning the gate dielectric layer and the gate electrode layer to form the first and second gate structures (130a) (“and patterning the gate conductive layer”, ¶ [0103]).
Regarding claim 10, Fujita and Chien together disclose the method of claim 1 as applied above, and Fig. 16 of Fujita further discloses wherein a bottom surface of the source/drain structure (120) is above bottom surfaces of the first and second gate structures (130a) (shown in Fig. 16).
Regarding claim 21, Figs. 13-17 of Fujita disclose a method for manufacturing an image sensor structure (Figs. 13-17, method of manufacturing an image sensor, ¶ [0093]), comprising:
forming an isolation structure (101) in a substrate (100), the isolation structure (101) dividing a top portion of the substrate (100) into a grid of cells (110a);
forming a first light sensing region (110a) in a first one of the cells (110a) and a second light sensing region (110a) in a second one of the cells (110a) adjacent to the first one of the cells (110a);
forming a first gate structure (130a) above the first light sensing region (110a) and a second gate structure (130a) above the second light sensing region (110a);
depositing gate spacers (SPC) on sidewalls of the first and second gate structures (130a);
depositing a blocking layer (150) on sidewalls of the gate spacers (SPC), the blocking layer (150) has a first opening (hole for contact plug 141) exposing a first portion of the isolation structure (101), the first portion of the isolation structure (101) shared by the first one and the second one of the cells (110a); and
forming a source/drain structure (120) overlapping with the first portion of the isolation structure (101) when viewed from top.
Fujita fails to disclose after the depositing of the blocking layer, forming a source/drain structure.
In the similar field of endeavor of image sensor devices, Figs. 7A-7C of Chien disclose after the depositing of the blocking layer (713), forming a source/drain structure (705).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include forming the source/drain structure after the blocking layer as disclosed by Chien, to achieve a desired dopant profile (see Chien, ¶ [0044]) and/or because selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (MPEP 2144.04IV.C).
Regarding claim 23, Fujita and Chien disclose the method of claim 21 as
applied above, and Fig. 17 of Fujita further discloses comprising:
forming a backside isolation feature (Fig. 17, pixel isolation layer 105, ¶ [0049])
extending through the isolation structure (101).
Claims 2, 7-8, and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fujita (US 20200344433 A1) and Chien (US 20150189207 A1) in further view of Lee et al. (US 20220271077 A1) herein after “Lee”.
Regarding claim 2, Fujita and Chien together disclose the method of claim 1 as applied above, but Fujita and Chien fail to disclose forming a contact trench through the interlayer dielectric layer, such that a portion of the source/drain structure is exposed by the contact trench; and
forming a contact in the contact trench.
In the similar field of endeavor of image sensors, Figs. 25-26 of Lee disclose forming a contact trench (Fig. 25, second contact hole CA2H, ¶ [0049]) through the interlayer dielectric layer (Fig. 25, fifth mask pattern M22, ¶ [0118]), such that a portion of the source/drain structure (Fig. 25, floating diffusion region FD, ¶ [0109]) is exposed by the contact trench (CA2H); and
forming a contact (Fig. 26, active contact CA2, ¶ [0049]) in the contact trench (CA2H).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include the contact trench and contact as disclosed by Lee, to allow contact for subsequent wiring layers (see Lee, ¶ [0054]).
Regarding claim 7, Fujita and Chien together disclose the method of claim 1 as applied above, and Figs. 8 and 16 of Fujita further disclose wherein the blocking layer (150) is a first blocking layer (150) and the opening (hole for contact plug 141) is a first opening (hole for contact plug 141), the method further comprising:
forming a strapping well (Fig. 8, well dopant layer 115, ¶ [0057]) (“The well dopant layer 115 may be formed by ion-implanting dopants of the first conductivity type”, ¶ [0096]).
Fujita fails to disclose depositing a second blocking layer, wherein the first gate structure is positioned between the first and second blocking layers, and the second blocking layer has a second opening; and
the strapping well directly under the second opening in the second blocking layer.
In the similar field of endeavor of image sensors, Fig. 23 of Lee discloses depositing a second blocking layer (central portion of 162), wherein the first gate structure (140) is positioned between the first (outer portion of 162) and second blocking layers (central portion of 162), and the second blocking layer (central portion of 162) has a second opening (Fig. 23, first contact hole CA1H, ¶ [0047]); and
forming a strapping well (Fig. 23, ground region GND, ¶ [0048]) directly under the second opening (CA1H) in the second blocking layer (central portion of 162).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include the forming the strapping well under the second opening as disclosed by Lee, to simplify production (see Lee, ¶ [0063]).
Regarding claim 8, Fujita, Chien, and Lee together disclose the method of claim 7 as applied above, and Fujita further discloses wherein the strapping well (115) and the source/drain structure (120) include dopants of opposite conductivities (“The floating diffusion region 120 may be formed by ion-implanting dopants of a second conductivity type “, “The well dopant layer 115 may be formed by ion-implanting dopants of the first conductivity type”, ¶ [0051] and [0096]).
Regarding claim 11, Figs. 13-17 of Fujita disclose a method for manufacturing an image sensor structure (Figs. 13-17, method of manufacturing an image sensor, ¶ [0093]), comprising:
forming an isolation structure (101) in a substrate (100) to define an enclosure;
forming a light sensing region (110a) in the enclosure;
forming a gate structure (130a) above the light sensing region (110a);
depositing a first gate spacer (SPC) on a first sidewall of the gate structure (130a);
depositing a second gate spacer (SPC) on a second sidewall of the gate structure (130a), the second sidewall being opposing the first sidewall;
depositing a first blocking layer (150) on the first gate spacer (SPC), the first blocking layer (150) including a first opening (hole for contact plug 141);
implanting a first dopant into the substrate (100) to form a first doped region (120) (“The floating diffusion region 120 may be formed by ion-implanting dopants of a second conductivity type (e.g., an N-type) into the semiconductor substrate 100”, ¶ [0051]); and
implanting a second dopant into the substrate (100) to form a second doped region (115) (“The well dopant layer 115 may be formed by ion-implanting dopants of the first conductivity type”, ¶ [0096]), the first and second dopants including opposite conductivities (“a second conductivity type that is different than the first conductivity type”, ¶ [0007]).
Fujita fails to disclose depositing a second blocking layer on the second gate spacer, the second blocking layer including a second opening; and
after the depositing of the first blocking layer, implanting a first dopant into the substrate through the first opening to form a first doped region; and
after the depositing of the second blocking layer, implanting a second dopant into the substrate through the second opening to form a second doped region.
In the similar field of endeavor of image sensors, Fig. 23 of Lee discloses depositing a second blocking layer (central portion of 162) on the second gate spacer (140S), the second blocking layer (central portion of 162) including a second opening (CA1H).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include the blocking layer as disclosed by Lee, to simplify production (see Lee, ¶ [0063]).
Lee fails to disclose after the depositing of the first blocking layer, implanting a first dopant into the substrate through the first opening to form a first doped region; and
after the depositing of the second blocking layer, implanting a second dopant into the substrate through the second opening to form a second doped region.
In the similar field of endeavor of image sensor devices, Figs. 7A-7C of Chien disclose after the depositing of the first blocking layer (Fig. 7A, protective layer 402, ¶ [0036]), implanting a first dopant (Fig. 7A, the implantation 701, ¶ [0041]) into the substrate through the first opening (Fig. 7A, gap in 402 in region 406) to form a first doped region (Fig. 7A, source and drain 703, ¶ [0041]); and
after the depositing of the second blocking layer (713), implanting a second dopant (Fig. 7B, the implantation 711, ¶ [0042]) into the substrate through the second opening (715) to form a second doped region (705).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include forming the source/drain structure after the blocking layer as disclosed by Chien, to achieve a desired dopant profile (see Chien, ¶ [0044]) and/or because selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (MPEP 2144.04IV.C).
Regarding claim 12, Fujita, Chien, and Lee together disclose the method of claim 11 as applied above, but Fujita and Chien fail to disclose comprising:
depositing a dielectric layer covering the first and second blocking layers, the first and second gate spacers, and the first and second gate structures;
forming a first contact through the dielectric layer and in physical contact with the first doped region; and
forming a second contact through the dielectric layer and in physical contact with the second doped region.
In the similar field of endeavor of image sensors, Figs. 25-26 of Lee disclose comprising:
depositing a dielectric layer (M22) covering the first (outer portion of 162) and second blocking layers (central portion of 162), the first and second gate spacers (140S), and the first and second gate structures (140);
forming a first contact (CA2) through the dielectric layer (M22) and in physical contact with the first doped region (FD); and
forming a second contact (CA1) through the dielectric layer (M22) and in physical contact with the second doped region (GND).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include the contacts as disclosed by Lee, to allow contact for subsequent wiring layers (see Lee, ¶ [0054]).
Regarding claim 13, Fujita, Chien, and Lee together disclose the method of claim 11 as applied above, but Fujita and Chien fail to disclose wherein the first contact is in physical contact with sidewalls of the first opening, and the second contact is in physical contact with sidewalls of the second opening.
In the similar field of endeavor of image sensors, Figs. 25-26 of Lee disclose wherein the first contact (CA2) is in physical contact with sidewalls of the first opening (CA2H), and the second contact (CA1) is in physical contact with sidewalls of the second opening (CA1H).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include the contacts as disclosed by Lee, to allow contact for subsequent wiring layers (see Lee, ¶ [0054]).
Regarding claim 14, Fujita, Chien, and Lee together disclose the method of claim 11 as applied above, and Fujita further discloses wherein the first dopant is a p-type dopant, and the second dopant is an n-type dopant (“a well dopant layer 115 having the first conductivity type”, “the first conductivity type (e.g., the P-type)”, ¶ [0057] and [0098]), and the second type dopant is an n-type dopant (“The floating diffusion region 120 may be formed by ion-implanting dopants of a second conductivity type (e.g., an N-type)”, ¶ [0051]).
Regarding claim 15, Fujita, Chien, and Lee together disclose the method of claim 11 as applied above, and Fig. 4 of Fujita further discloses wherein a size of the first doped region (120) is smaller than a size of the second doped region (115) in a top view of the image sensor structure.
Regarding claim 16, Fujita, Chien, and Lee together disclose the method of claim 11 as applied above, the combination fails to explicitly disclose wherein each of the first and second blocking layers has a square shape or a rectangular shape in a top view of the image sensor structure.
However, it would be obvious to one of ordinary skill in the art to arrive at the claimed structure through optimization of the blocking layers within the prior art and/or because it has been ruled that changes of shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)(B)).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Fujita (US 20200344433 A1) and Chien (US 20150189207 A1) in further view of Ha et al. (US 20210143191 A1) herein after “Ha”.
Regarding claim 6, Fujita and Chien together disclose the method of claim 1 as applied above, but Fujita and Chien fail to disclose wherein the gate spacers and the blocking layer include different material compositions.
In the similar field of endeavor of image sensors, Fig. 2E of Ha discloses the gate spacers (Fig. 2E, gate spacer 520, ¶ [0060]) and the blocking layer (Fig. 2E, first dielectric layer 410, ¶ [0061]) include different material compositions (“The gate spacer 520 may include… silicon carbonitride”, “The first, second, and third dielectric layers 410, 420, and 430 may include… silicon oxide”, ¶ [0060-0061]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Fujita to include the materials as disclosed by Ha, to isolate components in the wiring layer (see Lee, ¶ [0060-0061]) and/or because it has been ruled that changes of shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)(B)).
Allowable Subject Matter
Claims 17 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, the prior art of record alone or in combination fails to disclose or fairly suggest “wherein each of the first and second openings is directly above the isolation structure” in combination with the other limitations of claim 17.
Regarding claim 22, the prior art of record alone or in combination fails to disclose or fairly suggest “wherein the blocking layer has a second opening exposing a second portion of the isolation structure that is spaced apart from the second one of the cells, the method further comprising:
forming a strapping well overlapping with the second portion of the isolation structure when viewed from top, wherein the source/drain structure and the strapping well include opposite conductivity types” in combination with the other limitations of claim 22.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights