DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 12/28/2025.
Claims 1-15 and 21-25 are pending. Claims 16-20 are cancelled. Claims 21-25 are new. Claims 1, 13 and 21 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/9/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 12/28/2025 is acknowledged.
Claims 16-20, which have been canceled, were drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/28/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the unit via assembly” in line 4 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note, claim 1 previously introduces “a unit via assembly structure” (emphasis added) in line 2 of the claim, which is not identical to the limitation “the unit via assembly” and thus does not provide sufficient antecedent basis.
Claim 1 recites “a respective unit area” in line 8 of the claim, however “a respective unit area” element was already introduced earlier in lines 6-7 of the claim, and thereby it is unclear whether the “a respective unit area” in line 8 of the claim is directed to that same element and therefore should be properly amended to “the respective unit area” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element.
Claim 1 recites the limitation “the rectangular areas” (plural form) in line 11 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note, claim 1 previously introduces “a respective rectangular area” (singular form) in line 9 of the claim, which does not provide sufficient antecedent basis for limitation “the rectangular areas” (plural form).
Claim 12 recites the limitation “the LSI bridges” (plural form) in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note, claim 1, which claim 12 depends from, previously introduces “at least one local silicon interconnect (LSI) bridge” (singular form) in line 15 of the claim, which does not provide sufficient antecedent basis for limitation “the LSI bridges” (plural form).
Claim 13 recites “a respective unit area” in line 5 of the claim, however “a respective unit area” element was already introduced earlier in line 4 of the claim, and thereby it is unclear whether the “a respective unit area” in line 5 of the claim is directed to that same element and therefore should be properly amended to “the respective unit area” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element.
Claim 13 recites the limitation “the unit areas of repetition” in line 9 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation “the LSI bridges” (plural form) in line 14 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note, claim 13 previously introduces “at least one local silicon interconnect (LSI) bridge” (singular form) in line 11 of the claim, which does not provide sufficient antecedent basis for limitation “the LSI bridges” (plural form).
Claim 14 recites the limitation “the semiconductor dies” (plural form) in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note, claim 13, which claim 14 depends from, previously introduces “at least one semiconductor die” (singular form) in line 5 of the claim, which does not provide sufficient antecedent basis for limitation “the semiconductor dies” (plural form).
Claim 14 recites the limitation “the first carrier” in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note the dependent claims 2-12 and 14-15 necessarily inherit the indefiniteness of the claims on which they depend.
Allowable Subject Matter
Claims 21-25 are allowed.
Regarding independent claim 21, Lee (US 2014/0048948 A1) discloses a method of forming a semiconductor structure, the method comprising:
forming through interposer via (TIV) structures TSV(M) (“main TSV region”- ¶0023) and alignment via structures TSV(A) (“sub-TSV regions”- ¶0024) over a carrier wafer (i.e., “semiconductor memory device”- ¶0023), wherein the alignment via structures TSV(A) are arranged in a non-periodic pattern within each of two alignment mark via assemblies located in two corner regions of a unit area and diagonally spaced apart from each other (see Figs. 3-4).
Lee does not expressly disclose identifying corner locations of the unit area using the non-periodic pattern of the alignment via structures within the two alignment mark via assemblies and placing at least one local silicon interconnect (LSI) bridge within the unit area using a pick and place tool.
Thus, regarding independent claim 21, the claim is allowed, because the prior art of record including Lee, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “identifying corner locations of the unit area using the non-periodic pattern of the alignment via structures within the two alignment mark via assemblies” and “placing at least one local silicon interconnect (LSI) bridge within the unit area using a pick and place tool”.
Claims 22-25 are allowed as being dependent on allowed claim 21.
Claims 1-15 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding independent claim 1, Lee discloses a method of forming a semiconductor structure, the method comprising:
forming via structures over a first carrier wafer (i.e., “semiconductor memory device”- ¶0023) to form an instance of the unit via assembly which comprises through interposer via (TIV) structures TSV(M) (“main TSV region”- ¶0023) and two alignment mark via assemblies TSV(A) (“sub-TSV regions”- ¶0024) located in two corner regions of a respective unit area and are diagonally spaced apart from each other, wherein each of the two alignment mark via assemblies TSV(A) in a respective unit area comprises a respective set of alignment via structures (i.e., “TSVs”- ¶0033) located within a respective rectangular area (i.e., a rectangle encompassing TSV(A)) defined by a respective smallest rectangle that includes an entire area of the respective set of alignment via structures (see Figs. 3-4).
Lee does not expressly disclose forming via structures over a first carrier wafer such that a unit via assembly structure is repeated along a first horizontal direction and along a second horizontal direction over the first carrier wafer, wherein each instance of the unit via assembly is formed within a respective unit area of repetition, wherein the rectangular areas are laterally spaced from boundaries between unit areas of repetition at least by a maximum side length of the rectangular areas, identifying corner locations of the unit areas of repetition using the alignment mark via assemblies within the unit areas of repetition and placing at least one local silicon interconnect (LSI) bridge within each unit area of repetition using a pick and place tool.
Thus, regarding independent claim 1(which claims 2-12 depend from), the prior art of record including Lee, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “forming via structures over a first carrier wafer such that a unit via assembly structure is repeated along a first horizontal direction and along a second horizontal direction over the first carrier wafer, wherein each instance of the unit via assembly is formed within a respective unit area of repetition”, “wherein the rectangular areas are laterally spaced from boundaries between unit areas of repetition at least by a maximum side length of the rectangular areas”, “identifying corner locations of the unit areas of repetition using the alignment mark via assemblies within the unit areas of repetition” and “placing at least one local silicon interconnect (LSI) bridge within each unit area of repetition using a pick and place tool”.
Regarding independent claim 13, Lee discloses a method of forming a semiconductor structure, the method comprising:
forming an instance of a unit via assembly which comprises through interposer via (TIV) structures TSV(M) (“main TSV region”- ¶0023) and two alignment mark via assemblies TSV(A) (“sub-TSV regions”- ¶0024) located in two corner regions of a respective unit area and are diagonally spaced apart from each other, wherein each of the two alignment mark via assemblies TSV(A) in a respective unit area comprises a respective set of alignment via structures (i.e., “TSVs”- ¶0033) located within a respective rectangular area (i.e., a rectangle encompassing TSV(A)) which is defined by a respective smallest rectangle that includes an entire area of the respective set of alignment via structures.
Lee does not expressly disclose forming multiple instances of a unit via assembly, identifying corner locations of the unit areas of repetition using the alignment mark via assemblies within the multiple instances of the unit via assembly, placing at least one local silicon interconnect (LSI) bridge within each unit area of repetition using a pick and place tool and forming a molding compound matrix around the multiple instances of the unit via assembly structure and around the LSI bridges.
Thus, regarding independent claim 13 (which claims 14-15 depend from), the prior art of record including Lee, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “forming multiple instances of a unit via assembly”, “identifying corner locations of the unit areas of repetition using the alignment mark via assemblies within the multiple instances of the unit via assembly”, “placing at least one local silicon interconnect (LSI) bridge within each unit area of repetition using a pick and place tool” and “forming a molding compound matrix around the multiple instances of the unit via assembly structure and around the LSI bridges”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Park et al. (US 2011/0233736 A1), which discloses a method of forming a semiconductor structure comprising forming alignment mask assemblies located in two corner regions of a carrier wafer diagonally spaced apart from each other.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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