DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/300,513, Applicant’s response filed on 07/13/2026 to the Election/Restriction requirement submitted on 05/13/2026. In the response, Applicant has amended claims 1-2, cancelled claims 8-20 and presents as new claims 21-33. Claims 1-7 and 21-33 are currently pending in this application.
Election/Restrictions
3. Applicant’s election without traverse of Group/Invention I which includes claims 1-7 in the reply filed on 07/13/2026 is acknowledged.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/14/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Dependent claims 21, 27 and 29 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
7. With respect to dependent claim 21, the claim fails to further limit the subject matter of independent claim 1, from which claim 21 directly depends. While fclaim 21 recites the “actual SRAM cell” and the “pseudo SRAM cell” from claim 1 in the preamble of claim 21, the body of claim 21 fails to further limit the “actual SRAM cell” and the “pseudo SRAM cell” specifically. Moreover, the body of claim 21 recites features such as “interconnect structure” and “a plurality of pins”, with no recited direct physical/functional relationship to the “actual SRAM cell” and the “pseudo SRAM cell”. Thus, the subject matter recited in the body of claim 21 is found indefinite for lacking required physical/functional relationship(s). Claims 27 and 29 follow similarly.
Double Patenting
8. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
9. Claims 1-5 and 7 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 14-18 and 20 of U.S. Patent No. 11,631,682 (“the 682 patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 14-18 and 20 of the ‘682 patent are nearly identical in scope to claims 1-5 and 7 of the instant application.
10. For purposes of comparison, the following table shows rejected claims of the instant application across from claims of the reference patent, as follows:
Claims of instant application
Claims of the ‘682 patent
1. A semiconductor device, comprising:
an actual SRAM cell, comprising:
a first pair of cross-coupled inverters defining a
first pair of complementary data storage nodes, and a first pair of access transistors
coupled to the first pair of complementary data storage nodes, respectively; and
a pseudo SRAM cell comprising: a
second pair of cross-coupled inverters, and a
second pair of access transistors,
wherein the pseudo SRAM cell and the actual SRAM cell have the same number of transistors laid out in the same layout configuration as one
another, but
wherein a plurality of electrical pathways are absent from the pseudo SRAM cell relative to the actual SRAM cell to provide a plurality of electrical gaps in the pseudo SRAM cell.
14. A semiconductor device, comprising:
an actual SRAM cell, comprising:
a first pair of cross-coupled inverters configured to store data in a first pair of complementary data storage nodes, and a first pair of access transistors configured to allow selective access to the first pair of complementary data storage nodes; and
a pseudo SRAM cell comprising:
a second pair of cross-coupled inverters, and a second pair of access transistors,
wherein the pseudo SRAM cell and the actual SRAM cell have the same number of transistors laid out in the same layout configuration as one another, but
wherein a plurality of electrical pathways are selectively removed in the pseudo SRAM cell relative to the actual SRAM cell to provide a plurality of electrical gaps in the pseudo SRAM cell.
2. A semiconductor device of claim 1, further
comprising
an actual SRAM cell, comprising: a first pair of cross-coupled inverters defining a first pair of complementary data storage nodes, and a first pair of access transistors coupled to the first pair of complementary data storage nodes, respectively;
a pseudo SRAM cell comprising: a second pair of cross-coupled inverters, and a second pair of access transistors, wherein the pseudo SRAM cell and the actual SRAM cell have the same number of transistors laid out in the same layout configuration as one another, but
wherein a plurality of electrical pathways are absent from the pseudo SRAM cell relative to the actual SRAM cell to provide a plurality of electrical gaps in the pseudo SRAM cell; and
test circuitry configured to apply a first voltage bias across a first of the electrical gaps, and measure a first leakage current while the first voltage bias is applied.
15. The semiconductor device of claim 14, further comprising
(see claim 14 of the 682 patent).
(see claim 14 of the 682 patent).
(see claim 14 the 682 patent).
test circuitry configured to apply a first voltage bias across a first of the electrical gaps, and measure a first leakage current while the first voltage bias is applied.
3. (Original) The semiconductor device of claim 2,
wherein the test circuitry is further configured to characterize a process or a design rule by which the pseudo SRAM cell is made based on the first leakage current.
16. The semiconductor device of claim 15,
wherein the test circuitry is further configured to characterize a process or a design rule by which the pseudo SRAM cell is made based on the first leakage current.
4. (Original) The semiconductor device of claim 1,
wherein the plurality of electrical pathways that are absent consists of a plurality of contacts that are absent from the pseudo SRAM cell relative to the actual SRAM cell.
17. The semiconductor device of claim 14,
wherein the plurality of electrical pathways that are selectively removed consists of a plurality of contacts that are selectively removed in the pseudo SRAM cell relative to the actual SRAM cell.
5. (Original) The semiconductor device of claim 1,
wherein the pseudo SRAM cell comprises six transistors each having a first conductivity type, the six transistors including a first access transistor, a second access transistor, a first data
storage transistor, a second data storage transistor, a third data storage transistor, and a
fourth data storage transistor.
18. The semiconductor device of claim 14,
wherein the pseudo SRAM cell comprises six transistors each having a first conductivity type, the six transistors including a first access transistor, a second access transistor, a first data storage transistor, a second data storage transistor, a third data storage transistor, and a fourth data storage transistor.
7. (Currently Amended) A semiconductor device of claim 1, comprising:
an actual SRAM cell, comprising: a first pair of cross-coupled inverters defining a first pair of complementary data storage nodes, and a first pair of access transistors coupled to the first pair of complementary data storage nodes, respectively; and
a pseudo SRAM cell comprising: a second pair of cross-coupled inverters, and a second pair of access transistors,
wherein the pseudo SRAM cell and the actual SRAM cell have the same number of transistors laid out in the same layout configuration as one another, but wherein a plurality of electrical pathways are absent from the pseudo SRAM cell relative to the actual SRAM cell to provide a plurality of electrical gaps in the pseudo
SRAM cell,
wherein a first pin is coupled to a first electrical feature on one side of a first electrical gap of the plurality of electrical gaps and a second pin is coupled to a second electrical feature on an opposite side of the first electrical gap, such that application of a voltage bias between the first pin and the second pin induces a leakage current between the first electrical feature and the second electrical feature.
20. The semiconductor device of claim 14,
(see claim 14 of the 682 patent).
(see claim 14 of the 682 patent).
(see claim 14 of the 682 patent).
wherein a first pin is coupled to a first electrical feature on one side of a first electrical gap of the plurality of electrical gaps and a second pin is coupled to a second electrical feature on an opposite side of the first electrical gap, such that application of a voltage bias between the first pin and the second pin induces a leakage current between the first electrical feature and the second electrical feature.
Allowable Subject Matter
11. Dependent claims 6, 22-26, 28 and 30-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. With respect to claim 6, the prior art made of record fails to teach the combination of steps recited in dependent claim 6, including the following particular combination of steps as recited in claim 6, as follows:
wherein the test circuitry is further configured to apply a second voltage bias across a second of the electrical gaps, and measure a second leakage current while the second voltage bias is applied, wherein a difference between the first voltage bias and the second voltage bias is more than 10
volts.
13. With respect to claim 22, the prior art made of record fails to teach the combination of steps recited in dependent claim 22 including the following particular combination of steps as recited in claim 22, as follows:
wherein the SRAM cell comprises an access transistor whose source region and drain region are each floating.
14. With respect to claim 23, the prior art made of record fails to teach the combination of steps recited in dependent claim 23, including the following particular combination of steps as recited in claim 23, as follows:
wherein the pseudo SRAM cell comprises a pair of cross-coupled inverters establishing first and second complementary data storage nodes, and comprising a pair of access transistors whose source regions and drain regions are each floating.
15. With respect to claim 24, the prior art made of record fails to teach the combination of steps recited in dependent claim 24, including the following particular combination of steps as recited in claim 24, as follows:
wherein the pseudo SRAM cell and the actual SRAM cell have the same number of transistors, the same active area layouts, and the same lower metal layouts as one another, but where contacts are absent in the pseudo SRAM cell relative to the actual SRAM cell.
16. With respect to claims 25-26, the prior art made of record fails to teach the combination of steps recited in dependent claim 25, including the following particular combination of steps as recited in claim 25, as follows:
wherein the pseudo SRAM cell comprises six transistors each having a first conductivity type, the six transistors including a first access transistor, a second access transistor, a first data storage transistor, a second data storage transistor, a third data storage transistor, and a fourth data storage transistor.
17. With respect to claim 28, the prior art made of record fails to teach the combination of steps recited in dependent claim 28, including the following particular combination of steps as recited in claim 28, as follows:
a first well region of a first conductivity type disposed about a first edge and a
second edge of the pseudo SRAM cell; and
a second well region of the first conductivity type disposed about a third edge and a fourth edge of the pseudo SRAM cell, the first well region and the second well region adjoining one another to form an enclosed ring that surrounds the pseudo SRAM cell.
18. With respect to claim 30, the prior art made of record fails to teach the combination of steps recited in dependent claim 30, including the following particular combination of steps as recited in claim 30, as follows:
wherein the pseudo SRAM cell comprises an access transistor whose source region and drain region are each floating.
19. With respect to claim 31, the prior art made of record fails to teach the combination of steps recited in dependent claim 31, including the following particular combination of steps as recited in claim 31, as follows:
wherein the pseudo SRAM cell comprises a pair of cross-coupled inverters establishing first and second complementary data storage nodes, and comprising a pair of access transistors whose source regions and drain regions are each floating.
20. With respect to claim 32, the prior art made of record fails to teach the combination of steps recited in dependent claim 32, including the following particular combination of steps as recited in claim 32, as follows:
wherein the pseudo SRAM cell comprises an access transistor whose source region and drain region are each floating.
21. With respect to claim 33, the prior art made of record fails to teach the combination of steps recited in dependent claim 33, including the following particular combination of steps as recited in claim 33, as follows:
wherein the pseudo SRAM cell comprises a pair of cross-coupled inverters establishing first and second complementary data storage nodes, and comprising a pair of access transistors whose source regions and drain regions are each floating.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
Prosecution Insights