DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application repeats a substantial portion of prior Applications No. 17/233,755, filed on 4/19/2021, No. 16/359,092, filed on 3/20/2019, and No. 62/737/317, filed on 9/27/2018, and adds disclosure not presented in the prior application. Note that the claimed limitation “Pauling’s scale” of the instant application was not presented in the above prior applications.
Because this application names the inventor or at least one joint inventor named in the prior application, it may constitute a continuation-in-part of the prior application. Should applicant desire to claim the benefit of the filing date of the prior application, attention is directed to 35 U.S.C. 120, 37 CFR 1.78, and MPEP § 211 et seq. The presentation of a benefit claim may result in an additional fee under 37 CFR 1.17(w)(1) or (2) being required, if the earliest filing date for which benefit is claimed under 35 U.S.C. 120, 121, 365(c), or 386(c) and 1.78(d) in the application is more than six years before the actual filing date of the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trinh (US 2016/0276586).
Regarding claim 1, Trinh discloses, in FIG. 5 and in related text, a method of forming an integrated chip, the method comprising:
forming a reactivity reducing coating (126 in FIG. 1B, 126’ in FIG. 5) over one or more lower interconnect layers (122) disposed over a substrate (see Trinh, [0021]-[0022], [0044]);
forming a bottom electrode layer (104 in FIG. 1B, 104’ in FIG. 5) on and in contact with the reactivity reducing coating (see Trinh, [0015], [0045]);
forming a data storage element (102 in FIG. 1B, 102’ in FIG. 5) over the bottom electrode layer (see Trinh, [0016], [0045]);
forming a top electrode layer (112 in FIG. 1B, 112’ in FIG. 5) over the data storage element (see Trinh, [0016], [0045]); and
patterning the top electrode layer, the data storage element, the reactivity reducing coating, and the bottom electrode layer to define a memory device (see Trinh, FIGS. 6 and 8, [0047], [0051]).
Trinh discloses the bottom electrode layer (104) being iridium (see Trinh, [0016]), Trinh discloses the reactivity reducing coating (126) being tungsten (see Trinh, [0022]). Since iridium has a 2.20 electronegativity in Pauling’s scale and tungsten has a 2.36 electronegativity in Pauling’s scale (see Wikipedia: Electronegativities of the elements, 12 December 2017), Trinh inherently discloses wherein the bottom electrode layer (iridium) has a first electronegativity (2.20) that is less than or equal to a second electronegativity (2.36) of the reactivity reducing coating (tungsten) as measured by numerical values according to Pauling's scale
Regarding claim 2, Trinh discloses the method of claim 1.
Trinh discloses wherein a lower surface of the bottom electrode layer (104) physically contacts an upper surface of the reactivity reducing coating (126), the lower surface of the bottom electrode layer facing the substrate (below 122) (see Trinh, FIG. 1B, [0021]).
Regarding claim 3, Trinh discloses the method of claim 1.
Trinh discloses wherein the reactivity reducing coating (126) is disposed directly between the bottom electrode layer (104) and the substrate (below 122) after forming the bottom electrode layer (see Trinh, FIG. 1B, [0021]).
Regarding claim 4, Trinh discloses the method of claim 1.
Trinh discloses forming a capping layer (106) onto an upper surface of the data storage element (102) that faces away from the substrate (below 122), wherein the capping layer is separated from the reactivity reducing coating (126) by both the data storage element (102) and the bottom electrode layer (104) (see Trinh, FIG. 1B, [0016], [0021]).
Regarding claim 5, Trinh discloses the method of claim 1.
Trinh discloses wherein the reactivity reducing coating (126’) is formed prior to forming the bottom electrode layer (104’) (see Trinh, [0045]).
Regarding claim 6, Trinh discloses the method of claim 1.
Trinh discloses wherein the reactivity reducing coating (126) is a metal (tungsten), or a doped polysilicon (see discussion on claim 1 above).
Regarding claim 7, Trinh discloses the method of claim 1.
Trinh discloses wherein the data storage element (102) is configured to enable formation of a conductive filament (114) of oxygen vacancies within and across the data storage element upon application of a bias voltage across the data storage element (see Trinh, FIG. 1B, [0017]-[0018]).
Regarding claim 8, Trinh discloses the method of claim 1.
Trinh discloses wherein the bottom electrode layer (104) continuously extends between a bottom surface of the bottom electrode layer that physically contacts the reactivity reducing coating (126) and a top surface of the bottom electrode layer that physically contacts the data storage element (102) (see Trinh, FIG. 1B).
Claims 10-12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trinh (US 2016/0276586).
Regarding claim 10, Trinh discloses, in FIG. 4 and in related text, a method of forming an integrated chip, the method comprising:
forming an opening (404) to extend through an insulating structure (402) and expose an interconnect (122) within a dielectric structure (124) over a substrate (below 122) (see Trinh, [0021], [0041]-[0042]);
forming a reactivity reducing coating (126 in FIG. 1B, 126’ in FIG. 5) directly between sidewalls of the insulating structure forming the opening (see Trinh, [0021]-[0022], [0044]);
forming a bottom electrode layer (104 in FIG. 1B, 104’ in FIG. 5) on the reactivity reducing coating and over an upper surface of the insulating structure (see Trinh, [0015], [0045]);
forming a data storage element (102 in FIG. 1B, 102’ in FIG. 5) over the bottom electrode layer (see Trinh, [0016], [0045]);
forming a top electrode layer (112 in FIG. 1B, 112’ in FIG. 5) over the data storage element; and
forming a memory device by removing parts of the top electrode layer, the data storage element, the reactivity reducing coating, and the bottom electrode layer (see Trinh, FIGS. 6 and 8, [0047], [0051]).
Trinh discloses the bottom electrode layer (104) being iridium (see Trinh, [0016]), Trinh discloses the reactivity reducing coating (126) being tungsten (see Trinh, [0022]). Since iridium has a 2.20 electronegativity in Pauling’s scale and tungsten has a 2.36 electronegativity in Pauling’s scale (see Wikipedia: Electronegativities of the elements, 12 December 2017), Trinh inherently discloses wherein the bottom electrode layer (iridium) has a first electronegativity (2.20) that is less than or equal to a second electronegativity (2.36) of the reactivity reducing coating (tungsten) as measured by numerical values according to Pauling's scale.
Regarding claim 11, Trinh discloses the method of claim 10.
Trinh discloses wherein the reactivity reducing coating (126) is a metal (tungsten), or a doped polysilicon (see discussion on claim 10 above); and
wherein the data storage element (102) is a metal-oxide (titanium oxide) (see Trinh, [0015]).
Regarding claim 12, Trinh discloses the method of claim 10.
Trinh discloses wherein the second electronegativity (2.36) is greater than 1.5 (see discussion on claim 10 above).
Regarding claim 14, Trinh discloses the method of claim 10.
Trinh discloses wherein the data storage element (102) comprises a material that is configured to enable formation of a conductive filament of oxygen vacancies by movement of oxygen atoms from the data storage element to the top electrode layer during operation (see Trinh, [0018]-[0019]).
Regarding claim 15, Trinh discloses the method of claim 10.
Trinh discloses forming a capping layer (106’) onto an upper surface of the data storage element (102’) that faces away from the reactivity reducing coating (126’) prior to forming the top electrode layer (110’), wherein the capping layer is a metal or a metal-oxide (see Trinh, FIG. 5, [0045]).
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trinh (US 2016/0276586).
Regarding claim 17, Trinh discloses, in FIG. 5 and in related text, a method of forming an integrated chip, the method comprising:
forming a reactivity reducing coating (126 in FIG. 1B, 126’ in FIG. 5) over an upper surface of an interconnect (122) within an inter-level dielectric (ILD) (124), the upper surface facing away from a substrate (below 122) (see Trinh, [0021]-[0022], [0044]);
forming a bottom electrode layer (104 in FIG. 1B, 104’ in FIG. 5) on and in contact with an upper surface of the reactivity reducing coating that faces away from the reactivity reducing coating (see Trinh, [0015], [0045]);
forming a data storage element (102 in FIG. 1B, 102’ in FIG. 5) on and in contact with an upper surface of the bottom electrode layer that faces away from the reactivity reducing coating (see Trinh, [0016], [0045]);
forming a top electrode layer (112 in FIG. 1B, 112’ in FIG. 5) over the data storage element, the top electrode layer being separated from the bottom electrode layer by the data storage element (see Trinh, [0016], [0045]); and
performing one or more etching processes to remove parts of the top electrode layer, the data storage element, the reactivity reducing coating, and the bottom electrode layer (see Trinh, FIGS. 6 and 8, [0047], [0051]).
Trinh discloses the bottom electrode layer (104) being iridium (see Trinh, [0016]), Trinh discloses the reactivity reducing coating (126) being tungsten (see Trinh, [0022]). Since iridium has a 2.20 electronegativity in Pauling’s scale and tungsten has a 2.36 electronegativity in Pauling’s scale (see Wikipedia: Electronegativities of the elements, 12 December 2017), Trinh inherently discloses wherein the bottom electrode layer (iridium) has a first electronegativity (2.20) that is less than or equal to a second electronegativity (2.36) of the reactivity reducing coating (tungsten) as measured by numerical values according to Pauling's scale.
Regarding claim 18, Trinh discloses the method of claim 17,
Trinh discloses wherein the reactivity reducing coating (126) is formed to have a thickness (in vertical direction) that varies over a width (in horizontal direction) of the reactivity reducing coating (see Trinh, FIG. 1B).
Regarding claim 19, Trinh discloses the method of claim 17,
Trinh discloses wherein a bottom surface of the reactivity reducing coating (126) has a first width (in horizontal direction) and a top surface of the reactivity reducing coating has a second width (in horizontal direction) that is different than the first width (see Trinh, FIG. 1B).
Regarding claim 20, Trinh discloses the method of claim 17,
Trinh discloses wherein the first electronegativity (2.20) has a first value and the second electronegativity (2.36) has a larger second value (see discussion on claim 17 above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Trinh.
Regarding claim 16, Trinh discloses the method of claim 10.
Trinh discloses wherein the reactivity reducing coating (126) has a vertical outer sidewall after removing the parts of the reactivity reducing coating to form the memory device (see Trinh, FIG. 8).
Trinh does not explicitly disclose a curved outer sidewall.
However, the limitation is merely changes in shape and is a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also, MPEP § 2144.04.
Allowable Subject Matter
Claims 9 and 13 each are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, Trinh, discloses forming a plurality of additional conductive materials onto the one or more lower interconnect layers prior to forming the reactivity reducing coating, wherein the plurality of additional conductive materials comprise a first additional conductive material and a second additional conductive material formed onto a topmost surface of the first additional conductive material. The prior art of records, individually or in combination, do not disclose nor teach “the second additional conductive material being a different material than the first additional conductive material” in combination with other limitations as recited in claim 9.
The prior art of records, individually or in combination, do not disclose nor teach “wherein a difference between the first electronegativity and the second electronegativity is greater than 0.2” in combination with other limitations as recited in claim 13.
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because of the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811