DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-16, and species I, Figs. 1.1A-1.1C, in the reply filed on 2/27/2026 is acknowledged. Claims 17-20 have been withdrawn from consideration.
As the Applicant correctly pointed out, the group II reads on claims 17-20, not the claims 13-20. The Examiner thanks the Applicant for correcting the misidentification of the claims.
Claim 13, however, reads on the non-elected embodiment of Figs. 1.6A-1.6B. Thus, claims 13-16 have also been withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4, 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “wherein the first semiconductor fin has a first channel region positioned laterally between first source/drain regions having a first groove extending from the first top surface downward”. The language of a groove in “a first groove” implies two vertical and opposing sidewalls joined by a bottom surface. As shown in Figs. 1.1A-1.1C of the specification of the instant application, the fin 111a has one half of the fin removed resulting in a thinner top portion. However, the resulting thinner top portion only has only one single sidewall (112a) without any opposing sidewall. So it is unclear what constitutes a groove in the claim. For the purpose of examination and to be consistent with the specification, it is interpreted that the fin having a groove includes the situation when it is partially etched to have a thinner width.
Claim 4 is dependent of claim 3, and thus inherits the same indefiniteness issue.
Claim 8 recites “wherein the second semiconductor fin has a second channel region positioned laterally between second source/drain regions and, at the second channel region, a second groove extending from the second top surface downward”. The language of a groove in “a second groove” implies two vertical and opposing sidewalls joined by a bottom surface. As shown in Figs. 1.1A-1.1C of the specification of the instant application, the fin 111b has one half of the fin removed resulting in a thinner top portion. However, the resulting thinner top portion only has only one single sidewall (112b) without any opposing sidewall. So it is unclear what constitutes a groove in the claim. For the purpose of examination and to be consistent with the specification, it is interpreted that the fin having a groove includes the situation when it is partially etched to have a thinner width.
Claim 9 is dependent of claim 8, and thus inherits the same indefiniteness issue.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh et al. (US 2020/0135580 A1).
Regarding claim 1, Hsieh teaches a structure (device in Figs. 2-16 of Hsieh) comprising:
a first semiconductor fin (240 in Fig. 14) having a first top surface (top surface of fin 240), a first inner sidewall (right sidewall of fin 240), and a first outer sidewall (left sidewall of fin 240) opposite the first inner sidewall;
a second semiconductor fin (241) parallel to the first semiconductor fin and having a second top surface (top surface of fin 241), a second inner sidewall (left sidewall of fin 241), and a second outer sidewall (right sidewall of fin 241) opposite the second inner sidewall;
a first isolation structure (275 to 500 on the left side of fin 240) immediately adjacent to the first outer sidewall; and
a gate (800 in Fig. 14) immediately adjacent to the first inner sidewall opposite the first isolation structure and further extending over the first top surface to the first isolation structure (as shown in Fig. 14 of Hsieh).
Regarding claim 2, Hsieh teaches all limitations of the structure of claim 1, and also teaches wherein the gate and the first semiconductor fin have surfaces in contact with the first isolation structure (as shown in Fig. 14 of Hsieh).
Regarding claim 10, Hsieh teaches all limitations of the structure of claim 1, and also teaches wherein the gate is further immediately adjacent the second inner sidewall, the second outer sidewall, and the second top surface (as shown in Fig. 14 of Hsieh).
Regarding claim 11, Hsieh teaches all limitations of the structure of claim 1, and further comprising a gate sidewall spacer (spacers such as vertical portions of 115 in Fig. 1 of Hsieh) defining a gate opening (distance between the gate sidewall spacers), wherein the gate and at least the first isolation structure are within the gate opening (as shown in Fig. 14 of Hsieh), and wherein the gate includes: a gate dielectric layer (gate dielectric layer described in [0020] and [0059] of Hsieh) lining the gate opening; and a gate conductor layer (gate electrode described in [0020] and [0059] of Hsieh) on the gate dielectric layer, wherein the gate dielectric layer is positioned laterally between the first isolation structure and the gate conductor layer (as implied in Fig. 13-14 of Hsieh).
Claims 1 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2014/0203376 A1).
Regarding claim 1, Xie teaches a structure (device in Figs. 11 of Xie) comprising:
a first semiconductor fin (a fin 58 immediately on the left of the isolation structure 80-84) having a first top surface (top surface of first fin 58), a first inner sidewall (left sidewall of first fin 58), and a first outer sidewall (right sidewall of first fin 58) opposite the first inner sidewall;
a second semiconductor fin (a fin 58 immediately to the left of the first fin 58) parallel to the first semiconductor fin and having a second top surface (top surface of second fin 58), a second inner sidewall (right sidewall of second fin 58), and a second outer sidewall (left sidewall of second fin 58) opposite the second inner sidewall;
a first isolation structure (etch stop layer 70) immediately adjacent to the first outer sidewall; and
a gate (88) immediately adjacent to the first inner sidewall opposite the first isolation structure and further extending over the first top surface to the first isolation structure (as shown in Fig. 11 of Xie).
Regarding claim 12, Xie teaches all limitations of the structure of claim 1, and further comprising:
a semiconductor substrate (52), wherein the semiconductor fins extend essentially vertically from the semiconductor substrate (as shown in Fig. 11); and
an insulator layer (62) on the semiconductor substrate laterally surrounding lower portions of the first semiconductor fin and the second semiconductor fin, wherein upper portions of the first semiconductor fin and the second semiconductor fin extend above the insulator layer (as shown in Fig. 11 of Xie).
Claims 1, 3, 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miura et al. (US 2021/0082766 A1).
Regarding claim 1, Miura teaches a structure (structure in Fig. 2D of Miura) comprising:
a first semiconductor fin (the right nMOS stack in Fig. 2D, hereinafter referred to as the first fin) having a first top surface (top surface of layer 5 of the first fin), a first inner sidewall (left sidewall of the first fin), and a first outer sidewall (right sidewall of the first fin) opposite the first inner sidewall;
a second semiconductor fin (the left nMOS stack, hereinafter referred to as the first fin) parallel to the first semiconductor fin and having a second top surface (top surface of layer 5 of the second fin), a second inner sidewall (right sidewall of the second fin), and a second outer sidewall (left sidewall of the second fin) opposite the second inner sidewall;
a first isolation structure (isolation structure 7) immediately adjacent to the first outer sidewall; and
a gate (10 in Fig. 2D) immediately adjacent to the first inner sidewall opposite the first isolation structure and further extending over the first top surface to the first isolation structure (as shown in Fig. 2D).
Regarding claim 3, Miura teaches all limitations of the structure of claim 1, and also teaches wherein the first semiconductor fin has a first channel region (region of first fin covered by the gate 10 in Fig. 2D of Miura) positioned laterally between first source/drain regions (13 in Fig. 13) having a first groove (the groove for the isolation structure 7) extending from the first top surface downward, so the first top surface is narrower at the first channel region than at the first source/drain regions (epitaxial S/D regions 13 is epitaxial grown so it has a flat top surface and two inclined surfaces on the two sides. Thus, the epitaxial S/D regions have larger top surface than the first fin), and wherein the first isolation structure fills the first groove (as shown in Fig. 13 of Miura).
Regarding claim 5, Miura teaches all limitations of the structure of claim 1, and also teaches wherein the second inner sidewall (right sidewall of second fin in Fig. 2D of Miura) is physically separated from the first inner sidewall (left sidewall of first fin in Fig. 2D of Miura) by a space (gap between fins), and wherein the gate further extends laterally across the space between the first semiconductor fin and the second semiconductor fin and is immediately adjacent to at least the second inner sidewall and the second top surface (as shown in Fig. 2D of Miura).
Regarding claim 6, Miura teaches all limitations of the structure of claim 5, and further comprising a second isolation structure (the left isolation structure 7 in Fig. 2D of Miura) immediately adjacent to the second outer sidewall opposite the gate, wherein the gate further extends over the second top surface to the second isolation structure (as shown in Fig. 2D of Miura).
Regarding claim 7, Miura teaches all limitations of the structure of claim 6, and also teaches wherein the gate and the second semiconductor fin have surfaces in contact with the second isolation structure (see Fig. 2D of Miura).
Regarding claim 8, Miura teaches all limitations of the structure of claim 6, and also teaches wherein the second semiconductor fin has a second channel region (region of second fin covered by the gate 10 in Fig. 2D of Miura) positioned laterally between second source/drain regions (13) and, at the second channel region, a second groove (the groove for the second isolation structure 7 in Fig. 2D of Miura) extending from the second top surface downward, so the second top surface is narrower at the second channel region than at the second source/drain regions (epitaxial S/D regions 13 is epitaxial grown so it has a flat top surface and two inclined surfaces on the two sides. Thus, the epitaxial S/D regions have larger top surface than the first fin), and wherein the second isolation structure fills the second groove (as shown in Fig. 2D of Miura).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Miura as applied in claims 3 and 8, respectively.
Regarding claim 4, Miura teaches all limitations of the structure of claim 3, but does not explicitly teach wherein the first top surface at the first channel region is half as wide as the first top surface at the first source/drain regions.
As is well-known in the art, one of the reason to form the epitaxial S/D regions is to increase the top surface of the S/D region, which makes it easier to form the S/D contacts to the S/D region.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the top surface of the epitaxial S/D region twice as large as that of the fin region in order to make it twice as easy to land the S/D contacts on the S/D region.
Regarding claim 9, Miura teaches all limitations of the structure of claim 8, but does not explicitly teach wherein the second top surface at the second channel region is half as wide as the second top surface at the second source/drain regions.
As is well-known in the art, one of the reason to form the epitaxial S/D regions is to increase the top surface of the S/D region, which makes it easier to form the S/D contacts to the S/D region.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the top surface of the epitaxial S/D region twice as large as that of the fin region in order to make it twice as easy to land the S/D contacts on the S/D region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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