DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/27/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-17, 20-22, and 25-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Madurawe et al. (U.S. Publication 2020/0135795 A1; hereinafter Madurawe)
With respect to claim 15, Madurawe discloses a method, comprising: forming a first integrated circuit (IC) chip [34], wherein the forming of the first IC chip comprises forming a plurality of first transistors [44] on a first substrate and depositing a first dielectric layer covering the plurality of first transistors (See ¶[0032]); forming a pair of first conductive pads [38A] and a first shield structure [60] recessed into the first dielectric layer, wherein the first shield structure separates the first conductive pads (see Figure 6); forming a second IC chip [36], wherein the forming of the second IC chip comprises forming a plurality of second transistors [52] on a second substrate and depositing a second dielectric layer covering the plurality of second transistors (see ¶[0032]); forming a pair of second conductive pads [38B] and a second shield structure [60] recessed into the second dielectric layer (See ¶[0040]); and bonding the first IC chip to the second IC chip, wherein the first conductive pads respectively and directly contact the second conductive pads at a bond interface and the first and second shield structures directly contact at the bond interface (See Figure 6).
With respect to claim 16, Madurawe discloses wherein the bonding electrically couples the first transistors respectively to the second transistors through the pairs of first and second conductive pads (See Figure 6).
With respect to claim 17, Madurawe discloses wherein the forming of the first IC chip comprises forming a plurality of photodiodes [62] in the first substrate, respectively adjacent to the first transistors, wherein the plurality of photodiodes are grouped into multi-dimensional blocks in a plurality of rows and columns, and wherein the pair of first conductive pads respectively and directly underlie corresponding ones of the multi-dimensional blocks (See Figure 10).
With respect to claim 20, Madurawe discloses forming a plurality of shield structures, including the first shield structure, evenly spaced in a first closed path around a first one of the pair of first conductive pads and evenly spaced in a second closed path around a second one of the pair of first conductive pads, wherein the first and second closed paths are only partially overlapping (See Figure 10).
With respect to claim 21, Madurawe discloses a method comprising: forming a pair of photodetectors [62] in a first substrate [42]; forming a pair of transfer transistors [44] respectively bordering the pair of photodetectors on a first side of the first substrate, wherein the pair of transfer transistors share a floating diffusion region [46A] in the first substrate; forming a first interconnect structure [66A] on the first side of the first substrate and electrically coupled to the pair of transfer transistors; and forming a first integrated circuit (IC) chip, comprising: forming a pair of first shield structures [60] and a first conductive pad [38A] between the pair of first shield structures, wherein the first conductive pad is electrically coupled to the floating diffusion region via the first interconnect structure and the pair of first shield structures are spaced from the first interconnect structure; and bonding a second IC chip [36] to the first IC chip, wherein the second IC chip contacts the first conductive pad and the pair of first shield structures on the first side of the first substrate at completion of the bonding (See Figure 10).
With respect to claim 22, Madurawe discloses wherein the floating diffusion region overlies the first conductive pad after the bonding (See Figure 6).
With respect to claim 25, Madurawe discloses wherein the second IC chip comprises a plurality of pixel transistors [52], and wherein the bonding electrically couples the first conductive pad to the plurality of pixel transistors (see Figure 6).
With respect to claim 26, Madurawe discloses wherein the forming of the second IC chip comprises: forming a plurality of pixel transistors [52] on a second substrate [42]; forming a second interconnect structure [66B] on the second substrate and electrically coupled to the plurality of pixel transistors; and forming a second conductive pad [38B] electrically coupled to the plurality of pixel transistors via the second interconnect structure, wherein the first and second conductive pads contact each other at completion of the bonding (see Figure 6).
With respect to claim 27, Madurawe discloses wherein the forming of the second IC chip comprises: forming a pair of second shield structures [60] between which the second conductive pad [38B] is arranged, wherein the pair of second shield structures are spaced from the second interconnect structure and contact the pair of first shield structures at completion of the bonding (see Figure 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 18 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madurawe in view of Jang et al. (U.S. Publication No. 2023/0081238 A1; hereinafter Jang).
With respect to claim 18, Madurawe fails to disclose wherein the forming of the pair of first conductive pads and the first shield structure comprises: patterning the first dielectric layer to form pad openings and a shield opening; depositing a conductive layer filling the pad openings and a shield opening; and performing a planarization into the conductive layer, but does disclose the shielding structures are formed using the same conductive layer as the conductive pads (see ¶[0040]) In the same field of endeavor, Jang teaches patterning the first dielectric layer to form pad openings and a shield opening (see ¶[0113]); depositing a conductive layer filling the pad openings and a shield opening (see ¶[0114]); and performing a planarization into the conductive layer (see ¶[0114]). Implementation of producing the conductive layer as taught by Jang can be implemented as it well appreciated in the art of producing multiple conductive pads and shielding structures as all are produced in the same material in the same layer. (see ¶[0115]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 24, Madurawe fails to disclose wherein the forming of the pair of first shield structures and the first conductive pad comprises: depositing a dielectric layer on the first interconnect structure; patterning the dielectric layer to form a pad opening and a pair of shield openings; depositing a conductive layer filling the pad opening and the pair of shield openings; and performing a planarization into the conductive layer, but does disclose the shielding structures are formed using the same conductive layer as the conductive pads (see ¶[0040]).
In the same field of endeavor, Jang teaches depositing a dielectric layer [112] on the first interconnect structure (See Figure 18); patterning the dielectric layer to form a pad opening and a pair of shield openings (see ¶[0113]); depositing a conductive layer filling the pad opening and the pair of shield openings (see ¶[0114]); and performing a planarization into the conductive layer (see ¶[0114]). Implementation of producing the conductive layer as taught by Jang can be implemented as it well appreciated in the art of producing multiple conductive pads and shielding structures as all are produced in the same material in the same layer. (see ¶[0115]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 19 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madurawe in view of Nitta et al (U.S. Publication No. 2024/0006437 A1; hereinafter Nitta)
With respect to claim 19, Madurawe fails to disclose wherein the forming of the pair of first conductive pads and the first shield structure comprises: patterning the first dielectric layer to form pad openings; depositing a conductive layer filling the pad openings; performing a first planarization into the conductive layer; patterning the first dielectric layer to form a shield opening; depositing a low k dielectric layer filling the shield opening; and performing a second planarization into the low k dielectric layer. In the same field of endeavor, Nitta teaches wherein the forming of the pair of first conductive pads and the first shield structure comprises: patterning the first dielectric layer [56c] to form pad openings [58a] (see Figure 8E); depositing a conductive layer [58] filling the pad openings (see Figure 8F); performing a first planarization into the conductive layer (see Figure 8G); patterning the first dielectric layer to form a shield opening (See Figure 12A); depositing a low k dielectric layer [85] filling the shield opening; and performing a second planarization into the low k dielectric layer (See ¶[0156] and ¶[0161]; Figure 9A and 15). Implementation of a deposition and planarization process is well appreciated in the art to provide a level surface for which bonding surface is increased and improved (See ¶[0182-0183]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 23, Madurawe fails to disclose wherein the pair of first shield structures comprise a dielectric material. In the same field of endeavor, Nitta teaches a pair of first shield structures [85] comprise a dielectric material. Shield structures comprising dielectric material as taught by Nitta provides electrical insulation between bonding structures (see ¶[0131]; note that shield structures are ambiguously defined by the claims and can mean any type of shielding). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 28-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Horikoshi (U.S. Publication No. 2022/0077215 A1) in view of Madurawe.
With respect to claim 28, Horikoshi discloses a method comprising: forming a first semiconductor structure, comprising: forming a photodetector [10] in a first substrate [1]; forming a transfer transistor [16a] bordering the photodetector on a first side of the first substrate; forming a second semiconductor structure, comprising forming a plurality of pixel transistors [34a,34b] on a first side of a second substrate [3]; bonding the second semiconductor structure to the first semiconductor structure with a second side of the second substrate, opposite the first side of the second substrate, facing the first semiconductor structure (see Figure 10A); forming a through via [33ba] extending through the second semiconductor structure, from the first side of the second substrate to the transfer transistor; forming a first conductive pad [38d], electrically coupled to the plurality of pixel transistors; and bonding a third semiconductor structure [5] to the second semiconductor structure at the first conductive pad (See Figure 10A).
Horikoshi fails to disclose a first shield structure on the first side of the second substrate and the first shield structure. In the same field of endeavor, Madurawe teaches a first shield structure [60] alongside a first conductive pad [38A] (See Figure 6). Implementation of the shield structure of Madurawe within the device of Horikoshi prevents cross-talk between conductive lines (see Madurawe ¶[0043]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 29, the combination of Horikoshi and Madurawe discloses
forming a plurality of first shield structures, including the first shield structure, that are spaced in a ring-shaped pattern around the first conductive pad and that contact the third semiconductor structure (See Madurawe Figure 10).
With respect to claim 30, the combination of Horikoshi and Madurawe discloses wherein the first shield structure extends in a closed path around the first conductive pad (see Madurawe Figure 10).
With respect to claim 31, the combination of Horikoshi and Madurawe discloses wherein the forming of the third semiconductor structure comprises: forming a plurality of logic transistors [52] on a third substrate; and forming a second conductive pad [58c] and a second shield structure (see Horikoshi Figure 3A and Madurawe Figure 6), wherein the second conductive pad is electrically coupled to a transistor of the plurality of logic transistors, and wherein the second conductive pad and the second shield structure respectively contact the first conductive pad and the first shield structure at completion of the bonding of the third semiconductor structure to the second semiconductor structure (see Horikoshi Figure 3A and Madurawe Figure 6).
With respect to claim 32, the combination of Horikoshi and Madurawe discloses wherein the forming of the second semiconductor structure further comprises: forming an interconnect structure [38a/38b/39] on the first side of the second substrate, wherein the first conductive pad and the through via electrically couple to the plurality of pixel transistors via the interconnect structure (see Horikoshi Figure 3A).
With respect to claim 33, the combination of Horikoshi and Madurawe discloses forming a trench isolation structure [19] extending into a second side of the first substrate, opposite the first side of the first substrate, and extending laterally in a closed path around the photodetector, wherein the trench isolation structure overlies the first shield structure (see Hirokoshi Figure 3A; Madurawe Figure 6 [42]).
With respect to claim 34, the combination of Horikoshi and Madurawe discloses wherein the trench isolation structure further overlies the first conductive pad (see Hirokoshi Figure 3A; Madurawe Figure 6 [42]).
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818