DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, species A, in the reply filed on 5/4/2026 is acknowledged. Claims 18-20 have been canceled. Claims 9, 15 and 17 have been withdrawn from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-7, 10-11, 13, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsiao et al. (US 2021/0305386 A1).
Regarding claim 1, Hsiao teaches a semiconductor structure (IC structure 100 in Fig. 4A), comprising:
a semiconductor substrate (substrate of the IC 100) having a first circuit region (120 in Fig. 4A) and a second circuit region (122 in Fig. 4A);
first transistors (FETs in region 120) that include first gate stacks (112A) disposed in the first circuit region;
second transistors (FETs in region 122) that include second gate stacks (112B) disposed in the second circuit region, wherein the first gate stacks and the second gate stacks have different material compositions (as described in [0033] of Hsiao, the gates 112A and 112B have different gate compositions); and
a guard ring structure (150-152) disposed between the first circuit region and the second circuit region, wherein the guard ring structure fully surrounds the second circuit region (as shown in Fig. 4A).
Regarding claim 2, Hsiao teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the second transistors are high-frequency transistors and the first transistors are logic transistors (as described in [0034] of Hsiao).
Regarding claim 4, Hsiao teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the guard ring structure includes at least a dummy gate stack (as described in [0012], the guard rings are dummy gate structures) extends continuously and fully surrounds the second circuit region (as shown in Fig. 4A of Hsiao).
Regarding claim 5, Hsiao teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the guard ring structure includes a first dummy gate stack (inner guard ring of the region 122) and a second dummy gate stack (outer guard ring of the region 122), wherein each of the first and second dummy gate stacks extends continuously and fully surrounds the second circuit region (see Fig. 4A of Hsiao).
Regarding claim 6, Hsiao teaches all limitations of the semiconductor structure of claim 5, and also teaches wherein the first and second dummy gate stacks are disposed on at least a same active region (see Fig. 4A of Hsiao).
Regarding claim 7, Hsiao teaches all limitations of the semiconductor structure of claim 6, and also teaches wherein the active region has a fin shape (106 in Figs. 1A-1D of Hsiao) protruding from the semiconductor substrate.
Regarding claim 10, Hsiao teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the first gate stacks have a first gate pitch less than a reference pitch, and the second gate stacks have a second gate pitch larger than the reference pitch (as described in [0032] of Hsiao).
Regarding claim 11, Hsiao teaches a semiconductor structure (IC structure 100 in Fig. 4A), comprising:
a semiconductor substrate (substrate of IC 100) having a logic circuit region (120 in Fig. 4A) and a radio frequency (RF) circuit region (122 in Fig. 4A);
first transistors (FETs in region 120) that include first gate stacks (112A) disposed in the logic circuit region;
second transistors (FETs in region 122) that include second gate stacks (112B) disposed in the RF circuit region; and
a guard ring structure (150-152 in Fig. 4A) disposed between the logic circuit region and the RF circuit region, wherein the guard ring structure includes an inner guard ring (inner guard ring of 152) fully surrounding the RF circuit region and an outer guard ring (outer guard ring of 152) fully surrounding the inner guard ring and the RF circuit region (see Fig. 4A of Hsiao).
Regarding claim 13, Hsiao teaches all limitations of the semiconductor structure of claim 11, and also teaches wherein the outer guard ring includes a first dummy gate stack (as described in [0012], the guard rings are dummy gate structures), and the inner guard ring includes a second dummy gate stack(as described in [0012], the guard rings are dummy gate structures), and wherein the first and second dummy gate stacks are disposed on a same active region (as shown in Fig. 4A of Hsiao).
Regarding claim 16, Hsiao teaches all limitations of the semiconductor structure of claim 11, and also teaches wherein the inner guard ring (156 in Fig. 4B of Hsiao) includes a first metal fill layer (as described in [0047] of Hsiao), the outer guard ring (160-164 in Fig. 4B of Hsiao) includes a second metal fill layer (as described in [0047] of Hsiao), and wherein the first metal fill layer has a width larger than the second metal fill layer (as shown in Fig. 4B of Hsiao).
Allowable Subject Matter
Claims 3, 8, 12, 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record does not disclose or fairly suggest a semiconductor structure satisfying “wherein the first circuit region fully surrounds the second circuit region” along with other limitations of claim 1.
Regarding claim 8, the prior art of record does not disclose or fairly suggest a semiconductor structure satisfying “wherein the first gate stacks and the first dummy gate stack include a same material composition that is different from the second gate stacks and the second dummy gate stack” along with other limitations of claim 1.
Regarding claim 12, the prior art of record does not disclose or fairly suggest a semiconductor structure satisfying “wherein the guard ring structure further includes an epitaxial feature disposed between the inner guard ring and the outer guard ring, and a metal line electrically coupled to the epitaxial feature, and wherein the metal line fully surrounds the RF circuit region” along with other limitations of claim 11.
Regarding claim 14, the prior art of record does not disclose or fairly suggest a semiconductor structure satisfying “wherein the first dummy gate stack includes a first material composition same as the first gate stacks, and the second dummy gate stack includes a second material composition same as the second gate stacks” along with other limitations of claim 11.
Regarding claim 21, the prior art of record does not disclose or fairly suggest a semiconductor structure “a guard ring structure disposed between the logic circuit region and the RF circuit region, wherein: the guard ring structure includes an inner guard ring surrounding the RF circuit region and an outer guard ring surrounding the inner guard ring and the RF circuit region, the outer guard ring includes a third gate dielectric layer and a third gate metal layer disposed on the third gate dielectric layer, the inner guard ring includes a fourth gate dielectric layer and a fourth gate metal layer disposed on the fourth gate dielectric layer, the first gate metal layer and the third gate metal layer both have a first material composition, and the second gate metal layer and the fourth gate metal layer both have a second material composition that is different from the first material composition” along with other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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