DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 6-24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub. No. US 2022/0037192 A1) in view of Lee et al. (PG Pub. No. US 2022/0238713 A1).
Regarding claim 1, Yu teaches a semiconductor device (figs. 40A-40C), comprising:
a device layer (¶ 0065: composite layer comprising gate, source/drain and channel elements of transistors 109) comprising a front side and a back side opposite to each other (figs. 40A-40C among others: transistor layer comprises front and back sides), the device layer further comprising:
source/drain (S/D) structures (¶ 0043: 92);
semiconductor channel layers (¶ 0021: 54) connecting the S/D structures (fig. 40C: 54 connects S/D portions 92); and
a gate structure (¶ 0056: 100/102) disposed between the S/D structures (fig. 40C: at least portion 102 disposed between S/D portions 92) and around each of the semiconductor channel layers (fig. 40A: at least portion 102 disposed around each 54), wherein the back side is planar and comprises bottom surface of the S/D structures and a bottom surface of the gate structure (fig. 40A and/or 40B: at least a portion of back side is planar and comprises bottom surfaces of 92 and 109);
a dielectric layer (¶ 0062: 106) overlying the front side of the device layer (figs. 40A-40C: 106 overlies front side of 109);
a gate contact (¶ 0061: 114) penetrating through the dielectric layer to be in contact with a topmost segment of the gate structure (figs. 40A-40C: 114 penetrates through 106 to contact topmost portion of 100/102) disposed on a topmost one of the semiconductor channel layers (figs. 40A-40C topmost portion of 100/102 disposed on topmost semiconductor layer 54C); and
a dielectric layer (¶ 0086: 132) disposed on the back side of the device layer (fig. 40C: 132 disposed on back side of 109).
Yu is silent to the dielectric layer comprising a bonding layer, a top surface of the bonding layer is aligned with the bottom surfaces of the S/D structures and the bottom surface of the gate structure, and the semiconductor device further comprises a carrier substrate underlying the bonding layer.
Lee teaches a semiconductor device (¶ 0014 & fig. 6M: 100A) including a planar device layer surface comprising S/D structures (140, similar to 92 of Yu) and a gate structure (132, similar to 100/102 of Yu), a bonding dielectric layer (¶ 0065: composite layer including elements 110 and 688) disposed on the back side of the device layer (fig. 6M: 110/688 at least indirectly disposed on planar surface including 140 and 132), wherein a top surface of the bonding layer is aligned with the bottom surfaces of the S/D structures and the bottom surface of the gate structure (fig. 6M among others: top surface of 110/688 aligned with bottom surfaces of 140 and 132); and
a carrier substrate (¶ 0065: 685) underlying the bonding layer (fig. 6M: 685 underlies 110/688).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Yu with the backside bonding/carrier structure of Lee, as a means to provide support for subsequent BEOL processing, such as connecting external conductive features to the gate and/or source/drain elements.
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Regarding claim 3, Yu in view of Lee teaches the semiconductor device of claim 1, wherein the S/D structures and the gate structure are bonded to the carrier substrate through the bonding layer (Lee, ¶ 0065 & fig. 6M: 140 and 132 at least indirectly bonded to 685 through 110/688).
Regarding claim 4, Yu in view of Lee teaches the semiconductor device of claim 1, wherein the bonding layer comprises first segments and a second segment separating the first segments from one another, and the S/D structures are bonded to the carrier substrate through the first segments (Lee, fig. 6M: 110/688 includes first portions bonding 140 to 685, and a second portion separated by first portions).
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Regarding claim 6, Yu in view of Lee teaches the semiconductor device of claim 1, wherein the back side of the device layer comprises planarized marks (Lee, fig. 6I: back side of transistor layer comprising 132/140 comprises a planarized surface pattern, meeting the broadest reasonable interpretation of ‘planarized marks’).
Regarding claim 7, Yu in view of Lee teaches the semiconductor device of claim 1, wherein the device layer further comprises:
an inner spacer (Yu, ¶ 0051: 90, and/or Lee, ¶ 0031: 138) laterally separating the gate structure from the S/D structures (Yu, fig. 40C: 90 separates 102 from 92, and/or Lee, fig. 6M: 138 separates 132 from 140), wherein the inner spacer is bonded to the carrier substrate through the bonding layer (Lee, fig. 6M: 138 at least indirectly bonded to 685 through 110/688).
Regarding claim 8, Yu teaches a semiconductor device (figs. 40A-40C among others), comprising:
a dielectric layer (¶ 0086: 132); and
a device layer (¶ 0065: layer comprises transistors 109) overlying the dielectric layer (fig. 40C: layer comprising 109 overlies 132) and comprising:
semiconductor channel layers (¶ 0021: 54) vertically separating apart from one another (fig. 40C: 54A, 54B, 54C vertically separated);
a gate structure (¶ 0061: 102 and/or 114) between adjacent two of the semiconductor channel layers (fig. 40C: portion 102 disposed between vertically adjacent channel layers 54A, 54B and/or 54C);
inner spacers (¶ 0041: 90) disposed on opposite sidewalls of the gate structure (fig. 40C: 90 disposed on sidewalls of portion 102); and
source/drain (S/D) structures (¶ 0044: 92) laterally abutting the semiconductor channel layers and the inner spacers (fig. 40C: portions 92 laterally abut 54 and 90); and
an etch stop layer (¶ 0052: 94) lining a sidewall of a topmost segment of the gate structure and top surfaces of the S/D structures (fig. 40C: 92 lines sidewall and topmost surfaces of 102 and top surfaces of 92), wherein the top surfaces of the S/D structures are opposite to bottom surfaces of the S/D structures, and the top surfaces of the S/D structures are disposed between a top surface of the topmost segment of the gate structure and a top surface of a topmost one of the semiconductor channel layers underlying the topmost segment of the gate structure (fig. 40C: top surfaces of 92 disposed between a top surface of the topmost segment of 102 and a top surface of topmost semiconductor channel layer 54C).
Yu does not teach the dielectric layer is a bonding layer overlying a carrier substrate, the device layer overlying the bonding layer, the bottom surfaces of the S/D structures are bonding surfaces, wherein the top surfaces of the S/D structures are opposite to the bonding surfaces of the S/D structures.
Lee teaches a semiconductor device (¶ 0014 & fig. 6M: 100A) including a bonding dielectric layer (¶ 0065: composite layer including elements 110 and 688) disposed on a carrier substrate (¶ 0065: 685), and a device layer (¶ 0017: composite device layer including elements 120A-120C, 132 and/or 140 among others) over the bonding dielectric layer (fig. 6M: 122/132 disposed over 110/688), the bottom surfaces of S/D structures are bonding surfaces opposite to top surfaces (fig. 6M: 140 comprises bottom surfaces at least indirectly bonded to carrier 685).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Yu with the backside structure of Lee, as a means to provide support for subsequent BEOL processing, such as connecting external conductive features to the gate and/or source/drain elements.
Regarding claim 9, Yu in view of Lee teaches the semiconductor device of claim 8, wherein a bottom surface of the gate structure is substantially coplanar with the bonding surfaces of the S/D structures (Lee, fig. 6M: bottom surface of 132 substantially coplanar with bottom bonding surfaces of 140).
Regarding claim 10, Yu in view of Lee teaches the semiconductor device of claim 9, wherein the bottom surface of the gate structure is bonded to the carrier substrate through the bonding layer (Lee, fig. 6M: bottom surface of 132 at least indirectly bonded to 685 through 110/688).
Regarding claim 11, Yu in view of Lee teaches the semiconductor device of claim 8, wherein bottom surfaces of the inner spacers are substantially coplanar with the bonding surfaces of the S/D structures (Lee, fig. 6M: bottom surfaces of 138 substantially coplanar with bonded bottom surfaces of 140).
Regarding claim 12, Yu in view of Lee teaches the semiconductor device of claim 11, wherein the bottom surfaces of the inner spacers are bonded to the carrier substrate through the bonding layer (Lee, fig. 6M: bottom surfaces of 138 at least indirectly bonded to 685 through 110/688).
Regarding claim 13, Yu in view of Lee teaches the semiconductor device of claim 8, wherein the bonding layer comprises first segments and a second segment separating the first segments from one another, and each of the S/D structures is bonded to the carrier substrate through one of the first segments (Lee, fig. 6M: 110/688 includes first portions bonding 140 to 685, and a second portion separated by first portions).
Regarding claim 14, Yu in view of Lee teaches the semiconductor device of claim 13, wherein the second segment is vertically interposed between the carrier substrate and the gate structure (Lee, second portions of 110/688 vertically interposed between 685 and 132) and is vertically interposed between the carrier substrate and the inner spacers (Lee, fig. 6M: second portion of 110/688 vertically interposed between 685 and 138).
Regarding claim 21, Yu teaches a semiconductor device (figs. 40A-40C among others), comprising:
a dielectric layer (¶ 0044: 125);
a first source/drain (S/D) structure (¶ 0045: 92) comprising a first side interfaced with the dielectric layer (fig. 40C: 92 interfaces with 125) and a second side opposite to the first side (top side of 92), wherein an interface of the first side of the first S/D structure and the dielectric layer is planar (see annotated figs. 40A-40B of Yu above: at least a portion of 92 and 125 are coplanar);
a first gate structure (¶ 0058: 102) comprising a first side interfaced with the dielectric layer (fig. 40C: 102 interfaces with 125) and a second side opposite to the first side (top side of 102);
a first channel layer (¶ 0021: 54A, 54B and/or 54C) disposed on the second side of the first gate structure (fig. 40C: 54A/B/C disposed on top surface of 102) and laterally connected to the first S/D structure (fig. 40C: 54A/B/C laterally connected to portion 92); and
a second gate structure (second 102, or top portion of 102) disposed over the first channel layer (fig. 40C: second/top 102 disposed over 54A/B/C), the second gate structure comprising a first side in proximity to the first channel layer and a second side opposite to the first side, wherein the second side of the first S/D structure is disposed between the first side and the second side of the second gate structure (fig. 40C: top surface of 92 disposed between top and bottom surfaces of second/top 102).
Yu does not teach the dielectric layer is a bonding layer disposed on carrier substrate, the device layer overlying the bonding layer, the bottom surfaces of the S/D structures are bonding surfaces, wherein the top surfaces of the S/D structures are opposite to the bonding surfaces of the S/D structures.
Lee teaches a semiconductor device (¶ 0014 & fig. 6M: 100A) including a bonding dielectric layer (¶ 0065: composite layer including elements 110 and 688) disposed on a carrier substrate (¶ 0065: 685), and a device layer (¶ 0017: composite device layer including elements 120A-120C, 132 and/or 140 among others) over the bonding dielectric layer (fig. 6M: 122/132 disposed over 110/688), the bottom surfaces of S/D structures are bonding surfaces opposite to top surfaces (fig. 6M: 140 comprises bottom surfaces at least indirectly interfaced with 110/688 and bonded to carrier 685).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Yu with the backside structure of Lee, as a means to provide support for subsequent BEOL processing, such as connecting external conductive features to the gate and/or source/drain elements.
Regarding claim 22, Yu in view of Lee teaches the semiconductor device of claim 21, further comprising:
an inner spacer (Yu, ¶ 0041: 90, and/or Lee, ¶ 0043: 138) laterally surrounding the first gate structure and separating the first gate structure from the first S/D structure (Yu, fig. 40C: 90 laterally surrounds first 102 and separates first 102 from first 92), the inner spacer comprising a first side interfaced with the bonding layer and substantially coplanar with the first side of the first gate structure (Lee, fig. 6M: 138 at least indirectly interfaced with 110/688 and substantially coplanar with bottom surface of 132).
Regarding claim 23, Yu in view of Lee teaches the semiconductor device of claim 21, further comprising:
a second S/D structure (Lee, fig. 6M: second 140) comprising a first side interfaced with the bonding layer (Lee, fig. 6M: second 140 at least indirectly interfaced with 110/688) and laterally connected to the first channel layer (Lee, ¶ 0017 & fig. 6M: second 140 laterally connected to 120A), wherein the first side of the second S/D structure is substantially coplanar with the first side of the first gate structure (Lee, fig. 6M: bottom surface of second 140 substantially coplanar with bottom surface of 132).
Regarding claim 24, Yu in view of Lee teaches the semiconductor device of claim 21, further comprising:
a second channel layer (Yu, ¶ 0021: 54B or 54C) disposed above the first channel layer and laterally connected to the first S/D structure (Yu, fig. 40C: 54B/C disposed above 54A/B and laterally connected to first 92); and
the second gate structure (Yu, second/top portion of 102) disposed on the second channel layer (Yu, top portion of 102 disposed on 54B/C); and
an etch stop layer (Yu, ¶ 0052: 94) extending along a sidewall of the second gate structure and extending on a second side of the first S/D structure (Yu, fig. 40C: 94 extends along sidewall of second/top portion of 102 and on second side of first 92).
Regarding claim 26, Yu in view of Lee teaches the semiconductor device of claim 25, wherein a boundary of the first segment and the second segment is substantially aligned with a sidewall of the first S/D structure connected to the first side of the first S/D structure (Lee, fig. 6M).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Lee as applied to claim 1 above, and further in view of Cheng et al. (PG Pub. No. US 2020/0075720 A1).
Regarding claim 2, Yu in view of Lee teaches the semiconductor device of claim 1, wherein
the gate structure comprising an interfacial layer a gate dielectric layer (¶ 0056: 100) and a gate metal layer (Yu, ¶ 0056: 102) overlying the gate dielectric layer (Yu, fig. 40C: 102 overlies 100),
the S/D structures are epitaxial structures (Yu, ¶ 0043: 92 consists of epitaxial material, and/or Lee, ¶ 0017: 140 consists of epitaxial material),
the back side of the device layer comprises bottom surfaces of the epitaxial structures (Lee, fig. 6L: backside of device 100A comprises bottom surfaces of epitaxial S/D structures 140), and
a bottom surface of the gate structure is substantially coplanar with the bottom surfaces of the epitaxial structures (Lee, fig. 6M: bottom surface of 132 substantially coplanar with bottom surfaces of 140).
Yu in view of Lee as applied to claim 1 above does not teach wherein the gate structure further comprises an interfacial layer, the gate dielectric layer overlying the interfacial layer, or the interfacial layer of the gate structure is substantially coplanar with the bottom surfaces of the epitaxial structures.
However, Lee does teach a gate structure (¶ 0057: metal gates 157) comprising an interfacial layer, a gate dielectric layer overlying the interfacial layer, and a gate metal layer overlying the gate dielectric layer (¶ 0057: metal gates 132 include a gate dielectric and interface layers. In some embodiments, the gate dielectric layer is disposed over an interfacial layer, and the gate electrode is disposed over the gate dielectric layer). Lee further teaches metal gates are substantially coplanar with the bottom surfaces of the epitaxial structures (fig. 6M: bottom surface of 132 substantially coplanar with bottom surfaces of 140).
Cheng teaches a semiconductor device (fig. 13 among others) including an interfacial layer of a gate structure (¶ 0066: interfacial layer of gate dielectric 160) is substantially coplanar with the bottom surfaces of source/drain epitaxial structures (fig. 13 among others: 160 substantially coplanar with bottom surfaces of source/drain epitaxial structures 140).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the interfacial layer of Yu in view of Lee with the planarity of Cheng, as a means to passivate a substrate surface (exposed surface of 605 of Lee, and/or exposed surface of 105 of Cheng), preventing or minimizing interface traps and charges and other issues which can degrade device performance (Cheng, ¶ 0066).
Claims 5 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Lee as applied to claims 4 and 21 above, and further in view of Huang et al. (PG Pub. No. US 2022/0028752 A1).
Regarding claims 5 and 25, Yu in view of Lee teaches the semiconductor devices of claims 4 and 21, wherein the second segment is vertically interposed between the carrier substrate and the gate structure (Lee, fig. 6M: second portion of 110/688 disposed between vertically interposed between 685 and 132),
Yu in view of Lee does not teach the first segments and the second segment are of different materials.
Huang teaches a bonding layer (¶ 0056: 154) including different material (¶¶ 0058-0061: 154 includes layers 154A and 154B of different material).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the bonding layer segments of Yu in view of Lee with different material, as a means to provide electrical isolation, thermal conductivity, and/or bonding properties (Huang, ¶ 0056).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the bonding layer materials of Huang would be suitable to provide the intended use as a bonding layer.
Response to Arguments
Applicant’s arguments, see page 8, filed 2/26/2026, with respect to the 35 USC § 112(b) rejection of claim 24 have been fully considered and are persuasive. Accordingly, this rejection has been withdrawn.
Applicant’s arguments with respect to the 35 USC § 103 rejections of claims 1-14 and 21-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (PG Pub. No. US 2014/0151639 A1) teaches surfaces of a gate structure (52A) and source/drain structures (130S/130D) are coplanar and interface with a bonding dielectric layer (14) over a carrier substrate (10).
Mannebach et al. (PG Pub. No. US 2024/0332064 A1) teaches a bonding layer (116) formed on a planar surface of a transistor layer (fig. 1: 116 formed on a planar surface of 102, including gate electrodes 106).
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/BRIAN TURNER/Examiner, Art Unit 2818
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