DETAILED ACTION
This Notice is responsive to communication filed on 04/02/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 04/02/2026 under 37 CFR 1.111 has been entered.
Claims 1, 2, 4-6, 8-18 are pending in the application. Claims 3, 19, and 20 have been cancelled. Claim 7 remains withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Williams et al. (US 20200365782).
Regarding claim 14, Williams teaches a light-emitting diode (LED) chip, comprising:
a carrier submount Fig. 20: 354;
an active LED structure Fig. 20: 356 on the carrier submount Fig. 20: 354;
a reflective structure Fig. 20: 366+368+376 (para.0120 describes the barrier layer 376 as part of the active region and the metal layer 368) between the active LED structure Fig. 20: 356 and the carrier submount Fig. 20: 354, the reflective structure Fig. 20: 366+368+376 comprising a dielectric layer Fig. 20: 366 (para. 0111), a metal layer Fig. 20: 368 (para. 0114), and a number of reflective layer interconnects Fig. 20: 374 that extend from the metal layer Fig. 20: 368 to form electrically conductive paths through the dielectric layer Fig. 20: 366 (para. 0116, shown in Fig. 20);
a passivation layer Fig. 20: 380+396 between the reflective structure Fig. 20: 366+368+376 and the carrier submount Fig. 20: 354; and
a barrier layer Fig. 20: 386 arranged between the passivation layer Fig. 20: 380+396 and the carrier submount Fig. 20: 354, the barrier layer Fig. 20: 386 being electrically coupled to the reflective structure Fig. 20: 366+368+376 by a number of barrier interconnects Fig. 20: 398 that extend through the passivation layer Fig. 20: 380+396 (at 380), the barrier interconnects Fig. 20: 398 contacting portions of the reflective structure Fig. 20: 366+368+376 (at portion 376) that are laterally offset from the reflective layer interconnects Fig. 20: 374.
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Regarding claim 15, Williams teaches the LED chip of claim 14, wherein the active LED structure Fig. 20: 356 forms a mesa with mesa side walls that define a perimeter of the active LED structure Fig. 20: 356 (see annotated Fig. 20 above); and a portion of the passivation layer Fig. 20: 380+396 laterally extends past the mesa side walls.
Regarding claim 16, Williams teaches the LED chip of claim 15, further comprising a top passivation layer Fig. 20: 406 on the mesa sidewalls, wherein the top passivation layer Fig. 20: 406 contacts the passivation layer Fig. 20: 380 past the mesa side walls.
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Regarding claim 18, Williams teaches the LED chip of claim 14, wherein the barrier interconnects Fig. 20: 388+398 are electrically coupled to the metal layer Fig. 20: 368 (via part 398).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 1, 2, 4-6, 8-13, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US 20200365782), and further in view of Donofrio et al. (US 20160211420).
Regarding claim 1, Williams teaches a light-emitting diode (LED) chip Fig. 20: 350, comprising:
a carrier submount Fig. 20: 354;
an active LED structure Fig. 20: 356 on the carrier submount Fig. 20: 354, the active LED structure Fig. 20: 356 comprising an n-type layer Fig. 20: 360, a p-type layer Fig. 20: 358, and an active layer Fig. 20: 362 that is between the n-type layer Fig. 20: 360 and the p-type layer Fig. 20: 358 (para. [0144]), the active LED structure Fig. 20: 356 forming a mesa with mesa sidewalls that define a perimeter of the active LED structure Fig. 20: 356 (annotated);
a reflective structure Fig. 20: 366+368 between the active LED structure Fig. 20: 356 and the carrier submount Fig. 20: 354; and
a passivation layer Fig. 20: 380+396 between the reflective structure Fig. 20: 366+368 and the carrier submount Fig. 20: 354, a portion of the passivation layer Fig. 20: 406 laterally extending past the mesa sidewalls such that the mesa sidewalls are bounded by the passivation layer Fig. 20: 380+396 (shown in Fig. 20);
a barrier layer Fig. 20: 386 arranged between the carrier submount Fig. 20: 354 and the passivation layer Fig. 20: 380+396 (portion 380), wherein the barrier layer Fig. 20: 386 is electrically coupled to the reflective structure (via 398); and
a contact Fig. 20: 400 electrically coupled to the barrier layer Fig. 20: 386 (via 402) outside the mesa sidewalls,
wherein the contact extends through the portion of the passivation layer laterally extending past the mesa sidewalls.
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Donofrio teaches the following claim limitations not disclosed by Williams:
wherein the contact Fig. 4: 82 extends through the portion of the passivation layer Fig. 4: 60 laterally extending past the mesa sidewalls (para. 0073).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Williams with Donofrio in order to apply an electrical signal to the p-type layer (para. 0073).
Regarding claim 2, Williams teaches the LED chip of claim 1, wherein the barrier layer Fig. 20: 386 is electrically coupled to the reflective structure by a number of barrier interconnects Fig. 20: 398 that extend through the passivation layer Fig. 20: 380+396 (electrically coupled via interconnect 398, and passes through passivation layer at 380).
Regarding claim 4, Williams teaches the LED chip of claim 2, wherein the reflective structure Fig. 20: 366+368 comprises a dielectric layer Fig. 20: 366 (para. 0111) and a metal layer Fig. 20: 368 (para. 0114) on the active LED structure Fig. 20: 356 and the dielectric layer Fig. 20: 366 is arranged between the metal layer Fig. 20: 368 and the active LED structure Fig. 20: 356, wherein the barrier interconnects Fig. 20: 398 are electrically coupled to the metal layer Fig. 20: 368 (via interconnect 398).
Regarding claim 5, Williams teaches the LED chip of claim 4, further comprising reflective layer interconnects Fig. 20: 374 that extend from the metal layer Fig. 20: 368 and through the dielectric layer Fig. 20: 366 (para. 0116, shown in Fig. 20).
Regarding claim 6, Williams teaches the LED chip of claim 5, wherein the barrier interconnects Fig. 20: 398 are laterally offset from the reflective layer interconnects Fig. 20: 374.
Regarding claim 8, Williams teaches the LED chip of claim 2:
wherein the mesa sidewalls are formed by a portion of the n-type layer Fig. 20: 360, and
the passivation layer contacts a portion the n-type layer that laterally extends past the active layer and the p-type layer proximate the mesa sidewalls.
In a different embodiment (Fig. 11), Williams teaches:
the passivation layer Fig. 11: 218 contacts a portion the n-type layer Fig. 11: 202 that laterally extends past the active layer and the p-type layer Fig. 11: 204 proximate the mesa sidewalls.
Williams teaches another passivation layer 218 that is used to further protect the components of the device from moisture.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify these two embodiments in order to provide favorable moisture resistive characteristics, providing physical protection to the underlying components (para. 0080).
Regarding claim 9, Williams teaches the LED chip of claim 8, further comprising a top passivation layer Fig. 20: 406 on a portion of the active LED structure Fig. 20: 356 such that a portion of the n-type layer Fig. 20: 360 is between the top passivation layer Fig. 20: 406 and the carrier submount Fig. 20: 354, wherein the top passivation layer Fig. 20: 406 further extends on the mesa sidewalls and contacts the portion of the passivation layer Fig. 20: 380+396 that laterally extends past the mesa sidewalls such that the mesa sidewalls are bounded by the top passivation layer Fig. 20: 406 and the passivation layer Fig. 20: 380+396.
Regarding claim 10, Williams teaches a light-emitting diode (LED) chip Fig. 20: 350, comprising:
a carrier submount Fig. 20: 354;
an active LED structure Fig. 20: 356 on the carrier submount Fig. 20: 354, the active LED structure Fig. 20: 356 comprising an n-type layer Fig. 20: 360, a p-type layer Fig. 20: 358, and an active layer Fig. 20: 362 arranged between the n-type layer Fig. 20: 360 and the p-type layer Fig. 20: 358, the active LED structure Fig. 20: 356 forming a mesa with mesa sidewalls that define a perimeter of the active LED structure Fig. 20: 356;
a passivation layer Fig. 20: 380+396, comprising silicon nitride
the passivation layer Fig. 20: 380+396 laterally extending past the mesa sidewalls such that the mesa sidewalls are bounded by the passivation layer Fig. 20: 380+396;
a barrier layer Fig. 20: 386 arranged between the carrier submount Fig. 20: 354 and the passivation layer Fig. 20: 380+396 (portion 380), the barrier layer Fig. 20: 386 forming a portion of an electrically conductive path to the active LED structure (para. 0127); and
a contact Fig. 20: 400 electrically coupled to the barrier layer Fig. 20: 386 (via 402) outside the mesa sidewalls,
the contact extending through the passivation layer to contact the barrier layer.
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Donofrio teaches the following claim limitations not disclosed by Williams:
a passivation layer Fig. 4: 60 comprising silicon nitride (para. 0057).
contact Fig. 4: 82 extends through the portion of the passivation layer Fig. 4: 60 laterally extending past the mesa sidewalls (para. 0073).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Williams with Donofrio in order to use the contact to apply an electrical signal to the p-type layer (para. 0073), and to ensure a passivation layer of SiN with an excellent ability to promote total internal reflection allowing for efficient reflection of active structure light, improving emission (para. 0056) and further control moisture permeability (para. 0085).
Regarding claim 11, Williams teaches the LED chip of claim 10, further comprising a top passivation layer Fig. 20: 406 on a portion of the active LED structure Fig. 20: 356 such that a portion of the n-type layer Fig. 20: 360 is between the top passivation layer Fig. 20: 406 and the carrier submount Fig. 20: 354, wherein the top passivation layer Fig. 20: 406 further extends on the mesa sidewalls and contacts the portion of the passivation layer Fig. 20: 380 that laterally extends past the mesa sidewalls.
Regarding claim 12, Williams teaches the LED chip of claim 10, further comprising a reflective structure Fig. 20: 366+368 between the active LED structure Fig. 20: 356 and the carrier submount Fig. 20: 354, wherein a portion of the passivation layer Fig. 20: 380 is between the reflective structure Fig. 20: 366+368 and the barrier layer Fig. 20: 386.
Regarding claim 13, Williams teaches the LED chip of claim 12, wherein the reflective structure comprises a dielectric layer Fig. 20: 366 (para. 0111) and a metal layer Fig. 20: 368 (para. 0114) on the active LED structure Fig. 20: 356 and a number of reflective layer interconnects Fig. 20: 374 that extend from the metal layer Fig. 20: 368 to form electrically conductive paths through the dielectric layer Fig. 20: 366 (para. 0116, shown in Fig. 20), the barrier layer Fig. 20: 386 is electrically coupled to the reflective structure Fig. 20: 366+368 by a number of barrier interconnects Fig. 20: 398 that extend through the passivation layer Fig. 20: 380, and the barrier interconnects Fig. 20: 398 are laterally offset from the reflective layer interconnects Fig. 20: 374.
Regarding claim 17, Williams discloses the LED chip of claim 16 further comprising:
a contact Fig. 20: 400 electrically coupled to the barrier layer Fig. 20: 386 (via 402; para. 0145) outside the mesa sidewalls,
wherein the contact extends through the passivation layer and the top passivation layer.
Donofrio teaches the following claim limitations not disclosed by Williams:
wherein the contact Fig. 4: 82 extends through the passivation layer Fig. 4: 60 and the top passivation layer Fig. 4: 88 (para. 0073).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Williams with Donofrio in order to apply an electrical signal to the p-type layer (para. 0073).
Response to Arguments
Applicant’s arguments, see Remarks, filed 04/02/2026, with respect to the rejection(s) of claim(s) 1, 10, and 14 have been fully considered. Upon further consideration of the amended claims, a new ground(s) of rejection is made in view of Williams et al. (US 20200365782) and Donofrio (US 20160211420).
Regarding claim 1, Applicant’s argument that the passivation layer noted in the previous office action was an improper combination of the passivation layer 380 and passivation layer 406 has been assessed. Examiner has amended passivation layer accordingly.
Other relevant prior art not used in this rejection includes: Kim et al. (US 20170198711).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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