Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 3394-607
Filling Date: 4/18/23
Priority Date: 06/01/2022
Inventor: Check et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shioji (US 2017/0331009 A1).
Regarding claim 1, Shioji discloses a light-emitting diode (LED) chip (Fig. 1), comprising: an active LED structure 2 (Para. 29) comprising an n-type layer 21, a p-type layer 23, and an active layer 22 that is between the n-type layer 21 and the p-type layer 23; a current spreading layer 4 (Para. 122) on the active LED structure 2, the current spreading layer 4 forming a first region (portion around 11) of the current spreading layer 4 and a second region (portion underneath 62) of the current spreading layer 4, the first region (portion around 11) being discontinuous with the second region (portion around 11, Fig. 1); a dielectric reflector layer 61, 51 (Para. 45) on the current spreading layer 4, wherein portions of the dielectric reflector layer 51, 61 extend through the current spreading layer 4 to the active LED structure 2; and an n-contact interconnect 31 (Para. 122) arranged to contact a portion of the n-type layer 21, wherein the first region (portion around 11) of the current spreading layer 4 is closer to the n-contact interconnect 31 than the second region (portion underneath 62) of the current spreading layer 4, and the first region (portion around 11) of the current spreading layer 4 comprises a larger area than the second region (portion underneath 62) of the current spreading layer 4 (Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14, 15-16, 17-19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (US 2021/0066549 A1) in view of Shioji (US 2017/0331009 A1).
Regarding claim 1, Liu discloses a light-emitting diode (LED) chip (Fig. 13, see annotated figure 13), comprising: an active LED structure 120 (Para. 24) comprising an n-type layer 121 (Para. 24), a p-type layer 123 (Para. 24), and an active layer 122 (Para. 49) that is between the n-type layer 121 and the p-type layer 123; a current spreading layer 130 (Para. 26) on the active LED structure 120; and a dielectric reflector layer 141 (Para. 28) on the current spreading layer 130, wherein portions of the dielectric reflector layer 141 extend through the current spreading layer 130 to the active LED structure 120;
Liu does not explicitly discloses the current spreading layer forming a first region of the current spreading layer and a second region of the current spreading layer, the first region being discontinuous with the second region; and an n-contact interconnect arranged to contact a portion of the n-type layer, wherein the first region of the current spreading layer is closer to the n-contact interconnect than the second region of the current spreading layer, and the first region of the current spreading layer comprises a larger area than the second region of the current spreading layer.
However, Shioji discloses the current spreading layer 4 (Fig. 1, Para. 122) forming a first region (portion around 11) of the current spreading layer 4 and a second region (portion underneath 62) of the current spreading layer 4, the first region being discontinuous with the second region (Fig. 1); and an n-contact interconnect 31 (Para. 122) arranged to contact a portion of the n-type layer 21, wherein the first region (portion around 11) of the current spreading layer 4 is closer to the n-contact interconnect 31 than the second region (portion underneath 62) of the current spreading layer 4, and the first region (portion around 11) of the current spreading layer 4 comprises a larger area than the second region (portion underneath 62) of the current spreading layer (Fig. 1).
Shioji teaches the above modification is used to improve emission power of the device (Para. 123). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Liu current spreading layer with Shioji current spreading layer as suggested above to improve emission power of the device (Para. 123).
Regarding claim 2, Liu further discloses the LED chip of claim 1, wherein the current spreading layer 130 comprises indium tin oxide (Para. 26) and the dielectric reflector layer 141 comprises silicon dioxide (Para. 28).
Regarding claim 3, Liu further discloses the LED chip of claim 1, further comprising a metal reflector layer 151 (Para. 33) on the dielectric reflector layer 141 and a plurality of reflective layer 151 (via portions that directly connected to the 130) interconnects that extend from the metal reflector layer 151 (top portion) and through the dielectric reflector layer 141.
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Regarding claim 4, Liu further discloses the LED chip of claim 3, wherein the plurality of reflective layer 151 (via portions that directly connected to the 130) interconnects contact portions of the current spreading layer 130.
Regarding claim 5, Liu further discloses the LED chip of claim 4, wherein the current spreading layer forms a plurality of openings 161 of the current spreading layer 130 and the plurality of openings define a plurality of discontinuous regions of the current spreading layer 130.
Regarding claim 6, Liu further discloses the LED chip of claim 5, wherein the plurality of reflective layer 151 (via portions that directly connected to the 130) interconnects contact the plurality of discontinuous regions of the current spreading layer 130 (Fig. 13).
Regarding claim 7, Liu further discloses the LED chip of claim 4, wherein the current spreading layer forms a plurality of openings 161 of the current spreading layer 130 and the plurality of openings define a plurality of regions of the current spreading layer (Fig. 13) that are connected by extensions 141 of the current spreading layer 130.
Regarding claim 8, Liu further discloses the LED chip of claim 1, wherein edges of the current spreading layer 130 are laterally spaced from the n-contact interconnect 173 (Fig. 13).
Regarding claim 9, Liu further discloses the LED chip of claim 8, wherein the edges of the current spreading layer 130 form a non-circular shape about a periphery of the n-contact interconnect 173.
Regarding claim 10, Liu discloses a light-emitting diode (LED) chip (Fig. 13, see annotated figure 13), comprising: an active LED structure 120 (Para. 24) comprising an n-type layer 121, a p-type layer 123, and an active layer 122 that is between the n-type layer 121 and the p-type layer 123; a plurality of current spreading regions 130 (Para. 26) on the active LED structure 120, each current spreading region 130 of the plurality of current spreading regions being discontinuous with other current spreading regions (Fig. 13) of the plurality of current spreading regions; a dielectric reflector layer 141 (Para. 28) on the plurality of current spreading regions 130; and a metal reflector layer 151 (Para. 33) on the dielectric reflector layer 141 and electrically coupled to the plurality of current spreading regions 130 by a plurality of reflective layer interconnects (see annotated figure) that extend from the metal reflector layer 151 and through the dielectric reflector layer 141.
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Liu does not explicitly disclose sizes of individual current spreading regions of the plurality of current spreading regions vary across the active LED structure.
However, Shioji discloses sizes of individual current spreading regions 4 (Fig. 1, Para. 122) of the plurality of current spreading regions 4 (portion around 11, portion under 62) vary across the active LED structure 2 (Para. 29).
Shioji teaches the above modification is used to improve emission power of the device (Para. 123). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Liu current spreading layer with Shioji current spreading layer as suggested above to improve emission power of the device (Para. 123).
Regarding claim 11, Liu further discloses the LED chip of 10, wherein each current spreading region 130 of the plurality of current spreading regions is electrically coupled to the metal reflector layer 151 by a single reflective layer interconnect 151 (top portion) of the plurality of reflective layer interconnects (see annotated figure).
Regarding claim 12, Liu further discloses the LED chip of claim 11, wherein the reflective layer interconnects (see annotated figure) comprise a same material as the metal reflector layer (same layer, Para. 33).
Regarding claim 13, Liu further discloses the LED chip of claim 12, wherein portions of the dielectric reflector layer 141 extend between adjacent current spreading regions 130 of the plurality of current spreading regions 130.
Regarding claim 14, Liu further discloses the LED chip of claim 13, wherein the portions of the dielectric reflector layer 141 contact the active LED structure 120 between the adjacent current spreading regions 130 of the plurality of current spreading regions (Fig. 13).
Regarding claim 17, Liu further discloses the LED chip of claim 10, wherein each current spreading region of the plurality of current spreading regions 130 forms a shape of a square (Fig. 13), a rectangle, an oval, a hexagon, or an octagon.
Regarding claim 18, Liu further discloses the LED chip of claim 10, wherein diameters of individual reflective layer interconnects 151 (see annotated figure) of the plurality of reflective layer interconnects vary across the active LED structure 120.
Regarding claims 15 and 16, Liu does not explicitly disclose the LED chip of claim 10, wherein each current spreading region of the plurality of current spreading regions forms a circular shape; the LED chip of claim 15, wherein a diameter of each circular shape is greater than a diameter of each reflective layer interconnect of the plurality of reflective layer interconnects.
However, Liu discloses a particular shape and diameter for the current spreading regions 130 and reflective layer interconnect 151 (Fig. 13).
Therefore, it would have been obvious to one of the ordinary skill of the at before the effective filling date of the claimed invention to each current spreading region of the plurality of current spreading regions forms a circular shape; the LED chip of claim 15, wherein a diameter of each circular shape is greater than a diameter of each reflective layer interconnect of the plurality of reflective layer interconnects for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the diameter and shape.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed diameter and shape or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 19, Liu further discloses the LED chip of claim 10, further comprising an n-contact interconnect 173 (Para. 46) arranged to extend through the plurality of current spreading regions 130, the p-type layer 123, and the active layer 122 to electrically couple with the n-type layer 121, wherein: the plurality of reflective layer 151 interconnects comprises a first reflective layer interconnect 151 (see three reflective layer interconnects annotated figure 13) and a second reflective layer interconnect 151 (see three reflective layer interconnects annotated figure 13); the first reflective layer interconnect 151 (left most one) is positioned closer to the n-contact interconnect 173 (left most one) than the second reflective layer interconnect 151 (right most one).
Liu does not explicitly disclose in figure 13 that a diameter of the first reflective layer interconnect is larger than a diameter of the second reflective layer interconnect.
Liu does not explicitly disclose a diameter of the first reflective layer interconnect 163 is larger than a diameter of the second reflective layer interconnect.
However, Liu discloses a diameter of the first reflective layer interconnect 163 is larger than a diameter of the second reflective layer interconnect 162 (Fig. 4, Paras. 29, 30).
Therefore, it would have been obvious to one of the ordinary skill of the at before the effective filling date of the claimed invention to obtain a diameter of the first reflective layer interconnect is larger than a diameter of the second reflective layer interconnect for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the diameter.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed diameter or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 20, Liu further discloses the LED chip of claim 10, further comprising an n-contact interconnect 173 arranged to extend through the plurality of current spreading regions 130, the p-type layer 123, and the active layer 122 to electrically couple with the n-type layer 121, wherein: the plurality of current spreading regions 130 comprise a first current spreading region 130 (left most one) and a second current spreading region 130 (right most one) such that the first current spreading region is closer to the n-contact interconnect 173 than the second current spreading region 130 (right most one).
Liu does not explicitly disclose a diameter of the first current spreading region is larger than a diameter of the second current spreading region.
However, Liu discloses a particular diameter for the current spreading regions 130 (Fig. 13).
Therefore, it would have been obvious to one of the ordinary skill of the at before the effective filling date of the claimed invention to obtain a diameter of the first current spreading region is larger than a diameter of the second current spreading region for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the diameter.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed diameter or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (US 2021/0066549 A1) in view of Kuo et al (US 2017/0155018 A1).
Regarding claim 10, Liu discloses a light-emitting diode (LED) chip (Fig. 13, see annotated figure 13), comprising: an active LED structure 120 (Para. 24) comprising an n-type layer 121, a p-type layer 123, and an active layer 122 that is between the n-type layer 121 and the p-type layer 123; a plurality of current spreading regions 130 (Para. 26) on the active LED structure 120, each current spreading region 130 of the plurality of current spreading regions being discontinuous with other current spreading regions (Fig. 13) of the plurality of current spreading regions; a dielectric reflector layer 141 (Para. 28) on the plurality of current spreading regions 130; and a metal reflector layer 151 (Para. 33) on the dielectric reflector layer 141 and electrically coupled to the plurality of current spreading regions 130 by a plurality of reflective layer interconnects (see annotated figure) that extend from the metal reflector layer 151 and through the dielectric reflector layer 141.
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Liu does not explicitly disclose sizes of individual current spreading regions of the plurality of current spreading regions vary across the active LED structure.
However, Kuo discloses sizes of individual current spreading regions 108 (Fig. 2, Para. 27) of the plurality of current spreading 108 vary across the active LED structure 103 (Para. 23).
Kuo teaches the above modification is used to improve electrical connection of the device (Para. 28). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Liu current spreading layer with Kuo current spreading layer as suggested above to improve electrical connection of the device (Para. 28).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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