DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 and 221-33 in the reply filed on 1/12/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7, 21-22, and 27-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (US 2022/0254756) (“Choi”).
With regard to claim 1, fig. 5 of Choi disclose a semiconductor die package, comprising: a first semiconductor die (530, 540), comprising: a first device region 530; one or more trench capacitor structures (“trench-type capacitor”, par [0110]) in the first device region 530; a first interconnect region 540 vertically adjacent with the first device region 530; an inductor region L included in the first interconnect region 540, wherein the inductor region L comprises one or more inductor structures L; and a second semiconductor die 570 bonded with the first semiconductor die (530, 540) at a bonding region 580 between the first interconnect region 540 and a second interconnect region (bottom of 572) of the second semiconductor die 570, wherein the second semiconductor die 570 comprises: a second device region 572; one or more semiconductor logic devices 572 included in the second device region 572; and the second interconnect region (bottom of 572) vertically adjacent with the second device region 572.
With regard to claims 2, 22, and 29, fig. 5 of Choi disclose a trench capacitor structure C of the one or more trench capacitor structures C, an inductor structure L of the one or more inductor structures L, and at least a subset of the one or more semiconductor logic devices 572 are included in a voltage regulator (“voltage regulator”, abstract) circuit of the semiconductor die package (“semiconductor package”, par [0090]).
With regard to claims 7 and 27, fig. 5 of Choi disclose that the one or more trench capacitor structures C and the one or more inductor structures L are electrically connected in the first interconnect region 540 of the first semiconductor die 530.
With regard to claim 21, fig. 5 of Choi disclose a semiconductor die package, comprising: an inductor-capacitor (LC) semiconductor die (530, 540), comprising: a first device region 530; one or more trench capacitor structures (“trench-type capacitor”, par [0110]) in the first device region 530; a first interconnect region 540 vertically adjacent with the first device region 530; an inductor region L included in the first interconnect region 540, wherein the inductor region L comprises one or more inductor structures L; and a logic semiconductor die 570 bonded with the LC semiconductor die (530, 540) at a bonding region 580 between the first interconnect region 540 and a second interconnect region (bottom of 572) of the second semiconductor die 570, wherein the second semiconductor die 570 comprises: a second device region 572; one or more semiconductor logic devices 572 included in the second device region 572; and the second interconnect region (bottom of 572) vertically adjacent with the second device region 572.
With regard to claim 28, fig. 5 of Choi disclose a semiconductor die package, comprising: a first semiconductor die (530, 540), comprising: a first device region 530; one or more trench capacitor structures (“trench-type capacitor”, par [0110]) in the first device region 530; an inductor region L included in the first interconnect region 540, wherein the inductor region L comprises one or more inductor structures L; a first interconnect region 540 vertically adjacent with the first device region 530; and a second semiconductor die 570 bonded with the first semiconductor die (530, 540) at a bonding region 580 between the first interconnect region 540 and a second interconnect region (bottom of 572) of the second semiconductor die 570, wherein the second semiconductor die 570 comprises: a second device region 572; one or more semiconductor logic devices 572 included in the second device region 572; and the second interconnect region (bottom of 572) vertically adjacent with the second device region 572.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 26, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2022/0254756) (“Choi”) in view of Zhang et al. (US 2023/0353049) (“Zhang”).
With regard to claims 6, 26, and 33, fig. 5 of Choi disclose that the one or more semiconductor logic devices 572 comprise: a plurality of semiconductor transistor structures 572.
Choi does not disclose a pulse width modulation (PWM) circuit.
However, fig. 1 of Zhang disclose a pulse width modulation (PWM) circuit 20.
Therefore, it would have been obvious to one of ordinary skill in the art to form the controller of Choi with the PWM controller as taught in Zhang in order to provide a switching regulator. See par [0005] of Zhang.
Allowable Subject Matter
Claims 3-5, 23-25, and 30-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
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