02610Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of claims 8-20 in the reply filed on 10/23/25 is acknowledged.
Claim Objections
Claim 21 is objected to because of the following informalities: the limitation “pluralities” in line 6 of claim 21 appears to be a typographical error. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Caplet, EP 2075224.
Regarding claim 19, Caplet discloses (figs. 1-5 and related text) a method for manufacturing a structure, the method comprising: forming, in a first die, a first recess (cavity 110 left side); forming, in the first recess, a first antistiction bump (116/118); forming, in a second die, a second recess (cavity right side); and coupling the first die to the second die by coupling regions (fig. 5), the first and the second recesses form, together, a cavity which contains the first antistiction bump (116/118).
Regarding claim 20, Caplet discloses in the second recess, a second (cavity 110 on the right) antistiction bump (118/116), wherein the cavity contains the second antistiction bump (118/116).
Allowable Subject Matter
Claims 8-18 and 21-27 are allowed.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination at least the limitation “at a second surface region of the semiconductor body, contiguous to said first surface region, at least one second columnar portion having a second value of base area different from the first value of base area; epitaxially growing, above said first and second columnar portions and said first trenches, a membrane layer of semiconductor material; and annealing that causes the migration of the semiconductor material of said first and second columnar portions concurrently forming: a buried cavity in the semiconductor body below the membrane layer, internally delimited by a first wall, a second wall opposite to the first wall, and third and fourth walls coupled between the first wall with the second wall; and at least one first antistiction bump, completely contained in the cavity, protruding from one of the first wall and the second wall” is the first major difference and the second difference is the limitation “a plurality of first columns surrounded by a plurality of first trenches, each first column having a first base area; forming, in the first surface, a plurality of second columns surrounded by a plurality of second trenches, each second column having a second base area greater than the first base area; forming a first membrane layer on the first surface and the first and second plurality of columns; and forming a cavity in the semiconductor substrate, the forming the cavity including: a first wall on the first membrane layer, the first wall including a first antistiction bump; and a second wall opposite the first wall, the second wall including a second antistiction bump” as recited in claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811