Prosecution Insights
Last updated: October 02, 2026
Application No. 18/302,905

DISPLAY DEVICE AND METHOD OF PROVIDING THE SAME

Non-Final OA §103
Filed
Apr 19, 2023
Priority
Jul 15, 2022 — RE 10-2022-0087849
Examiner
NICELY, JOSEPH C
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
628 granted / 808 resolved
+9.7% vs TC avg
Strong +20% interview lift
Without
With
+19.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
839
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
51.9%
+11.9% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
20.4%
-19.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 808 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office action is in response to the RCE filed 6/9/2026 with claims filed 8/25/2026. Claims 1-29 are pending with claims 1-4 and 11 presented for examination and claims 5-10 and 12-29 remaining withdrawn. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2020/0342806 and Kim hereinafter) in view of Okigawa et al (US 2018/0366680 and Okigawa hereinafter) in view of Sakakura et al (US 2002/0153831 and Sakakura hereinafter). As to claims 1-4 and 11: Kim discloses [claim 1] a display device (Fig. 9) comprising: a substrate (SUB; [0061]) comprising a display area (DA; [0062]) including a light emission area (area defined by overlap of PE, EML, and CE; [0115]), and a non-emission area (defined by area of PDL; [0117]) which is adjacent to the light emission area (area defined by overlap of PE, EML, and CE); a circuit array layer (comprising 10, TR, 20, and 30; [0107]-[0113]) on the substrate (SUB), wherein the circuit array layer comprises: a pixel driving circuit (comprising IE, OP, GE, and OE within CH2; [0105]); a first planarization layer (upper half of 20 that can provide a flat surface; [0109]) on the pixel driving circuit (comprising IE, OP, GE, and OE within CH2) and comprising an organic insulating material (20 can be organic material; [0109]); an anode connection electrode (OE on top of 20; [0110]) on the first planarization layer (upper half of 20) and connected to the pixel driving circuit (through OE within CH2; [0110]); and a second planarization layer (30 can provide a flat surface; [0113]) on the first planarization layer (upper half of 20), on the anode connection electrode (OE on top of 20), and comprising an organic insulating material (30 can be organic material; [0113]), and a light emitting array layer (comprising PE, EML, CE, and PDL; [0115]) on the circuit array layer (comprising 10, TR, 20, and 30), wherein the light emitting array layer comprises (comprising PE, EML, CE, and PDL): an anode electrode (PE; [0116]) on the second planarization layer (30), corresponding to the light emission area (area defined by overlap of PE, EML, and CE), and connected (through CH3; [0116]) to the anode connection electrode (OE on top of 20); a pixel defining layer (PDL; [0115]) on the second planarization layer (30), corresponding to the non-emission area (defined by area of PDL), overlapping an edge (left edge; [0117]) of the anode electrode (PE); a light emitting layer (EML; [0117]) on the anode electrode (PE); and a cathode electrode (CE; [0118]) on the pixel defining layer (PDL) and the light emitting layer (EML), and corresponding to the light emission area (area defined by overlap of PE, EML, and CE), wherein each of the first planarization layer (upper half of 20) and the pixel defining layer (PDL) forms an interface (area where top surface of 20 and bottom surface of 30 are in contact is an interface and an area where bottom surface of PDL and top surface of 30 are in contact is an interface) with the second planarization layer (30); [claim 2] wherein the light emitting array layer (comprising PE, EML, CE, and PDL) further comprises: a first common layer (hole transport layer; [0119]) between the anode electrode (PE) and the light emitting layer (EML); and a second common layer (electron transport layer; [0119]) between the light emitting layer (EML) and the cathode electrode (CE); [claim 11] wherein the pixel driving circuit (comprising IE, OP, GE, and OE within CH2; [0105]) includes a transistor (comprising IE, OP, GE, and OE within CH2), the transistor comprising a semiconductor layer (OP; [0105]) on the substrate (SUB), a gate electrode (GE; [0105]), and a gate insulating layer (10; [0106]-[0108]) between the semiconductor layer (OP) and the gate electrode (GE), and the pixel driving circuit (comprising IE, OP, GE, and OE within CH2) further includes an interlayer insulating layer (lower half of 20; [0104]) facing the substrate (SUB) with the transistor (specifically portions GE, 10, and OP) therebetween. Kim fails to expressly disclose [claim 1] where the pixel driving circuit corresponding to the light emission area. Okigawa discloses [claim 1] where the pixel driving circuit (Fig. 3; comprising TR2; [0051]) corresponding to the light emission area (area defined by overlap of 132, 133, and 134). A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the location of the driving circuit/transistor to be that of Okigawa, where it is within the light emission area, instead of that of Kim, where it is within the non-emission area since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case the two locations of where to place the driving circuit; if this leads to the anticipated success, in the instant case a circuit that can control the light emission structure, it is likely the product not of innovation but of ordinary skill. Kim in view of Okigawa fail to expressly disclose where the pixel defining layer [claim 1] comprising an organic insulating material; wherein a layer among the first planarization layer, the second planarization layer and the pixel defining layer comprises a gas blocking thickness portion which extends from a surface of the layer which is closest to the cathode electrode; [claim 3] wherein the pixel defining layer comprises: the surface which is closest to the cathode electrode, and the gas blocking thickness portion is in contact with the second common layer; [claim 4] wherein the pixel defining layer further comprises: a surface which is closest to the substrate, and oxygen within the gas blocking thickness portion less than oxygen at the surface which is closest to the substrate. Sakakura discloses in Figs. 6B and 8 a display device where the pixel defining layer (947; [0131]) [claim 1] comprising an organic insulating material (947 can be an organic resin; [0132]); wherein a layer among the first planarization layer, the second planarization layer and the pixel defining layer (947) comprises a gas blocking thickness portion (the top surface of 947 is subjected to plasma processing and is shown as having slanted lines in the Figure, which reduces gas emissions from the organic resin material; [0133]) which extends from a surface of the layer (top surface of 947) which is closest to the cathode electrode (950; [0105]); [claim 3] wherein the pixel defining layer (947) comprises: the surface (the top surface of 947 is subjected to plasma processing and is shown as having slanted lines in the Figure) which is closest to the cathode electrode (950); [claim 4] wherein the pixel defining layer (950) further comprises: a surface (bottom surface of 947) which is closest to the substrate (900; [0072]), and oxygen within the gas blocking thickness portion (the top surface of 947 is subjected to plasma processing and is shown as having slanted lines in the Figure) less than oxygen (processing the surface of the pixel defining layer 947 using, for example a noble gas, reduces the amount of oxygen present in the area treated; [0133]) at the surface (bottom surface) which is closest to the substrate (601). Given the teachings of Sakakura, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Kim in view of Okigawa by employing the well-known or conventional features of display device fabrication, such as displayed by Sakakura, by employing plasma processing the top surface of the pixel defining layer that forms a gas blocking thickness that has reduced oxygen concentration relative to non-processed regions of the pixel defining layer in order to prevent moisture and gas from being generated from the inside from degrading the light-emitting device ([0133]). As to [claim 3] the gas blocking thickness portion is in contact with the second common layer, Okigawa discloses in Fig. 3 that the second common layer/electron transport layer 1334 can be in direct contact with the pixel defining layer 122, see [0081]. Using the light emitting structure of Okigawa where the second common layer is in direct contact with the pixel defining layer 122 and using the pixel defining layer 947 of Sakakura in the structure of Kim will result in the claimed structure. As all the claimed elements were known in the prior art and one of ordinary skill in the art before the effective filing date could have combined the elements as claimed by known methods (as disclosed by Kim, Okigawa, and Sakakura) with no change in their respective functions, and the combination would have yielded predictable results, namely a display device that has reduced degradation of the light emitting device caused by oxygen and water vapor within the pixel defining layer to one of ordinary skill in the art. Response to Arguments Applicant's arguments filed 8/25/2026 have been fully considered but they are not persuasive. In the remarks, applicant argues in substance that while layers 20, 30, and PDL of Kim may be considered as forming respective interfaces therebetween, Kim is silent as to a layer among layers 20, 30, and PDL as having a gas blocking thickness portion. Planarization layer 118 of Okigawa does not form an interface with bank 122. Organic film 935 of Sakakura does not form an interface with pixel defining layer 947. Sakakura teaches an inorganic layer 936 on organic film 935 to avoid degradation caused by moisture and gas. Sakakura provides no suggestion or motivation for choosing a layer from among interface-forming layers to have a glass blocking thickness portion. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Each reference was provided for a specific teaching, as shown in the rejection, and the combination of references as a whole teach the claimed limitations. Further, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In addition, Sakakura discloses in [0132] that organic insulating films, such as those in the Okigawa reference, occludes moisture and gas in the air, which are released due to heat generated by driving of a light-emitting element and causes degradation of the device. Sakakura then goes on to disclose in [0133] that in order to solve this specific problem, the organic insulating film 947, which is equated to the pixel defining layer PDL of Okigawa, is subjected to a plasma treatment to modify the top surface of the pixel defining layer 947 to have a gas blocking feature. Therefore, Sakakura provides an explicit teaching of providing a top surface of the pixel defining layer to have gas blocking feature and an explicit motivation for doing so. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JOSEPH C. NICELY Primary Examiner Art Unit 2813 /JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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Prosecution Timeline

Show 3 earlier events
Dec 23, 2025
Applicant Interview (Telephonic)
Dec 23, 2025
Examiner Interview Summary
Dec 31, 2025
Response Filed
Apr 09, 2026
Final Rejection mailed — §103
Jun 09, 2026
Request for Continued Examination
Jun 12, 2026
Response after Non-Final Action
Aug 25, 2026
Response Filed
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
98%
With Interview (+19.8%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 808 resolved cases by this examiner. Grant probability derived from career allowance rate.

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